; -------------------------------------------------------------------------------- ; @Title: KVx On-Chip Peripherals ; @Props: Released ; @Author: GAJ, TER, SZM, KOB, KMB, LUK, KOG, MKO, RAB, KRZ ; @Changelog: 2018-04-25 KMB ; 2019-04-25 RAB ; @Manufacturer: NXP- NXP Semiconductors ; @Doc: KV4XP100M168RM.pdf (Rev.3.2, 2015-09) ; KV10P48M75RM.pdf (Rev. 4, 2014-02) ; KV5XP144M240RM.pdf (Rev. 4, 2016-06) ; KV10P48M75RM_Rev7.pdf (Rev. 7, 2014-09) ; KV10P48M75_Rev4.pdf (Rev. 4, 2015-02) ; KV11P64M75RM.pdf (Rev. 4, 2017-05) ; KV11P64M75.pdf (Rev. 4, 2017-05) ; KV30P64M100SFA.pdf (Rev. 1, 2014-03) ; KV30P64M100SFARM.pdf (Rev. 2, 2016-02) ; KV31P100M100SF9_Rev7.pdf (Rev. 7, 2016-02) ; KV31P100M120SF8_Rev7.pdf (Rev. 7, 2016-02) ; KV31P100M100SF9RM_Rev4.pdf (Rev. 4, 2016-02) ; KV31P100M120SF8RM_Rev4.pdf (Rev. 4, 2016-02) ; KV31P100M120SF7_Rev7.pdf (Rev. 7, 2016-02) ; KV31P100M120SF7RM_Rev4.pdf (Rev. 4, 2016-02) ; KV4XP100M168RM_Rev4.pdf (Rev. 4, 2016-06) ; KV4XP100M168_Rev3.pdf (Rev. 3, 2016-06) ; @Core: Cortex-M0P, Cortex-M7F, Cortex-M4F ; @Chip: MKV10Z16VFM7, MKV10Z16VLC7, MKV10Z16VLF7, MKV10Z32VFM7, ; MKV10Z32VLC7, MKV10Z32VLF7, MKV30F128VFM10, MKV30F128VLH10, ; MKV30F64VFM10, MKV30F128VLF10, MKV30F64VLF10, MKV30F64VLH10, ; MKV31F128VLH10, MKV31F128VLL10, MKV31F256VLH12, MKV31F256VLL12, ; MKV31F512VLH12, MKV31F512VLL12, MKV56F1M0VLL24, MKV56F1M0VLQ24, ; MKV56F1M0VMD24, MKV56F512VLL24, MKV56F512VLQ24, MKV56F512VMD24, ; MKV58F1M0VLL24, MKV58F1M0VLQ24, MKV58F1M0VMD24, MKV58F512VLL24, ; MKV58F512VLQ24, MKV58F512VMD24, MKV10Z32VLC7R, MKV10Z32VFM7R, ; MKV10Z64VFM7, MKV10Z64VLF7, MKV10Z64VFM7P, MKV10Z128VFM7, ; MKV10Z128VLF7, MKV10Z128VLH7, MKV11Z128VFM7, MKV11Z128VFM7P, ; MKV11Z128VLF7, MKV11Z128VLF7P, MKV11Z128VLH7, MKV30F128VLF10P, ; MKV30F64VLF10R, MKV42F64VLF16, MKV42F64VLH16, MKV42F128VLF16, ; MKV46F256VLH16R, MKV11Z64VFM7, MKV11Z64VLF7, MKV11Z64VLH7, ; MKV11Z128VLH7P, MKV10Z64VLH7, MKV10Z64VLH7P, MKV31F256VLH12P, ; MKV31F256VLH12R, MKV31F512VLH12R, MKV31F512VLL12P, MKV31F128VLH10P ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perkinetisv.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif (CORENAME()=="CORTEXM0+") tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif (CORENAME()=="CORTEXM7F") tree.close "Core Registers (Cortex-M7F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes" bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes" bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes" textline " " bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes" textline " " bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes" bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" textline " " bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" textline "" group.long 0x10++0x03 line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x04 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" textline " " rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x13 line.long 0x00 "HFSR,HardFault Status Register" eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred" eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" line.long 0x10 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Memory System" width 10. rgroup.long 0xD78++0x0B line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..." bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." textline " " bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." line.long 0x04 "CTR,Cache Type Register" bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..." bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CCSIDR,Cache Size ID Register" bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU" line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)" line.long 0x08 "DCISW,Data cache invalidate by set/way" line.long 0x0C "DCCMVAU,Data cache by address to PoU" line.long 0x10 "DCCMVAC,Data cache clean by address to PoC" line.long 0x14 "DCCSW,Data cache clean by set/way" line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC" line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way" group.long 0xF90++0x13 line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register" bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register" bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "AHBPCR,AHBP control register" bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled" line.long 0x0C "CACR,L1 Cache Control Register" bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled" bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes" bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled" line.long 0x10 "AHBSCR,AHB Slave Control Register" bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion" bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI" group.long 0xFA8++0x03 line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register" bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred" bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred" group.long 0xFB0++0x03 line.long 0x00 "IEBR0,Instruction Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB4++0x03 line.long 0x00 "IEBR1,Instruction Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB8++0x03 line.long 0x00 "DEBR0,Data Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFBC++0x03 line.long 0x00 "DEBR1,Data Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM7F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" newline bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." newline bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." newline bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" newline if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" newline rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" newline bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" newline bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count register" line.long 0x08 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" newline group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end else tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif config 16. 8. sif cpuis("MKV1*") tree.open "PORT (Port Control And Interrupts)" tree "PORTA" base ad:0x40049000 width 13. group.long 0x00++0x13 line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "SWD_CLK,PTA0,UART0_CTS_b,FTM0_CH5,,EWM_IN,,SWD_CLK" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,UART0_CTS_b,FTM0_CH5,,,,SWD_CLK" endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM2_CH0,CMP0_OUT,FTM2_QD_PHA,FTM1_CH1,FTM4_CH0" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM2_CH0,CMP0_OUT,FTM2_QD_PHA,FTM1_CH1,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM2_CH1,CMP1_OUT,FTM2_QD_PHB,FTM1_CH0,FTM4_CH1" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM2_CH1,CMP1_OUT,FTM2_QD_PHB,FTM1_CH0,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "SWD_DIO,PTA3,UART0_RTS_b,FTM0_CH0,FTM2_FLT0,EWM_OUT_b,,SWD_DIO" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,UART0_RTS_b,FTM0_CH0,FTM2_FLT0,EWM_OUT_b,,SWD_DIO" endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "NMI_b,PTA4/LLWU_P3,,FTM0_CH1,FTM4_FLT0,FTM0_FLT3,,NMI_b" else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4/LLWU_P3,,FTM0_CH1,,FTM0_FLT3,,NMI_b" endif bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA5,,FTM0_CH2,FTM5_FLT0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x30++0x07 line.long 0x00 "PORTA_PCR12,Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA12,CAN0_TX,FTM1_CH0,,,,FTM1_QD_PHA" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR13,Pin Control Register 13" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA13/LLWU_P4,CAN0_RX,FTM1_CH1,,,,FTM1_QD_PHB" bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x48++0x0B line.long 0x00 "PORTA_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,FTM0_FLT2,FTM_CLKIN0,,FTM3_CH2,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,FTM0_FLT2,FTM_CLKIN0,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,FTM0_FLT0,FTM1_FLT0,FTM_CLKIN1,,LPTMR0_ALT1,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR20,Pin Control Register 20" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA20,,,,,,RESET_b" bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 29. " GPWE[13] ,Global pin 13 write enable" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" else bitfld.long 0x00 20. " GPWE[4] ,Global pin 4 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 20. " GPWE[20] ,Global pin 20 write enable" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x00 13. " GPWD13 ,Global pin 13 write data" "Low,High" newline bitfld.long 0x00 12. " GPWD13 ,Global pin 13 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x04 13. " GPWD13 ,Global pin 13 write data" "Low,High" newline bitfld.long 0x04 12. " GPWD12 ,Global pin 12 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 20. " ISF20 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") eventfld.long 0x00 13. " ISF13 ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 12. " ISF12 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" endif eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree "PORTB" base ad:0x4004A000 width 13. group.long 0x00++0x07 line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/ADC1_SE8,PTB0/LLWU_P5,I2C0_SCL,FTM1_CH0,,,FTM1_QD_PHA,UART0_RX" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/ADC1_SE9,PTB1,I2C0_SDA,FTM1_CH1,FTM0_FLT2,EWM_IN,FTM1_QD_PHB,UART0_TX" bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7") group.long 0x08++0x07 line.long 0x00 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE10/ADC1_SE10/ADC1_DM2,PTB2,I2C0_SCL,UART0_RTS_b,FTM0_FLT1,,FTM0_FLT3,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE2/ADC1_DP2,PTB3,I2C0_SDA,UART0_CTS_b,,,FTM0_FLT0,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") group.long 0x10++0x03 line.long 0x00 "PORTB_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE10/ADC1_SE10/ADC1_DM2,PTB2,I2C0_SCL,UART0_RTS_b,FTM0_FLT1,,FTM0_FLT3,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7") group.long 0x40++0x07 line.long 0x00 "PORTB_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,UART0_RX,FTM_CLKIN2,CAN0_TX,EWM_IN,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,UART0_RX,FTM_CLKIN2,,EWM_IN,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,UART0_TX,FTM_CLKIN1,CAN0_RX,EWM_OUT_b,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,UART0_TX,FTM_CLKIN1,,EWM_OUT_b,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") group.long 0x48++0x07 line.long 0x00 "PORTB_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB18,CAN0_TX,,FTM3_CH2,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB19,CAN0_RX,,FTM3_CH3,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VFM7") wgroup.long 0x80++0x03 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 19. " GPWE[3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" else bitfld.long 0x00 17. " GPWE[1] ,Global pin 1 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") wgroup.long 0x84++0x03 line.long 0x00 "PORTB_GPCHR,Global Pin Control High Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 19. " GPWE[19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" else bitfld.long 0x00 17. " GPWE[17] ,Global pin 17 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" endif else wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 Write Enable" "No,Yes" newline bitfld.long 0x00 16. " GPWE0 ,Global pin 0 Write Enable" "No,Yes" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" endif bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" newline bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 Write Enable" "No,Yes" newline bitfld.long 0x04 16. " GPWE16 ,Global pin 16 Write Enable" "No,Yes" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" newline bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" endif bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" newline endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "Not detected,Detected" newline endif sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" newline endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7") eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree "PORTC" base ad:0x4004B000 width 13. sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") group.long 0x00++0x03 line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE11,PTC0,SPI0_PCS4,PDB0_EXTRG0,,CMP0_OUT,FTM0_FLT0,SPI0_PCS0" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE11,PTC0,SPI0_PCS4,PDB0_EXTRG,,CMP0_OUT,FTM0_FLT0,SPI0_PCS0/SS_b" endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x1B line.long 0x00 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE3,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,FTM2_CH0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE11/CMP1_IN0,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,FTM2_CH1,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,FTM3_FLT0,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,?..." else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0/SS_b,UART1_TX,FTM0_CH3,,CMP1_OUT,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,FTM0_CH2" bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,,UART0_RX,,I2C0_SCL" bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,,,UART0_TX,,I2C0_SDA" bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") group.long 0x20++0x0B line.long 0x00 "PORTC_PCR8,Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE14/CMP0_IN2,PTC8,,FTM3_CH4,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR9,Pin Control Register 9" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE15/CMP0_IN3,PTC9,,FTM3_CH5,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR10,Pin Control Register 10" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE16,PTC10,,FTM5_CH0,FTM5_QD_PHA,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR11,Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE17,PTC11/LLWU_P11,,FTM5_CH1,FTM5_QD_PHB,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") wgroup.long 0x80++0x03 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Disabled,Enabled" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Disabled,Enabled" newline endif bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Disabled,Enabled" else bitfld.long 0x00 23. " GPWE[7] ,Global pin 5 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 22. " [6] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") newline bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" endif newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register" bitfld.long 0x04 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x04 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P") bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif endif group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") eventfld.long 0x00 11. " ISF11 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") newline eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif width 0x0B tree.end tree "PORTD" base ad:0x4004C000 width 13. sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") group.long 0x00++0x0F line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0,UART0_CTS_b,FTM0_CH0,UART1_RX,FTM3_CH0,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0/SS_b,UART0_CTS_b,FTM0_CH0,UART1_RX,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTD1,SPI0_SCK,UART0_RTS_b,FTM0_CH1,UART1_TX,FTM3_CH1,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE2,PTD1,SPI0_SCK,UART0_RTS_b,FTM0_CH1,UART1_TX,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART0_RX,FTM0_CH2,,FTM3_CH2,I2C0_SCL" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART0_RX,FTM0_CH2,,,I2C0_SCL" endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART0_TX,FTM0_CH3,,FTM3_CH3,I2C0_SDA" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART0_TX,FTM0_CH3,,,I2C0_SDA" endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x10++0x0F line.long 0x00 "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FTM2_CH0,EWM_IN,SPI0_PCS0" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FTM2_CH0,EWM_IN,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,FTM2_CH1,EWM_OUT_b,SPI0_SCK" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,FTM2_CH1,EWM_OUT_b,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE6,PTD6/LLWU_P15,FTM4_CH0,UART0_RX,FTM0_CH0,FTM1_CH0,FTM0_FLT0,SPI0_SOUT" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE6,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH0,FTM1_CH0,FTM0_FLT0,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,FTM4_CH1,UART0_TX,FTM0_CH1,FTM1_CH1,FTM0_FLT1,SPI0_SIN" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,,UART0_TX,FTM0_CH1,FTM1_CH1,FTM0_FLT1,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") wgroup.long 0x80++0x07 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" newline sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline endif hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif line.long 0x04 "PORTD_GPCHR,Global Pin Control High Register" bitfld.long 0x04 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x04 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif endif group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt status flag Register" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7") newline eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif width 0x0B tree.end tree "PORTE" base ad:0x4004D000 width 13. sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") group.long 0x00++0x07 line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE12,PTE0,,UART1_TX,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE13,PTE1/LLWU_P0,,UART1_RX,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x40++0x0F line.long 0x00 "PORTE_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1/ADC0_DP1/ADC1_SE0,PTE16,SPI0_PCS0,UART1_TX,FTM_CLKIN0,,FTM0_FLT3,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE1/ADC0_DP1/ADC1_SE0,PTE16,SPI0_PCS0/SS_b,UART1_TX,FTM_CLKIN0,,FTM0_FLT3,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_DM1/ADC0_SE5/ADC1_SE5,PTE17/LLWU_P19,SPI0_SCK,UART1_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5/ADC0_DM1/ADC1_SE5,PTE17,SPI0_SCK,UART1_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR18,Pin Control Register 18" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6/ADC1_SE1/ADC1_DP1,PTE18/LLWU_20,SPI0_SOUT,UART1_CTS_b,I2C0_SDA,,SPI0_SIN,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6/ADC1_SE1/ADC1_DP1,PTE18,SPI0_SOUT,UART1_CTS_b,I2C0_SDA,,SPI0_SIN,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR19,Pin Control Register 19" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE7/ADC1_SE7/ADC1_DM1,PTE19,SPI0_SIN,UART1_RTS_b,I2C0_SCL,,SPI0_SOUT,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7") group.long 0x50++0x07 line.long 0x00 "PORTE_PCR20,Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE0/ADC0_DP0,PTE20,,FTM1_CH0,UART0_TX,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR21,Pin Control Register 21" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE4/ADC0_DM0,PTE21,,FTM1_CH1,UART0_RX,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") group.long 0x58++0x07 line.long 0x00 "PORTE_PCR22,Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTE22,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR23,Pin Control Register 23" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTE23,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x60++0x07 line.long 0x00 "PORTE_PCR24,Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE24,CAN0_TX,FTM0_CH0,,I2C0_SCL,EWM_OUT_b,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTDE24,,FTM0_CH0,,I2C0_SCL,EWM_OUT_b,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR25,Pin Control Register 25" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE25/LLWU_P21,CAN0_RX,FTM0_CH1,,I2C0_SDA,EWM_IN,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTDE25,,FTM0_CH1,,I2C0_SDA,EWM_IN,?..." textfld " " endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7") group.long 0x74++0x03 line.long 0x00 "PORTE_PCR29,Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP1_IN5/CMP0_IN5,PTE29,,FTM0_CH2,,FTM_CLKIN0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x78++0x03 line.long 0x00 "PORTE_PCR30,Pin Control Register 30" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE4/CMP1_IN4/DAC0_OUT,PTE30,,FTM0_CH3,,FTM_CLKIN1,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") group.long 0x7C++0x03 line.long 0x00 "PORTE_PCR31,Pin Control Register 31" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14/CMP0_IN4,PTE31,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") wgroup.long 0x80++0x03 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 17. " GPWE[1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" endif wgroup.long 0x84++0x03 line.long 0x00 "PORTE_GPCHR,Global Pin Control High Register" sif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") sif !cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z64VLF7") bitfld.long 0x00 31. " GPWE[31] ,Global pin 31 write enable" "Disabled,Enabled" newline endif bitfld.long 0x00 30. " GPWE[30] ,Global pin 30 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Global pin 29 write enable" "Disabled,Enabled" else bitfld.long 0x00 30. " GPWE[30] ,Global pin 30 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 25. " [25] ,Global pin 25 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Global pin 24 write enable" "Disabled,Enabled" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 23. " [23] ,Global pin 23 write enable" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Global pin 22 write enable" "Disabled,Enabled" newline endif sif cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P") bitfld.long 0x00 21. " [21] ,Global pin 21 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Global pin 20 write enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x84++0x07 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 30. " GPWE30 ,Global pin 30 write enable" "No,Yes" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x00 29. " GPWE29 ,Global pin 29 write enable" "No,Yes" endif bitfld.long 0x00 25. " GPWE25 ,Global pin 25 write enable" "No,Yes" bitfld.long 0x00 24. " GPWE24 ,Global pin 24 write enable" "No,Yes" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x00 21. " GPWE21 ,Global pin 21 write enable" "No,Yes" bitfld.long 0x00 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" endif bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" line.long 0x04 "PORTE_GPCHR,Global Pin Control High Register" bitfld.long 0x04 30. " GPWE30 ,Global pin 30 write enable" "No,Yes" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "No,Yes" endif bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "No,Yes" bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "No,Yes" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7") bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "No,Yes" bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" endif bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" endif group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") eventfld.long 0x00 31. " ISF31 ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 30. " ISF30 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7") eventfld.long 0x00 29. " ISF29 ,Interrupt status flag" "Not detected,Detected" endif newline eventfld.long 0x00 25. " ISF25 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 24. " ISF24 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") eventfld.long 0x00 23. " ISF23 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 22. " ISF22 ,Interrupt status flag" "Not detected,Detected" endif newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7") eventfld.long 0x00 21. " ISF21 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 20. " ISF20 ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7") newline eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif width 0x0B tree.end tree.end tree "SIM (System Integration Module)" base ad:0x40047000 width 10. group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,,LPO 1kHz" base ad:0x40048000 group.long 0x04++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 24.--25. " FTMFFCLKSEL ,FTM fixed frequency clock select" "MCGFFCLK,MCGIRCLK,OSCERCLK,MCGFFCLK" bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Bus clock,LPO clock,MCGIRCLK,,OSCERCLK,?..." group.long 0x0C++0x07 line.long 0x00 "SOPT4,System Options Register 4" bitfld.long 0x00 28.--29. " FTM2CLKSEL ,FTM2 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." bitfld.long 0x00 26.--27. " FTM1CLKSEL ,FTM1 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." bitfld.long 0x00 24.--25. " FTM0CLKSEL ,FTM0 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." newline bitfld.long 0x00 22. " FTM2ICH1SRC ,FTM2 channel 1 input capture source select" "FTM2_CH1,FTM2_CH1 XOR FTM2_CH0 XOR FTM1_CH1" bitfld.long 0x00 20.--21. " FTM2ICH0SRC ,FTM2 channel 0 input capture source select" "FTM2_CH0,CMP0_OUT,CMP1_OUT,?..." bitfld.long 0x00 18.--19. " FTM1ICH0SRC ,FTM1 channel 0 input capture source select" "FTM1_CH0,CMP0_OUT,CMP1_OUT,?..." newline bitfld.long 0x00 15. " FTM2TRG2SRC ,FlexTimer 2 hardware trigger 2 source select" "HSCMP0,HSCMP1" bitfld.long 0x00 14. " FTM2TRG1SRC ,FlexTimer 2 hardware trigger 1 source select" "PDB1,FTM1" bitfld.long 0x00 13. " FTM2TRG0SRC ,FlexTimer 2 hardware trigger 0 source select" "HSCMP0,FTM0" newline bitfld.long 0x00 12. " FTM1TRG2SRC ,FlexTimer 1 hardware trigger 2 source select" "HSCMP0,HSCMP1" bitfld.long 0x00 11. " FTM1TRG1SRC ,FlexTimer 1 hardware trigger 1 source select" "PDB1,FTM2" bitfld.long 0x00 10. " FTM1TRG0SRC ,FlexTimer 1 hardware trigger 0 source select" "HSCMP0,FTM0" newline bitfld.long 0x00 9. " FTM0TRG2SRC ,FlexTimer 0 hardware trigger 2 source select" "HSCMP0,HSCMP1" bitfld.long 0x00 8. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB1,FTM2" bitfld.long 0x00 7. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "HSCMP0,FTM1" newline bitfld.long 0x00 3. " FTM2FLT0 ,FTM2 fault 0 select" "FTM2_FLT0,CMP0_OUT" bitfld.long 0x00 2. " FTM1FLT0 ,FTM1 fault 0 select" "FTM1_FLT0,CMP0_OUT" bitfld.long 0x00 1. " FTM0FLT1 ,FTM0 fault 1 select" "FTM0_FLT1,CMP1_OUT" newline bitfld.long 0x00 0. " FTM0FLT0 ,FTM0 fault 0 select" "FTM0_FLT0,CMP0_OUT" line.long 0x04 "SOPT5,System Options Register 5" bitfld.long 0x04 17. " UART1ODE ,UART1 open drain enable" "Disabled,Enabled" bitfld.long 0x04 16. " UART0ODE ,UART0 open drain enable" "Disabled,Enabled" bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..." newline bitfld.long 0x04 4.--5. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX-FTM1_CH0,UART1_TX-FTM2_CH0,?..." bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX,CMP0,CMP1,?..." bitfld.long 0x04 0.--1. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX,UART0_TX-FTM1_CH0,UART0_TX-FTM2_CH0,?..." sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") group.long 0x14++0x03 line.long 0x00 "SOPT6,System Options Register 6" bitfld.long 0x00 28.--29. " FTM5CLKSEL ,FTM5 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." bitfld.long 0x00 26.--27. " FTM4CLKSEL ,FTM4 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." bitfld.long 0x00 24.--25. " FTM3CLKSEL ,FTM3 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1,FTM_CLKIN2,?..." newline bitfld.long 0x00 20.--21. " FTM5CH0SRC ,FTM5 CH0 input capture source select" "FTM5_CH0,CMP0_OUT,CMP1_OUT,?..." bitfld.long 0x00 18.--19. " FTM4CH0SRC ,FTM4 CH0 input capture source select" "FTM4_CH0,CMP0_OUT,CMP1_OUT,?..." bitfld.long 0x00 15. " FTM5TRG2SRC ,FTM5 hardware trigger 2 source select" "CMP0_OUT,CMP1_OUT" newline bitfld.long 0x00 14. " FTM5TRG1SRC ,FTM5 hardware trigger 1 source select" "PDB1_OUT,FTM4" bitfld.long 0x00 13. " FTM5TRG0SRC ,FTM5 hardware trigger 0 source select" "CMP0_OUT,FTM3" bitfld.long 0x00 12. " FTM4TRG2SRC ,FTM4 hardware trigger 2 source select" "CMP0_OUT,CMP1_OUT" newline bitfld.long 0x00 11. " FTM4TRG1SRC ,FTM4 hardware trigger 1 source select" "PDB1_OUT,FTM5" bitfld.long 0x00 10. " FTM4TRG0SRC ,FTM4 hardware trigger 0 source select" "CMP0_OUT,FTM3" bitfld.long 0x00 9. " FTM3TRG2SRC ,FTM3 hardware trigger 2 source select" "CMP0_OUT,CMP1_OUT" newline bitfld.long 0x00 8. " FTM3TRG1SRC ,FTM3 hardware trigger 1 source select" "PDB1_OUT,FTM4" bitfld.long 0x00 7. " FTM3TRG0SRC ,FTM3 hardware trigger 0 source select" "CMP0_OUT,FTM5" bitfld.long 0x00 3. " FTM5FLT0 ,FTM5 fault 0 select" "FTM5_FLT0,CMP0_OUT" newline bitfld.long 0x00 2. " FTM4FLT0 ,FTM4 fault 0 select" "FTM4_FLT0,CMP0_OUT" bitfld.long 0x00 0. " FTM3FLT0 ,FTM3 fault 0 select" "FTM3_FLT0,CMP0_OUT" endif group.long 0x18++0x07 line.long 0x00 "SOPT7,System Options Register 7" bitfld.long 0x00 26.--27. " ADC1ALTCLKSRC ,ADC1 ALT clock source select" "OUTDIV5 output,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 24.--25. " ADC0ALTCLKSRC ,ADC0 ALT clock source select" "OUTDIV5 output,MCGIRCLK,OSCERCLK,?..." newline sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 14.--15. " ADC1ALTTRGEN ,ADC1 alternate conversion triggers enable" "PDB0_CH1,PDB1_CH1,ADC1TRGSEL,PDB0_CH1/PDB1_CH1" bitfld.long 0x00 12. " ADC1PRETRGSEL ,ADC1 pre-trigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x00 8.--11. " ADC1TRGSEL ,ADC1 trigger select" "PDB_EXTRG0,CMP0_OUT,CMP1_OUT,PDB_EXTRG1,DMA_CH0,DMA_CH1,DMA_CH2,DMA_CH3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,FTM4 trigger,FTM5 trigger,LPTMR0 trigger,?..." newline bitfld.long 0x00 6.--7. " ADC0ALTTRGEN , ADC0 alternate conversion triggers enable" "PDB0_CH0,PDB1_CH0,ADC0TRGSEL,PDB0_CH1/PDB1_CH1" bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pre-trigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB_EXTRG,CMP0_OUT,CMP1_OUT,PDB_EXTRG1,DMA_CH0,DMA_CH1,DMA_CH2,DMA_CH3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,FTM4 trigger,FTM5 trigger,LPTMR0 trigger,?..." else bitfld.long 0x00 15. " ADC1ALTTRGEN ,ADC1 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADC1PRETRGSEL ,ADC1 pre-trigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x00 8.--11. " ADC1TRGSEL ,ADC1 trigger select" "PDB0_EXTRG,HSCMP0_OUT,HSCMP1_OUT,,DMA_CH0,DMA_CH1,DMA_CH2,DMA_CH3,FTM0 trigger,FTM1 trigger,FTM2 trigger,,,,LPTMR0 trigger,?..." newline bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pre-trigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,HSCMP0_OUT,HSCMP1_OUT,,DMA_CH0,DMA_CH1,DMA_CH2,DMA_CH3,FTM0 trigger,FTM1 trigger,FTM2 trigger,,,,LPTMR0 trigger,?..." endif line.long 0x04 "SOPT8,System Options Register 8" bitfld.long 0x04 23. " FTM2OCH1SRC ,FTM2 channel 1 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x04 22. " FTM2OCH0SRC ,FTM2 channel 0 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x04 21. " FTM0OCH5SRC ,FTM0 channel 5 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" newline bitfld.long 0x04 20. " FTM0OCH4SRC ,FTM0 channel 4 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x04 19. " FTM0OCH3SRC ,FTM0 channel 3 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x04 18. " FTM0OCH2SRC ,FTM0 channel 2 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" newline bitfld.long 0x04 17. " FTM0OCH1SRC ,FTM0 channel 1 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x04 16. " FTM0OCH0SRC ,FTM0 channel 0 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" newline sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x04 8.--9. " CARRIER_SELECT0 , Carrier frequency selection for FTM0/2 output channel" "FTM1_CH1,LPTMR0,FTM5_CH1,?..." bitfld.long 0x04 5. " FTM5SYNCBIT ,FlexTimer 5 hardware trigger 0 configure by software" "No,Yes" bitfld.long 0x04 4. " FTM4SYNCBIT ,FlexTimer 4 hardware trigger 0 configure by software" "No,Yes" newline bitfld.long 0x04 3. " FTM3SYNCBIT ,FlexTimer 3 hardware trigger 0 configure by software" "No,Yes" else bitfld.long 0x04 8. " CARRIER_SELECT ,Carrier frequency selection for FTM0/2 output channel" "FTM1_CH1,LPTMR0" endif newline bitfld.long 0x04 2. " FTM2SYNCBIT ,FlexTimer 2 hardware trigger 0 configure by software" "No,Yes" bitfld.long 0x04 1. " FTM1SYNCBIT ,FlexTimer 1 hardware trigger 0 configure by software" "No,Yes" bitfld.long 0x04 0. " FTM0SYNCBIT ,FlexTimer 0 hardware trigger 0 configure by software" "No,Yes" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") group.long 0x20++0x03 line.long 0x00 "SOPT9,System Options Register 9" bitfld.long 0x00 23. " FTM4OCH1SRC ,FTM4 channel 1 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 22. " FTM4OCH0SRC ,FTM4 channel 0 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 21. " FTM3OCH5SRC ,FTM3 channel 5 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" newline bitfld.long 0x00 20. " FTM3OCH4SRC ,FTM3 channel 4 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 19. " FTM3OCH3SRC ,FTM3 channel 3 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 18. " FTM3OCH2SRC ,FTM3 channel 2 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" newline bitfld.long 0x00 17. " FTM3OCH1SRC ,FTM3 channel 1 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 16. " FTM3OCH0SRC ,FTM3 channel 0 output PWM/OCMP mode source select" "PWM/OCMP,PWM/OCMP_CARRIER_SELECT" bitfld.long 0x00 8.--9. " CARRIER_SELECT1 ,Carrier frequency selection for FTM3/4 output channel" "FTM1_CH1,LPTMR0,FTM5_CH1,?..." endif rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" bitfld.long 0x00 28.--31. " FAMID ,V-Family ID" ",MKV1xZx,?..." newline sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 24.--27. " SUBFAMID ,V sub-family ID" "MKV10xxxx,MKV11xxxx,?..." bitfld.long 0x00 20.--23. " SERIERID ,Series ID" ",,,,,,Motor Control,?..." bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,,,16KB,?..." newline bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,?..." else sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 24.--27. " SUBFAMID ,V sub-family ID" "MKV10xxxx,MKV11xxxx,?..." else bitfld.long 0x00 24.--27. " SUBFAMID ,V sub-family ID" "MKV10xxxx,?..." endif newline bitfld.long 0x00 20.--23. " SERIERID ,Series ID" ",,,,,,Motor Control,?..." bitfld.long 0x00 16.--19. " SRAMSIZE ,System SRAM size" ",,,4KB,8KB,?..." bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,?..." endif group.long 0x34++0x0F line.long 0x00 "SCGC4,System Clock Gating Control Register 4" bitfld.long 0x00 19. " CMP ,Comparator clock gate control" "Disabled,Enabled" bitfld.long 0x00 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled" bitfld.long 0x00 1. " EWM ,EWM clock gate control" "Disabled,Enabled" line.long 0x04 "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x04 13. " PORTE ,Port E clock gate control" "Disabled,Enabled" bitfld.long 0x04 12. " PORTD ,Port D clock gate control" "Disabled,Enabled" bitfld.long 0x04 11. " PORTC ,Port C clock gate control" "Disabled,Enabled" newline bitfld.long 0x04 10. " PORTB ,Port B clock gate control" "Disabled,Enabled" bitfld.long 0x04 9. " PORTA ,Port A clock gate control" "Disabled,Enabled" bitfld.long 0x04 0. " LPTMR ,Low power timer access control" "Disabled,Enabled" line.long 0x08 "SCGC6,System Clock Gating Control Register 6" bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 28. " ADC1 ,ADC1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 26. " FTM2 ,FTM2 clock gate control" "Disabled,Enabled" bitfld.long 0x08 25. " FTM1 ,FTM1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 24. " FTM0 ,FTM0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 22. " PDB ,PDB clock gate control" "Disabled,Enabled" bitfld.long 0x08 18. " CRC ,CRC clock gate control" "Disabled,Enabled" newline sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x08 17. " PDB1 ,PDB1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 12. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 8. " FTM5 ,FTM5 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 7. " FTM4 ,FTM4 clock gate control" "Disabled,Enabled" bitfld.long 0x08 6. " FTM3 ,FTM3 clock gate control" "Disabled,Enabled" bitfld.long 0x08 4. " FLEXCAN0 , FLEXCAN0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 1. " DMAMUX , DMA mux clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" else bitfld.long 0x08 12. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" endif line.long 0x0C "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x0C 8. " DMA ,DMA clock gate control" "Disabled,Enabled" if (((per.b(ad:0x4007E000+0x01))&0x60)==0x20) rgroup.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 15. " OUTDIV5EN ,OUTDIV5 divider Control" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " OUTDIV5 ,Clock 5 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8" else group.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--18. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 15. " OUTDIV5EN ,OUTDIV5 divider control" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " OUTDIV5 ,Clock 5 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8" endif group.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" "8 kB,16 kB,,32 kB,,64 kB,,128 kB,,256 kB,,,,,,32 kB" bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Disabled,Enabled" bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes" rgroup.long 0x50++0x03 line.long 0x00 "FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 1. " MAXADDR ,Max address block" rgroup.long 0x58++0x0B line.long 0x00 "UIDMH,Unique Identification Register Mid-High" hexmask.long.word 0x00 0.--15. 1. " UID ,Unique identification" line.long 0x04 "UIDML,Unique Identification Register Mid Low" line.long 0x08 "UIDL,Unique Identification Register Low" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z64VLF7") group.long 0x100++0x03 line.long 0x00 "WDOGCTRL,WDOG Control Register" bitfld.long 0x00 1. " WDOGCLKS ,WDOG clock select" "Internal 1kHz,MCGIRCLK" else group.long 0xA0++0x03 line.long 0x00 "WDOGCTRL,WDOG Control Register" bitfld.long 0x00 1. " WDOGCLKS ,WDOG clock select" "Internal 1kHz,MCGIRCLK" endif width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection register" bitfld.byte 0x00 5. " AVLP ,Allow very-low-power modes" "Not allowed,Allowed" bitfld.byte 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control register" bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very-Low-Power,?..." rbitfld.byte 0x01 3. "STOPA ,Stop aborted" "Successful,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,stop mode control" "Normal Stop,,Very-Low-Power Stop,,Very-Low-Leakage Stop,?..." sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" sif !cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") newline bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" endif newline bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" newline bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,,VLLS3,?..." endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.byte 0x00 6. " [6] ,Current power mode is VLLS" "No,Yes" bitfld.byte 0x00 4. " [4] ,Current power mode is VLPS" "No,Yes" bitfld.byte 0x00 3. " [3] ,Current power mode is VLPW" "No,Yes" newline bitfld.byte 0x00 2. " [2] ,Current power mode is VLPR" "No,Yes" bitfld.byte 0x00 1. " [1] ,Current power mode is STOP" "No,Yes" bitfld.byte 0x00 0. " [0] ,Current power mode is RUN" "No,Yes" else hexmask.byte 0x00 0.--6. 1. " PMSTAT ,Current power mode of the system" endif width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip point,High trip point,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Clear" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip point,Mid 1 trip point,Mid 2 trip point,High trip point" line.byte 0x02 "REGSC,Regulator Status And Control register" bitfld.byte 0x02 4. " BGEN ,Bandgap enable VLPx operation" "Disabled,Enabled" eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Normal,Isolated" rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stopped,Running" newline bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" sif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")) group.byte 0x0B++0x00 line.byte 0x00 "HVDSC1,High Voltage Detect Status And Control 1 register" rbitfld.byte 0x00 7. " HVDF ,High-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " HVDACK ,High-voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " HVDIE ,High-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " HVDRE ,High-voltage detect reset enable" "Not forced,Forced" bitfld.byte 0x00 0. " HVDV ,High-voltage detect voltage select" "Low,High" endif width 0x0B tree.end tree "LLWU (Low-Leakage Wakeup Unit)" base ad:0x4007C000 sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") width 7. group.byte 0x00++0x06 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE[3] ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE[7] ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 4.--5. " [6] ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 2.--3. " [5] ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 4.--5. " WUPE[10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 2.--3. " [9] ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 0.--1. " [8] ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE[15] ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 4.--5. " [14] ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x04 "ME,LLWU Module Enable Register" bitfld.byte 0x04 3. " [3] ,Wakeup module enable for module 3" "Disabled,Enabled" bitfld.byte 0x04 2. " [2] ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x04 1. " [1] ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x04 0. " [0] ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x05 "F1,LLWU Flag 1 Register" eventfld.byte 0x05 7. " WUF[7] ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x05 6. " [6] ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x05 5. " [5] ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x05 3. " [3] ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" line.byte 0x06 "F2,LLWU Flag 2 Register" eventfld.byte 0x06 7. " WUF[15] ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x06 6. " [14] ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x06 2. " [10] ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x06 1. " [9] ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" newline eventfld.byte 0x06 0. " [8] ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" rgroup.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 Register" bitfld.byte 0x00 3. " [3] ,Wakeup flag for module 3" "No wakeup,Wakeup" bitfld.byte 0x00 2. " [2] ,Wakeup flag for module 2" "No wakeup,Wakeup" bitfld.byte 0x00 1. " [1] ,Wakeup flag for module 1" "No wakeup,Wakeup" bitfld.byte 0x00 0. " [0] ,Wakeup flag for module 0" "No wakeup,Wakeup" group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15" line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15" width 0x0B elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") width 7. group.byte 0x00++0x05 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE[3] ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any change" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--1. " [0] ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE[7] ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 4.--5. " [6] ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 2.--3. " [5] ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any change" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--1. " [4] ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x02 6.--7. " WUPE[11] ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 4.--5. " [10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" else bitfld.byte 0x02 4.--5. " WUPE[10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" endif newline bitfld.byte 0x02 2.--3. " [9] ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 0.--1. " [8] ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE[15] ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 4.--5. " [14] ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any change" sif !cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7") newline bitfld.byte 0x03 2.--3. " [13] ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 0.--1. " [12] ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x04 "PE5,LLWU Pin Enable 5 Register" bitfld.byte 0x04 6.--7. " WUPE[19] ,Wakeup pin enable for LLWU_P19" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x05 "PE6,LLWU Pin Enable 6 Register" bitfld.byte 0x05 2.--3. " WUPE[21] ,Wakeup pin enable for LLWU_P21" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x05 0.--1. " [20] ,Wakeup pin enable for LLWU_P20" "Disabled,Rising edge,Falling edge,Any change" group.byte 0x08++0x03 line.byte 0x00 "ME,LLWU Module Enable Register" bitfld.byte 0x00 3. " WUME[3] ,Wakeup module enable for module 3" "Disabled,Enabled" bitfld.byte 0x00 2. " [2] ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x00 1. " [1] ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x00 0. " [0] ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x01 "PF1,LLWU Pin Flag 1 Register" eventfld.byte 0x01 7. " WUF[7] ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x01 6. " [6] ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x01 5. " [5] ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline eventfld.byte 0x01 4. " [4] ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup" endif newline eventfld.byte 0x01 3. " [3] ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline eventfld.byte 0x01 0. " [0] ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup" endif line.byte 0x02 "PF2,LLWU Pin Flag 2 Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") eventfld.byte 0x02 7. " WUF[15] ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x02 6. " [14] ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" sif !cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7") newline eventfld.byte 0x02 5. " [13] ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x02 4. " [12] ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" sif !cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7") newline eventfld.byte 0x02 3. " [11] ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup" endif endif newline eventfld.byte 0x02 2. " [10] ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x02 1. " [9] ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x02 0. " [8] ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" endif line.byte 0x03 "PF3,LLWU Pin Flag 3 Register" eventfld.byte 0x03 5. " WUF[21] ,Wakeup flag for LLWU_P21" "No wakeup,Wakeup" eventfld.byte 0x03 4. " [20] ,Wakeup flag for LLWU_P20" "No wakeup,Wakeup" eventfld.byte 0x03 3. " [19] ,Wakeup flag for LLWU_P19" "No wakeup,Wakeup" rgroup.byte 0x0D++0x00 line.byte 0x00 "MF5,LLWU Module Flag 5 Register" bitfld.byte 0x00 3. " MWUF[3] ,Wakeup flag for module 3" "No wakeup,Wakeup" bitfld.byte 0x00 2. " [2] ,Wakeup flag for module 2" "No wakeup,Wakeup" bitfld.byte 0x00 1. " [1] ,Wakeup flag for module 1" "No wakeup,Wakeup" bitfld.byte 0x00 0. " [0] ,Wakeup flag for module 0" "No wakeup,Wakeup" group.byte 0x0E++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" newline sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." elif cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." else bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." endif line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" newline sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." elif cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." else bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." endif width 0x0B else width 7. group.byte 0x00++0x06 line.byte 0x00 "PE1,LLWU Pin Enable 1 register" bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup Pin Enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x01 "PE2,LLWU Pin Enable 2 register" bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup Pin Enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup Pin Enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup Pin Enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x02 "PE3,LLWU Pin Enable 3 register" bitfld.byte 0x02 4.--5. " WUPE10 ,Wakeup Pin Enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x02 2.--3. " WUPE9 ,Wakeup Pin Enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x02 0.--1. " WUPE8 ,Wakeup Pin Enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x03 "PE4,LLWU Pin Enable 4 register" bitfld.byte 0x03 6.--7. " WUPE15 ,Wakeup Pin Enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x03 4.--5. " WUPE14 ,Wakeup Pin Enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x03 2.--3. " WUPE13 ,Wakeup Pin Enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x03 0.--1. " WUPE12 ,Wakeup Pin Enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any edge" textline " " line.byte 0x04 "ME,LLWU Module Enable register" bitfld.byte 0x04 7. " WUME7 ,Wakeup Module Enable For Module 7" "Not used,Used" bitfld.byte 0x04 6. " WUME6 ,Wakeup Module Enable For Module 6" "Not used,Used" bitfld.byte 0x04 5. " WUME5 ,Wakeup Module Enable For Module 5" "Not used,Used" textline " " bitfld.byte 0x04 4. " WUME4 ,Wakeup Module Enable For Module 4" "Not used,Used" bitfld.byte 0x04 3. " WUME3 ,Wakeup Module Enable For Module 3" "Not used,Used" bitfld.byte 0x04 2. " WUME2 ,Wakeup Module Enable For Module 2" "Not used,Used" textline " " bitfld.byte 0x04 1. " WUME1 ,Wakeup Module Enable For Module 1" "Not used,Used" bitfld.byte 0x04 0. " WUME0 ,Wakeup Module Enable For Module 0" "Not used,Used" line.byte 0x05 "F1,LLWU Flag 1 register" eventfld.byte 0x05 7. " WUF7 ,Wakeup Flag For LLWU_P7" "Not wake-up source,Wake-up source" eventfld.byte 0x05 6. " WUF6 ,Wakeup Flag For LLWU_P6" "Not wake-up source,Wake-up source" eventfld.byte 0x05 5. " WUF5 ,Wakeup Flag For LLWU_P5" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x05 3. " WUF3 ,Wakeup Flag For LLWU_P3" "Not wake-up source,Wake-up source" line.byte 0x06 "F2,LLWU Flag 2 register" eventfld.byte 0x06 7. " WUF15 ,Wakeup Flag For LLWU_P15" "Not wake-up source,Wake-up source" eventfld.byte 0x06 6. " WUF14 ,Wakeup Flag For LLWU_P14" "Not wake-up source,Wake-up source" eventfld.byte 0x06 5. " WUF13 ,Wakeup Flag For LLWU_P13" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x06 4. " WUF12 ,Wakeup Flag For LLWU_P12" "Not wake-up source,Wake-up source" eventfld.byte 0x06 2. " WUF10 ,Wakeup Flag For LLWU_P10" "Not wake-up source,Wake-up source" eventfld.byte 0x06 1. " WUF9 ,Wakeup Flag For LLWU_P9" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x06 0. " WUF8 ,Wakeup Flag For LLWU_P8" "Not wake-up source,Wake-up source" rgroup.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 register" bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not a wakeup source,Wakeup source" textline " " bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not a wakeup source,Wakeup source" textline " " bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not a wakeup source,Wakeup source" textline " " group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 register" eventfld.byte 0x00 7. " FILTF ,Filter Detect Flag" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 5.--6. " FILTE ,Digital Filter On External Pin" "Disabled,Posedge,Negedge,Any edge" textline " " bitfld.byte 0x00 0.--3. " FILTSEL ,Filter Pin Select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" line.byte 0x01 "FILT2,LLWU Pin Filter 2 register" eventfld.byte 0x01 7. " FILTF ,Filter Detect Flag" "Not a wakeup source,Wakeup source" bitfld.byte 0x01 5.--6. " FILTE ,Digital Filter On External Pin" "Disabled,Posedge,Negedge,Any edge" textline " " bitfld.byte 0x01 0.--3. " FILTSEL ,Filter Pin Select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" width 0x0B endif tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 6. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "No reset,Reset" bitfld.byte 0x00 6. " PIN ,External reset pin" "No reset,Reset" bitfld.byte 0x00 5. " WDOG ,Watchdog" "No reset,Reset" bitfld.byte 0x00 2. " LOC ,Loss-of-clock eeset" "No reset,Reset" newline bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "No reset,Reset" bitfld.byte 0x00 0. " WAKEUP ,Low leakage wakeup reset" "No reset,Reset" line.byte 0x01 "SRS1,System Reset Status Register 1" bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "No reset,Reset" bitfld.byte 0x01 3. " MDM_AP , MDM_AP system reset request" "No reset,Reset" bitfld.byte 0x01 2. " SW ,Software" "No reset,Reset" bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "No reset,Reset" group.byte 0x04++0x01 line.byte 0x00 "RPFC,Rest Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter delect in stop mode" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "Disabled,Bus clock,LPO clock,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Reset pin filter bus clock select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z64VLF7") group.byte 0x02++0x01 line.byte 0x00 "FM,Force Mode Register" bitfld.byte 0x00 1.--2. " FORCEROM ,Force ROM boot" "No effect,ROM with RCM_MR[1] set,ROM with RCM_MR[2] set,ROM with RCM_MR[2:1] set" line.byte 0x01 "MR,Mode Register" eventfld.byte 0x01 1.--2. " BOOTROM ,Boot ROM configuration" "Flash,ROM-BOOTCFG0 pin assertion,ROM-FOPT[7] configuration,ROM-BOOTCFG0 pin assertion/FOP[7] configuration" endif width 0x0B tree.end tree "MMDVSQ (Memory-Mapped Divide And Square Root)" base ad:0xF0004000 width 8. group.long 0x00++0x0B line.long 0x00 "DEND,Dividend Register" line.long 0x04 "DSOR,Divisor Register" line.long 0x08 "CSR,Control/Status Register" rbitfld.long 0x08 31. " BUSY ,Busy" "Idle,Busy" rbitfld.long 0x08 30. " DIVIDE ,Divide" "Not divided,Divided" rbitfld.long 0x08 29. " SQRT ,Square root" "Was not a square root,Was a square root" newline bitfld.long 0x08 5. " DFS ,Disable fast start" "DSOR,CSR" rbitfld.long 0x08 4. " DZ ,Divide-by-zero" "Non-zero divisor,Zero divisor" bitfld.long 0x08 3. " DZE ,Divide-by-zero-enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " REM ,Remainder calculation" "Return quotient,Return reminder" bitfld.long 0x08 1. " USGN ,Unsigned calculation" "Signed divide,Unsigned divide" bitfld.long 0x08 0. " SRT ,Start" "No effect,Start" newline hgroup.long 0x0C++0x03 hide.long 0x00 "RES,Result Register" in newline wgroup.long 0x10++0x03 line.long 0x00 "RCND,Radicand Register" width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xF0003000 width 8. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch Slave Configuration" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.word 0x00 7. " ASC[7] ,A bus slave connection port 7" "Not connected,Connected" bitfld.word 0x00 6. " [6] ,A bus slave connection port 6" "Not connected,Connected" bitfld.word 0x00 5. " [5] ,A bus slave connection port 5" "Not connected,Connected" bitfld.word 0x00 4. " [4] ,A bus slave connection port 4" "Not connected,Connected" newline bitfld.word 0x00 3. " [3] ,A bus slave connection port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,A bus slave connection port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,A bus slave connection port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,A bus slave connection port 0" "Not connected,Connected" else bitfld.word 0x00 2. " ASC[2] ,A bus slave connection port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,A bus slave connection port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,A bus slave connection port 0" "Not connected,Connected" endif line.word 0x02 "PLAMC,Crossbar Switch Master Configuration" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.word 0x02 7. " AMC[7] ,A bus master connection Port 7" "Not connected,Connected" bitfld.word 0x02 6. " [6] ,A bus master connection Port 6" "Not connected,Connected" bitfld.word 0x02 5. " [5] ,A bus master connection Port 5" "Not connected,Connected" bitfld.word 0x02 4. " [4] ,A bus master connection Port 4" "Not connected,Connected" newline bitfld.word 0x02 3. " [3] ,A bus master connection Port 3" "Not connected,Connected" bitfld.word 0x02 2. " [2] ,A bus master connection Port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,A bus master connection Port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,A bus master connection Port 0" "Not connected,Connected" else bitfld.word 0x02 2. " AMC[2] ,A bus master connection Port 2" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,A bus master connection Port 0" "Not connected,Connected" endif newline group.long 0x0C++0x03 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled" bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes" bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled" bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes" newline bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes" bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes" bitfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear" bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wake-up on interrupt" "No effect,Cleared" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge [entry/exit]" "Not completed/Completed,Completed/Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" width 0x0B tree.end tree.open "MTB (Micro Trace Buffer)" tree "RAM (System RAM Controller)" base ad:0xF0000000 width 17. group.long 0x00++0x0B line.long 0x00 "MTB_POSITION,MTB Position Register" hexmask.long 0x00 3.--31. 0x08 " POINTER ,Trace packet address pointer" bitfld.long 0x00 2. " WRAP ,Pointer value wraps" "Low,High" line.long 0x04 "MTB_MASTER,MTB Master Register" bitfld.long 0x04 31. " EN ,Main trace enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " HALTREQ ,Halt request bit" "Not requested,Requested" bitfld.long 0x04 8. " RAMPRIV ,RAM privilege bit" "Low,High" newline bitfld.long 0x04 7. " SFRWPRIV ,Special function register write privilege bit" "Low,High" bitfld.long 0x04 6. " TSTOPEN ,Trace stop input enable" "Disabled,Enabled" bitfld.long 0x04 5. " TSTARTEN ,Trace start input enable" "Disabled,Enabled" newline bitfld.long 0x04 0.--4. " MASK ,Maximum size of the trace buffer in RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MTB_FLOW,MTB Flow Register" hexmask.long 0x08 3.--31. 0x08 " WATERMARK ,Watermark value" bitfld.long 0x08 1. " AUTOHALT ,Autohalt" "Not halted,Halted" bitfld.long 0x08 0. " AUTOSTOP ,Autostop" "Not stopped,Stopped" rgroup.long 0x0C++0x03 line.long 0x00 "MTB_BASE,MTB Base Register" rgroup.long 0xF00++0x03 line.long 0x00 "MTB_MODECTRL,Integration Mode Control Register" rgroup.long 0xFA0++0x07 line.long 0x00 "MTB_TAGSET,Claim TAG Set Register" line.long 0x04 "MTB_TAGCLEAR,Claim TAG Clear Register" rgroup.long 0xFB0++0x0F line.long 0x00 "MTB_LOCKACCESS,Lock Access Register" line.long 0x04 "MTB_LOCKSTAT,Lock Status Register" line.long 0x08 "MTB_AUTHSTAT,Authentication Status Register" bitfld.long 0x08 2. " BIT2 ,It's hardwired to NIDEN or DBGEN signal" "Low,High" bitfld.long 0x08 0. " BIT0 ,It's hardwired to DBGEN" "Low,High" line.long 0x0C "MTB_DEVICEARCH,Device Architecture Register" rgroup.long 0xFC8++0x07 line.long 0x00 "MTB_DEVICECFG,Device Configuration Register" line.long 0x04 "MTB_DEVICETYPID,Device Type Identifier Register" rgroup.long 0xFD0++0x03 line.long 0x00 "MTB_PERIPHID4,Peripheral ID Register 4" rgroup.long 0xFD4++0x03 line.long 0x00 "MTB_PERIPHID5,Peripheral ID Register 5" rgroup.long 0xFD8++0x03 line.long 0x00 "MTB_PERIPHID6,Peripheral ID Register 6" rgroup.long 0xFDC++0x03 line.long 0x00 "MTB_PERIPHID7,Peripheral ID Register 7" rgroup.long 0xFE0++0x03 line.long 0x00 "MTB_PERIPHID0,Peripheral ID Register 0" rgroup.long 0xFE4++0x03 line.long 0x00 "MTB_PERIPHID1,Peripheral ID Register 1" rgroup.long 0xFE8++0x03 line.long 0x00 "MTB_PERIPHID2,Peripheral ID Register 2" rgroup.long 0xFEC++0x03 line.long 0x00 "MTB_PERIPHID3,Peripheral ID Register 3" rgroup.long 0xFF0++0x03 line.long 0x00 "MTB_COMPID0,Component ID Register 0" rgroup.long 0xFF4++0x03 line.long 0x00 "MTB_COMPID1,Component ID Register 1" rgroup.long 0xFF8++0x03 line.long 0x00 "MTB_COMPID2,Component ID Register 2" rgroup.long 0xFFC++0x03 line.long 0x00 "MTB_COMPID3,Component ID Register 3" width 0x0B tree.end tree "DWT (Data Watchpoint Trace)" base ad:0xF0001000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MTBDWT_CTRL,MTB DWT Control Register" bitfld.long 0x00 28.--31. " NUMCMP ,Number of comparators" "0,1,2,?..." bitfld.long 0x00 27. " NOTRCPKT ,Trace sample and exception trace" "Supported,Not supported" bitfld.long 0x00 26. " NOEXTTRIG ,External match signals" "Supported,Not supported" newline bitfld.long 0x00 25. " NOCYCCNT ,Cycle counter" "Supported,Not supported" bitfld.long 0x00 24. " NOPRFCNT ,Profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEBTENA ,POSTCNT underflow packets" "Not generated,Generated" newline bitfld.long 0x00 21. " FOLDEVTENA ,Folded instruction counter overflow events" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,LSU counter overflow events" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Sleep counter overflow events" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Exception overhead counter events" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,CPI counter overflow events" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLENA ,Periodic PC sample packets" "Not generated,Generated" bitfld.long 0x00 10.--11. " SYNCTAP ,Synchronization packets" "0,1,2,3" bitfld.long 0x00 9. " CYCTAP ,Cycle counter" "Not supported,Supported" newline bitfld.long 0x00 5.--8. " POSTINIT ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Cycle counter" "Not supported,Supported" group.long 0x20++0x0B line.long 0x00 "MTBDWT_COMP0,MTB_DWT Comparator Register 0" line.long 0x04 "MTBDWT_MASK0,MTB_DWT Comparator Mask Register 0" bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." hgroup.long (0x20+0x08)++0x03 hide.long 0x00 "MTBDWT_FCT0,MTB_DWT Comparator Function Register 0" newline in newline group.long 0x30++0x0B line.long 0x00 "MTBDWT_COMP1,MTB_DWT Comparator Register 1" line.long 0x04 "MTBDWT_MASK1,MTB_DWT Comparator Mask Register 1" bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..." hgroup.long (0x30+0x08)++0x03 hide.long 0x00 "MTBDWT_FCT1,MTB_DWT Comparator Function Register 1" newline in newline group.long 0x200++0x03 line.long 0x00 "MTBDWT_TBCTRL,MTB_DWT Trace Buffer Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,2,?..." bitfld.long 0x00 1. " ACOMP1 ,Action based on comparator 1 match" "TSTOP,TSTART" newline bitfld.long 0x00 0. " ACOMP0 ,Action based on comparator 0 match" "TSTOP,TSTART" rgroup.long 0xFC8++0x07 line.long 0x00 "MTBDWT_DEVICECFG,Device Configuration Register" line.long 0x04 "MTBDWT_DEVICETYPID,Device Type Identifier Register" rgroup.long (0xFD0+0x0)++0x03 line.long 0x00 "MTBDWT_PERIPHID4,Peripheral ID Register 4" rgroup.long (0xFD0+0x4)++0x03 line.long 0x00 "MTBDWT_PERIPHID5,Peripheral ID Register 5" rgroup.long (0xFD0+0x8)++0x03 line.long 0x00 "MTBDWT_PERIPHID6,Peripheral ID Register 6" rgroup.long (0xFD0+0xC)++0x03 line.long 0x00 "MTBDWT_PERIPHID7,Peripheral ID Register 7" rgroup.long (0xFD0+0x10)++0x03 line.long 0x00 "MTBDWT_PERIPHID0,Peripheral ID Register 0" rgroup.long (0xFD0+0x14)++0x03 line.long 0x00 "MTBDWT_PERIPHID1,Peripheral ID Register 1" rgroup.long (0xFD0+0x18)++0x03 line.long 0x00 "MTBDWT_PERIPHID2,Peripheral ID Register 2" rgroup.long (0xFD0+0x1C)++0x03 line.long 0x00 "MTBDWT_PERIPHID3,Peripheral ID Register 3" rgroup.long (0xFF0+0x0)++0x03 line.long 0x00 "MTBDWT_COMPID0,Component ID Register 0" rgroup.long (0xFF0+0x4)++0x03 line.long 0x00 "MTBDWT_COMPID1,Component ID Register 1" rgroup.long (0xFF0+0x8)++0x03 line.long 0x00 "MTBDWT_COMPID2,Component ID Register 2" rgroup.long (0xFF0+0xC)++0x03 line.long 0x00 "MTBDWT_COMPID3,Component ID Register 3" width 0x0B tree.end tree "ROM (System ROM)" base ad:0xF0002000 width 15. rgroup.long 0x0++0x03 line.long 0x00 "ROM_ENTRY0,Entry Register 0" rgroup.long 0x4++0x03 line.long 0x00 "ROM_ENTRY1,Entry Register 1" rgroup.long 0x8++0x03 line.long 0x00 "ROM_ENTRY2,Entry Register 2" rgroup.long 0x0C++0x03 line.long 0x00 "ROM_TABLEMARK,End Of Table Marker Register" rgroup.long 0xFCC++0x03 line.long 0x00 "ROM_SYSACCESS,System Access Register" rgroup.long 0xFD0++0x03 line.long 0x00 "ROM_PERIPHID4,Peripheral ID Register 4" rgroup.long 0xFD4++0x03 line.long 0x00 "ROM_PERIPHID5,Peripheral ID Register 5" rgroup.long 0xFD8++0x03 line.long 0x00 "ROM_PERIPHID6,Peripheral ID Register 6" rgroup.long 0xFDC++0x03 line.long 0x00 "ROM_PERIPHID7,Peripheral ID Register 7" rgroup.long 0xFE0++0x03 line.long 0x00 "ROM_PERIPHID0,Peripheral ID Register 0" rgroup.long 0xFE4++0x03 line.long 0x00 "ROM_PERIPHID1,Peripheral ID Register 1" rgroup.long 0xFE8++0x03 line.long 0x00 "ROM_PERIPHID2,Peripheral ID Register 2" rgroup.long 0xFEC++0x03 line.long 0x00 "ROM_PERIPHID3,Peripheral ID Register 3" rgroup.long 0xFF0++0x03 line.long 0x00 "ROM_COMPID0,Component ID Register 0" rgroup.long 0xFF4++0x03 line.long 0x00 "ROM_COMPID1,Component ID Register 1" rgroup.long 0xFF8++0x03 line.long 0x00 "ROM_COMPID2,Component ID Register 2" rgroup.long 0xFFC++0x03 line.long 0x00 "ROM_COMPID3,Component ID Register 3" width 0x0B tree.end tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 9. sif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") group.byte 0x0++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x1++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x2++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x3++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x4++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x5++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x6++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x7++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,FTM3 ch.4,FTM3 ch.5,FTM5 ch.0,FTM5 ch.1,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" elif cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV11Z64VFM7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,FlexCAN0,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM4 ch.0,FTM4 ch.1,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,FTM3 ch.2,FTM3 ch3.,ADC0,ADC1,CMP0,CMP1,,DAC0,,PDB1,PDB0,PortA,PortB,PortC,PortD,PortE,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif else group.byte 0x0++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x1++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x2++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" group.byte 0x3++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif width 0x0B tree.end tree "eDMA (Enhanced Direct Memory Access)" base ad:0x40008000 sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 4" group.long 0x80++0x03 line.long 0x00 "TCD4_SADDR,TCD Source Address" group.word (0x80+0x04)++0x03 line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD4_DADDR,TCD Destination Address" group.word (0x80+0x14)++0x01 line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x80+0x18)++0x03 line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x80+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 5" group.long 0xA0++0x03 line.long 0x00 "TCD5_SADDR,TCD Source Address" group.word (0xA0+0x04)++0x03 line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD5_DADDR,TCD Destination Address" group.word (0xA0+0x14)++0x01 line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xA0+0x18)++0x03 line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xA0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 6" group.long 0xC0++0x03 line.long 0x00 "TCD6_SADDR,TCD Source Address" group.word (0xC0+0x04)++0x03 line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD6_DADDR,TCD Destination Address" group.word (0xC0+0x14)++0x01 line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xC0+0x18)++0x03 line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xC0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 7" group.long 0xE0++0x03 line.long 0x00 "TCD7_SADDR,TCD Source Address" group.word (0xE0+0x04)++0x03 line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD7_DADDR,TCD Destination Address" group.word (0xE0+0x14)++0x01 line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xE0+0x18)++0x03 line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xE0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B else width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B endif tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Clock source select" "LPO_CLK[0],LPO_CLK[1],LPO_CLK[2],LPO_CLK[3]" endif sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,Allows the WDOG functional test mode to be disabled permanently" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested when the watchdog is in the byte test mode" "0,1,2,3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick,Byte" newline bitfld.word 0x00 10. " TESTWDOG ,Puts the watchdog in the functional test mode" "Disabled,Enabled" bitfld.word 0x00 7. " WAITEN ,Enables or disables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables or disables WDOG in stop mode" "Disabled,Enabled" newline bitfld.word 0x00 5. " DBGEN ,Enables or disables WDOG in debug mode" "Disabled,Enabled" bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" newline bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables or disables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F128VLH10P") eventfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" else bitfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" endif line.word 0x04 "TOVALH,Watchdog Time-Out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-Out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. sif (cpuis("MKV10Z*"))||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif elif cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12?")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)!=0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif else if (((per.b(ad:0x40064000+0x01))&0x30)==0x00||((per.b(ad:0x40064000+0x0C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" else bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" endif line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x03))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20-25 mHz,24 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "40-50 mHz,48 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60-75 mHz,72 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80-100 mHz,96 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" endif sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV10Z*") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN0 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN0 ,PLL stop enable" "Disabled,Enabled" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." newline endif newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV0 ,VCO 0 divider" "24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55" else group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV ,VCO divider" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif cpuis("MKV10Z*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" else bitfld.byte 0x00 7. " LOLS0 ,Loss of lock status" "Not locked,Locked" bitfld.byte 0x00 6. " LOCK0 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,Output PLL" bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" endif group.byte 0x08++0x00 sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" eventfld.byte 0x00 0. " LOCS0 ,OSC0 loss of clock status" "Not occurred,Occurred" else line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" rbitfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred" endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32khz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" newline hgroup.byte 0x11++0x00 hide.long 0x00 "C12,MCG Control 12 Register" hgroup.byte 0x12++0x00 hide.long 0x00 "S2,MCG Status 2 Register" hgroup.byte 0x13++0x00 hide.long 0x00 "T3,MCG Test 3 Register" elif (!cpuis("MKV10Z*"))&&(!cpuis("MKV5*"))&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif cpuis("MK65FN2M0CAF18")||cpuis("MK65FN2M0VMF18")||cpuis("MK65FX1M0CAF18")||cpuis("MK65FX1M0VMF18")||cpuis("MK66FN2M0VLQ18")||cpuis("MK66FN2M0VMD18")||cpuis("MK66FX1M0VLQ18")||cpuis("MK66FX1M0VMD18") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Disabled,Enabled" rbitfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" endif else sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" elif !cpuis("MKV10Z*")&&!cpuis("MKV11Z*") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif endif width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40065000 width 5. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x02++0x00 line.byte 0x00 "DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "FTFA (Flash Memory Module)" base ad:0x40020000 sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rgroup.byte 0x1C++0x03 line.byte 0x00 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Execute-only access control" "Yes,No" rgroup.byte 0x24++0x03 line.byte 0x00 "SACCL3,Supervisor-Only Access Regisster 3" bitfld.byte 0x00 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x01 "SACCL2,Supervisor-Only Access Regisster 2" bitfld.byte 0x01 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x02 "SACCL1,Supervisor-Only Access Regisster 1" bitfld.byte 0x02 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x03 "SACCL0,Supervisor-Only Access Regisster 0" bitfld.byte 0x03 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Supervisor-only access control" "Yes,No" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-Only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-Only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-Only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-Only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-Only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-Only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-Only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-Only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif sif !cpuis("MKV10Z32VLC7*")&&!cpuis("MKV10Z32VFM7*") rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif width 0x0B else width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" newline eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif (cpuis("MKV5*")) newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready" elif (cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block" rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..." newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" else newline rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..." rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif rgroup.byte 0x02++0x00 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" newline bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" sif cpuis("MKV5*") rgroup.byte 0x03++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" sif !cpuis("MKV5*") group.byte 0x10++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x18++0x03 line.byte 0x00 "FPROTH3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTH2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTH1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTH0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV31F*")&&cpuis("MKV30F*") group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" line.byte 0x01 "FDPROT,Data Flash Protection Register" endif newline sif cpuis("MKV31F*")||cpuis("MKV30F*") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif width 0x0B endif tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x00) group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" else group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal half-word" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" endif width 0x0B tree.end tree.open "ADC (Analog-To-Digital Converter)" tree "ADC 0" base ad:0x4003B000 sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") width 15. sif !cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") if ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x20)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif if ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x20)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif else if (((per.l(ad:0x4003B000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,,SE10,SE11,SE12,SE13,SE14,,,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,,SE10,SE11,SE12,SE13,SE14,,,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif endif group.long 0x08++0x07 line.long 0x00 "CFG1,Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection DIFF=0/DIFF=1" "8-bit/9-bit,12-bit/13-bit,10-bit/11-bit,16-bit" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,BUSCLK/2,ALTCK,ADACK" else bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,ALTCLK2,ALTCLK,ADACK" endif line.long 0x04 "CFG2,Configuration Register 2" sif !cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "ADCA,ADCB" newline endif bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "RA,Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "CV1,Compare Value Registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" line.long 0x04 "CV2,Compare Value Registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare value" line.long 0x08 "SC2,Status And Control Register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "SC3,Status And Control Register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" newline bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "OFS,Offset Correction Register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "PG,Plus-Side Gain Register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "MG,Minus-Side Gain Register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side gain" line.long 0x1C "CLPD,Plus-Side General Calibration Value Register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CLPS,Plus-Side General Calibration Value Register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CLP4,Plus-Side General Calibration Value Register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "CLP3,Plus-Side General Calibration Value Register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "CLP2,Plus-Side General Calibration Value Register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "CLP1,Plus-Side General Calibration Value Register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "CLP0,Plus-Side General Calibration Value Register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "CLMD,Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B else width 15. if (((per.l(ad:0x4003B000+0x0))&0x20)==0x0) group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x0) group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000))&0x20)==0x0) group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "ADC0_CFG2,ADC Configuration register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "ADC0_RA,ADC data result register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "ADC0_RB,ADC data result register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "ADC0_CV1,Compare value registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value" line.long 0x04 "ADC0_CV2,Compare value registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value" line.long 0x08 "ADC0_SC2,Status and control register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "ADC0_SC3,Status and control register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" sif (cpuis("MKV5*")) newline eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" else newline rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" endif newline bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "ADC0_OFS,ADC offset correction register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "ADC0_PG,ADC plus-side gain register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "ADC0_MG,ADC minus-side gain register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain" line.long 0x1C "ADC0_CLPD,ADC plus-side general calibration value register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ADC0_CLPS,ADC plus-side general calibration value register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ADC0_CLP4,ADC plus-side general calibration value register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "ADC0_CLP3,ADC plus-side general calibration value register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "ADC0_CLP2,ADC plus-side general calibration value register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "ADC0_CLP1,ADC plus-side general calibration value register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "ADC0_CLP0,ADC plus-side general calibration value register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "ADC0_CLMD,ADC minus-side general calibration value register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ADC0_CLMS,ADC minus-side general calibration value register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ADC0_CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "ADC0_CLM3,CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "ADC0_CLM2,ADC minus-side general calibration value register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "ADC0_CLM1,ADC minus-side general calibration value register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "ADC0_CLM0,ADC minus-side general calibration value register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B endif tree.end tree "ADC 1" base ad:0x4003C000 sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") width 15. sif !cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") if ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003C000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,,,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003C000+0x0))&0x20)==0x20)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003C000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif if ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003C000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,,,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003C000+0x4))&0x20)==0x20)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003C000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003C000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif else if (((per.l(ad:0x4003C000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif if (((per.l(ad:0x4003C000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif endif group.long 0x08++0x07 line.long 0x00 "CFG1,Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection DIFF=0/DIFF=1" "8-bit/9-bit,12-bit/13-bit,10-bit/11-bit,16-bit" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,BUSCLK/2,ALTCK,ADACK" else bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,ALTCLK2,ALTCLK,ADACK" endif line.long 0x04 "CFG2,Configuration Register 2" sif !cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "ADCA,ADCB" newline endif bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "RA,Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "CV1,Compare Value Registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" line.long 0x04 "CV2,Compare Value Registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare value" line.long 0x08 "SC2,Status And Control Register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "SC3,Status And Control Register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" newline bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "OFS,Offset Correction Register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "PG,Plus-Side Gain Register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "MG,Minus-Side Gain Register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side gain" line.long 0x1C "CLPD,Plus-Side General Calibration Value Register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CLPS,Plus-Side General Calibration Value Register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CLP4,Plus-Side General Calibration Value Register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "CLP3,Plus-Side General Calibration Value Register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "CLP2,Plus-Side General Calibration Value Register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "CLP1,Plus-Side General Calibration Value Register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "CLP0,Plus-Side General Calibration Value Register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "CLMD,Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B else width 15. if (((per.l(ad:0x4003C000+0x0))&0x20)==0x0) group.long 0x0++0x03 line.long 0x00 "ADC1_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "ADC1_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003C000+0x4))&0x20)==0x0) group.long 0x4++0x03 line.long 0x00 "ADC1_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "ADC1_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003C000))&0x20)==0x0) group.long 0x08++0x03 line.long 0x00 "ADC1_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "ADC1_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "ADC1_CFG2,ADC Configuration register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "ADC1_RA,ADC data result register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "ADC1_RB,ADC data result register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "ADC1_CV1,Compare value registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value" line.long 0x04 "ADC1_CV2,Compare value registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value" line.long 0x08 "ADC1_SC2,Status and control register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "ADC1_SC3,Status and control register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" sif (cpuis("MKV5*")) newline eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" else newline rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" endif newline bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "ADC1_OFS,ADC offset correction register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "ADC1_PG,ADC plus-side gain register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "ADC1_MG,ADC minus-side gain register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain" line.long 0x1C "ADC1_CLPD,ADC plus-side general calibration value register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ADC1_CLPS,ADC plus-side general calibration value register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ADC1_CLP4,ADC plus-side general calibration value register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "ADC1_CLP3,ADC plus-side general calibration value register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "ADC1_CLP2,ADC plus-side general calibration value register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "ADC1_CLP1,ADC plus-side general calibration value register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "ADC1_CLP0,ADC plus-side general calibration value register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "ADC1_CLMD,ADC minus-side general calibration value register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ADC1_CLMS,ADC minus-side general calibration value register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ADC1_CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "ADC1_CLM3,CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "ADC1_CLM2,ADC minus-side general calibration value register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "ADC1_CLM1,ADC minus-side general calibration value register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "ADC1_CLM0,ADC minus-side general calibration value register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B endif tree.end tree.end tree.open "CMP (Comparator)" tree "CMP 0" base ad:0x40073000 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") tree "CMP 1" base ad:0x40073008 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end endif tree.end tree "DAC (Digital-To-Analog Converter)" base ad:0x4003F000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC0_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC0_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.open "FTM (FlexTimer Module)" tree "Timer 0" base ad:0x40038000 width 15. if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM0_CNT,FTM0 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM0_MOD,FTM0 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x10)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x0C+0x10)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x18)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x0C+0x18)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x20)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x0C+0x20)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0C+0x28)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x0C+0x28)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" bitfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" newline bitfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" newline bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" newline bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 compl. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 compl. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 compl. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 compl. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register" bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM0_CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" newline bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " CH5SE ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SE ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SE ,Channel 3 select" "Not included,Included" newline bitfld.long 0x0C 2. " CH2SE ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "Timer 1" base ad:0x40039000 width 15. if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM1_CNT,FTM1 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM1_MOD,FTM1 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM1_CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "Timer 2" base ad:0x4003A000 width 15. if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM2_CNT,FTM2 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM2_MOD,FTM2 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM2_CONF,FTM2 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") tree "Timer 3" base ad:0x40026000 width 15. if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM3_CNT,FTM3 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM3_MOD,FTM3 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x10)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x0C+0x10)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x18)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x0C+0x18)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x20)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x0C+0x20)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0C+0x28)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x0C+0x28)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM3_CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" bitfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" newline bitfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM3_SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM3_OUTINIT,FTM3 Initial State For Channels Output Register" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" newline bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM3_OUTMASK,FTM3 Output Mask Register" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" newline bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40026000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 compl. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM Synchronization Enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 compl. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 compl. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" newline rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 compl. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM3_EXTTRIG,FTM3 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM3_FMS,FTM3 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM3_FILTER,FTM3 Input Capture Filter Control Register" bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM3_CONF,FTM3 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM3_SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM3_INVCTRL,FTM3 Inverting Control Register" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM3_SWOCTRL,FTM3 Software Output Control Register" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" newline bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM3_PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " CH5SE ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SE ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SE ,Channel 3 select" "Not included,Included" newline bitfld.long 0x0C 2. " CH2SE ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "Timer 4" base ad:0x40027000 width 15. if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM4_SC,FTM4 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM4_SC,FTM4 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM4_CNT,FTM4 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM4_MOD,FTM4 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM4_C0SC,FTM4 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM4_C0V,FTM4 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM4_C0SC,FTM4 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM4_C0V,FTM4 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM4_C1SC,FTM4 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM4_C1V,FTM4 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM4_C1SC,FTM4 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM4_C1V,FTM4 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM4_CNTIN,FTM4 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM4 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM4_STATUS,FTM4 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM4_MODE,FTM4 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM4_MODE,FTM4 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM4_SYNC,FTM4 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM4_OUTINIT,FTM4 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM4_OUTMASK,FTM4 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40027000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM4_COMBINE,FTM4 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM4_COMBINE,FTM4 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM4_DEADTIME,FTM4 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM4_DEADTIME,FTM4 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM4_EXTTRIG,FTM4 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM4_POL,FTM4 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM4_POL,FTM4 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM4_FMS,FTM4 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM4_FILTER,FTM4 Input Capture Filter Control Register" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM4_FLTCTRL,FTM4 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM4_FLTCTRL,FTM4 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM4_QDCTRL,FTM4 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM4 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM4_QDCTRL,FTM4 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM4 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM4_CONF,FTM4 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40027000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM4_FLTPOL,FTM4 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM4_FLTPOL,FTM4 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM4_SYNCONF,FTM4 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM4_INVCTRL,FTM4 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM4_SWOCTRL,FTM4 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM4_PWMLOAD,FTM4 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "Timer 5" base ad:0x40028000 width 15. if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM5_SC,FTM5 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM5_SC,FTM5 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "FTM5_CNT,FTM5 Conter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM5_MOD,FTM5 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM5_C0SC,FTM5 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM5_C0V,FTM5 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0C+0x0)++0x07 line.long 0x00 "FTM5_C0SC,FTM5 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM5_C0V,FTM5 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM5_C1SC,FTM5 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM5_C1V,FTM5 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x0C+0x8)++0x07 line.long 0x00 "FTM5_C1SC,FTM5 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM5_C1V,FTM5 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif group.long 0x4C++0x03 line.long 0x00 "FTM5_CNTIN,FTM5 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM5 counter" rgroup.long 0x50++0x03 line.long 0x00 "FTM5_STATUS,FTM5 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM5_MODE,FTM5 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM5_MODE,FTM5 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even CHN/Man. CLR,All CHN/Man. CLR,All CHN/Auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,Mod/Outmask" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM5_SYNC,FTM5 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM5_OUTINIT,FTM5 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" line.long 0x08 "FTM5_OUTMASK,FTM5 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" if (((per.l(ad:0x40028000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "FTM5_COMBINE,FTM5 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "FTM5_COMBINE,FTM5 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 compl. CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM5_DEADTIME,FTM5 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM5_DEADTIME,FTM5 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM5_EXTTRIG,FTM5 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM5_POL,FTM5 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "FTM5_POL,FTM5 Channels Polarity Register" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif group.long 0x74++0x07 line.long 0x00 "FTM5_FMS,FTM5 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not deteced,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM5_FILTER,FTM5 Input Capture Filter Control Register" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM5_FLTCTRL,FTM5 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FTM5_FLTCTRL,FTM5 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM5_QDCTRL,FTM5 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM5 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM5_QDCTRL,FTM5 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM5 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM5_CONF,FTM5 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40028000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM5_FLTPOL,FTM5 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FTM5_FLTPOL,FTM5 Fault Input Polarity Register" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "FTM5_SYNCONF,FTM5 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "SysCLK rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "SysCLK rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM5_INVCTRL,FTM5 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "FTM5_SWOCTRL,FTM5 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "FTM5_PWMLOAD,FTM5 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end endif tree.end tree "LPTMR (Low-Power Timer)" base ad:0x40040000 width 5. if (((per.l(ad:0x40040000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x40040000))&0x01)==0x00) if (((per.l(ad:0x40040000))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif else if (((per.l(ad:0x40040000))&0x02)==0x00) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif endif if (((per.l(ad:0x40040000))&0x01)==0x00)||(((per.l(ad:0x40040000))&0x81)==0x81) group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif else rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif sif cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") tree.open "PDB (Programmable Delay Block)" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R") tree "PDB 1" base ad:0x40031000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB tree.end endif tree "PDB 0" base ad:0x40036000 sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB else width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB endif tree.end tree.end else tree "PDB (Programmable Delay Block)" base ad:0x40036000 width 11. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,PDB reached MOD,Trigger detected,Trigger detected/PDB mod" bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 16. " SWTRIG,Software trigger" "No effect,Trigger" else bitfld.long 0x00 16. " SWTRIG,Software trigger" "Not triggered,Triggered" endif newline bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler factor" "/1*MULT,/2*MULT,/4*MULT,/8*MULT,/16*MULT,/32*MULT,/64*MULT,/128*MULT" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "PDB_EXTRG0,CMP0,CMP1,PDB_EXTRG1,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR,Software trigger" elif cpuis("MKV10Z*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV30F*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" elif (cpuis("MKV5*")) bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,XBARA_OUT38,,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV5*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV30F*")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" else group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*") else bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" newline endif bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0x0B tree.end endif sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") tree "FlexCAN (Flex Controller Area Network)" base ad:0x40024000 width 15. if ((per.l(ad:0x40024000)&0x40000000)==0x00) group.long 0x00++0x07 line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline rbitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" rbitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" rbitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline rbitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" rbitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" rbitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline rbitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" else group.long 0x00++0x07 line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" endif group.long 0x08++0x03 line.long 0x00 "CAN0_TIMER,CAN0 Free Running Timer Register" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN0_RX14MASK,CAN0 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN0_RX15MASK,CAN0 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN0_RX14MASK,CAN0 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN0_RX15MASK,CAN0 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "CAN0_ESR1,CAN0 Error and Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "CAN0_IMASK1,CAN0 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF31M ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BUF30M ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " BUF29M ,Buffer MB29 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 28. " BUF28M ,Buffer MB28 interrupt mask" "Masked,Not masked" bitfld.long 0x00 27. " BUF27M ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " BUF26M ,Buffer MB26 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 25. " BUF25M ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " BUF24M ,Buffer MB24 interrupt mask" "Masked,Not masked" bitfld.long 0x00 23. " BUF23M ,Buffer MB23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 22. " BUF22M ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " BUF21M ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " BUF20M ,Buffer MB20 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 19. " BUF19M ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " BUF18M ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " BUF17M ,Buffer MB17 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 16. " BUF16M ,Buffer MB16 interrupt mask" "Masked,Not masked" bitfld.long 0x00 15. " BUF15M ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " BUF14M ,Buffer MB14 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 13. " BUF13M ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " BUF12M ,Buffer MB12 interrupt mask" "Masked,Not masked" bitfld.long 0x00 11. " BUF11M ,Buffer MB11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 10. " BUF10M ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " BUF9M ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " BUF8M ,Buffer MB8 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 7. " BUF7M ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " BUF6M ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " BUF5M ,Buffer MB5 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 4. " BUF4M ,Buffer MB4 interrupt mask" "Masked,Not masked" bitfld.long 0x00 3. " BUF3M ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " BUF2M ,Buffer MB2 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 1. " BUF1M ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " BUF0M ,Buffer MB0 interrupt mask" "Masked,Not masked" if ((per.l(ad:0x40024000)&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " BUF7I ,Buffer MB7 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " BUF6I ,Buffer MB6 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " BUF5I ,Buffer MB5 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " BUF4I ,Buffer MB4 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " BUF3I ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BUF2I ,Buffer MB2 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " BUF1I ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" else group.long 0x30++0x03 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " RFO ,RX FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " RFW ,RX FIFO warning" "Not full,Almost full" eventfld.long 0x00 5. " FARF ,Frames available in RX FIFO" "Not available,Available" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" endif if ((per.l(ad:0x40024000)&0x40000000)==0x00) group.long 0x34++0x03 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" endif rgroup.long 0x38++0x03 line.long 0x00 "CAN0_ESR2,CAN0 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No,Yes" rgroup.long 0x44++0x03 line.long 0x00 "CAN0_CRCR,CAN0 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "CAN0_RXFGMASK,CAN0 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" else group.long 0x48++0x03 line.long 0x00 "CAN0_RXFGMASK,CAN0 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "CAN0_RXFIR,CAN0 RX FIFO Information Register" in newline if ((per.l(ad:0x40024000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN0 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN0 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" endif tree "CAN0 RX Individual Mask Registers $2" width 14. if (((per.l(ad:0x40024000))&0x40000000)==0x40000000) group.long 0x880++0x03 line.long 0x00 "CAN0_RXIMR0,CAN0 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x884++0x03 line.long 0x00 "CAN0_RXIMR1,CAN0 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x888++0x03 line.long 0x00 "CAN0_RXIMR2,CAN0 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x88C++0x03 line.long 0x00 "CAN0_RXIMR3,CAN0 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x890++0x03 line.long 0x00 "CAN0_RXIMR4,CAN0 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x894++0x03 line.long 0x00 "CAN0_RXIMR5,CAN0 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x898++0x03 line.long 0x00 "CAN0_RXIMR6,CAN0 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x89C++0x03 line.long 0x00 "CAN0_RXIMR7,CAN0 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A0++0x03 line.long 0x00 "CAN0_RXIMR8,CAN0 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A4++0x03 line.long 0x00 "CAN0_RXIMR9,CAN0 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A8++0x03 line.long 0x00 "CAN0_RXIMR10,CAN0 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8AC++0x03 line.long 0x00 "CAN0_RXIMR11,CAN0 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B0++0x03 line.long 0x00 "CAN0_RXIMR12,CAN0 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B4++0x03 line.long 0x00 "CAN0_RXIMR13,CAN0 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B8++0x03 line.long 0x00 "CAN0_RXIMR14,CAN0 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8BC++0x03 line.long 0x00 "CAN0_RXIMR15,CAN0 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" else rgroup.long 0x880++0x03 line.long 0x00 "CAN0_RXIMR0,CAN0 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x884++0x03 line.long 0x00 "CAN0_RXIMR1,CAN0 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x888++0x03 line.long 0x00 "CAN0_RXIMR2,CAN0 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x88C++0x03 line.long 0x00 "CAN0_RXIMR3,CAN0 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x890++0x03 line.long 0x00 "CAN0_RXIMR4,CAN0 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x894++0x03 line.long 0x00 "CAN0_RXIMR5,CAN0 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x898++0x03 line.long 0x00 "CAN0_RXIMR6,CAN0 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x89C++0x03 line.long 0x00 "CAN0_RXIMR7,CAN0 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A0++0x03 line.long 0x00 "CAN0_RXIMR8,CAN0 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A4++0x03 line.long 0x00 "CAN0_RXIMR9,CAN0 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A8++0x03 line.long 0x00 "CAN0_RXIMR10,CAN0 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8AC++0x03 line.long 0x00 "CAN0_RXIMR11,CAN0 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B0++0x03 line.long 0x00 "CAN0_RXIMR12,CAN0 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B4++0x03 line.long 0x00 "CAN0_RXIMR13,CAN0 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B8++0x03 line.long 0x00 "CAN0_RXIMR14,CAN0 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8BC++0x03 line.long 0x00 "CAN0_RXIMR15,CAN0 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" endif tree.end tree "CAN0 Message Buffer Structure" group.long 0x80++0x0F line.long 0x00 "MB0_0,Message Buffer 0 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB0_1,Message Buffer 0 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB0_2,Message Buffer 0 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB0_3,Message Buffer 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x90++0x0F line.long 0x00 "MB1_0,Message Buffer 1 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB1_1,Message Buffer 1 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB1_2,Message Buffer 1 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB1_3,Message Buffer 1 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xA0++0x0F line.long 0x00 "MB2_0,Message Buffer 2 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB2_1,Message Buffer 2 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB2_2,Message Buffer 2 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB2_3,Message Buffer 2 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xB0++0x0F line.long 0x00 "MB3_0,Message Buffer 3 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB3_1,Message Buffer 3 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB3_2,Message Buffer 3 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB3_3,Message Buffer 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xC0++0x0F line.long 0x00 "MB4_0,Message Buffer 4 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB4_1,Message Buffer 4 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB4_2,Message Buffer 4 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB4_3,Message Buffer 4 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xD0++0x0F line.long 0x00 "MB5_0,Message Buffer 5 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB5_1,Message Buffer 5 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB5_2,Message Buffer 5 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB5_3,Message Buffer 5 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xE0++0x0F line.long 0x00 "MB6_0,Message Buffer 6 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB6_1,Message Buffer 6 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB6_2,Message Buffer 6 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB6_3,Message Buffer 6 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xF0++0x0F line.long 0x00 "MB7_0,Message Buffer 7 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB7_1,Message Buffer 7 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB7_2,Message Buffer 7 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB7_3,Message Buffer 7 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x100++0x0F line.long 0x00 "MB8_0,Message Buffer 8 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB8_1,Message Buffer 8 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB8_2,Message Buffer 8 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB8_3,Message Buffer 8 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x110++0x0F line.long 0x00 "MB9_0,Message Buffer 9 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB9_1,Message Buffer 9 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB9_2,Message Buffer 9 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB9_3,Message Buffer 9 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x120++0x0F line.long 0x00 "MB10_0,Message Buffer 10 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB10_1,Message Buffer 10 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB10_2,Message Buffer 10 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB10_3,Message Buffer 10 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x130++0x0F line.long 0x00 "MB11_0,Message Buffer 11 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB11_1,Message Buffer 11 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB11_2,Message Buffer 11 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB11_3,Message Buffer 11 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x140++0x0F line.long 0x00 "MB12_0,Message Buffer 12 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB12_1,Message Buffer 12 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB12_2,Message Buffer 12 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB12_3,Message Buffer 12 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x150++0x0F line.long 0x00 "MB13_0,Message Buffer 13 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB13_1,Message Buffer 13 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB13_2,Message Buffer 13 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB13_3,Message Buffer 13 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x160++0x0F line.long 0x00 "MB14_0,Message Buffer 14 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB14_1,Message Buffer 14 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB14_2,Message Buffer 14 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB14_3,Message Buffer 14 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x170++0x0F line.long 0x00 "MB15_0,Message Buffer 15 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB15_1,Message Buffer 15 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB15_2,Message Buffer 15 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB15_3,Message Buffer 15 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline tree.end width 0x0B tree.end endif tree "SPI (Serial Peripheral Interface)" base ad:0x4002C000 sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") width 13. if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline rbitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline rbitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline bitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" endif group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4002C000)+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EQQ ,End of queue" "Not last,Last" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not cleared,Cleared" newline sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B else width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpu()=="MKV30F128VFM10"||cpu()=="MKV30F64VFM10"||cpuis("MKW2?D*")) bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B endif tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" newline in newline if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" width 0x0B tree.end tree "UART (Universal Asynchronous Receiver Transmitter)" tree "Module 0" base ad:0x4006A000 width 17. tree "UART 0 Standard Features Registers" group.byte 0x00++0x02 line.byte 0x00 "UART0_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART0_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" newline bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" newline bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" group.byte 0x03++0x00 line.byte 0x00 "UART0_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART0_S1,UART Status Register 1" newline in newline else rgroup.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif group.byte 0x05++0x01 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" newline bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" newline bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" newline bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at length of)" "Disabled,11/12 bit times" newline rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART0_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output" newline bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART0_D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "UART0_MA1,UART Match Address Registers 1" line.byte 0x01 "UART0_MA2,UART Match Address Registers 2" line.byte 0x02 "UART0_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" newline bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART0_C5,UART control register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART0_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART0_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" newline bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 0 FIFO Registers" if (((per.b(ad:0x4006A000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006A000+0x12))&0xC0)==0xC0) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" newline bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" newline eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" if (((per.b(ad:0x4006A000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006A000+0x03))&0x08)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count" tree.end width 0x0B tree.end tree "Module 1" base ad:0x4006B000 width 17. tree "UART 1 Standard Features Registers" group.byte 0x00++0x02 line.byte 0x00 "UART1_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART1_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" newline bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" newline bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" group.byte 0x03++0x00 line.byte 0x00 "UART1_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART1_S1,UART Status Register 1" newline in newline else rgroup.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif group.byte 0x05++0x01 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" newline bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" newline bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" newline bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at length of)" "Disabled,11/12 bit times" newline rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART1_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output" newline bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART1_D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "UART1_MA1,UART Match Address Registers 1" line.byte 0x01 "UART1_MA2,UART Match Address Registers 2" line.byte 0x02 "UART1_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" newline bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART1_C5,UART control register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART1_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART1_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" newline bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 1 FIFO Registers" if (((per.b(ad:0x4006B000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006B000+0x12))&0xC0)==0xC0) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" newline bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" newline eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" if (((per.b(ad:0x4006B000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006B000+0x03))&0x08)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count" tree.end width 0x0B tree.end tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIOA" base ad:0x400FF000 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOA_PDOR_set/clr,Port A Data Output Register" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port data output 20" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO13 ,Port data output 13" "Logic 0,Logic 1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO12 ,Port data output 12" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOA_PTOR,Port A Toggle Output Register" bitfld.long 0x00 20. " PTTO20 ,Port toggle output 20" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PTTO13 ,Port toggle output 13" "No change,Inverse logic" bitfld.long 0x00 12. " PTTO12 ,Port toggle output 12" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" newline endif bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" newline bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_PDIR,Port A Data Input Register" bitfld.long 0x00 20. " PDI20 ,Port data input 20" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PDI13 ,Port data input 13" "Logic 0,Logic 1" bitfld.long 0x00 12. " PDI12 ,Port data input 12" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" newline endif bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" newline bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" group.long 0x14++0x03 line.long 0x00 "GPIOA_PDDR,Port A Data Direction Register" bitfld.long 0x00 20. " PDD20 ,Port data direction 20" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PDD13 ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " PDD12 ,Port data direction 12" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" newline endif bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" width 0x0B tree.end tree "GPIOB" base ad:0x400FF040 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOB_PDOR_set/clr,Port B Data Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOB_PTOR,Port B Toggle Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" newline endif bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_PDIR,Port B Data Input Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" newline endif bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" group.long 0x14++0x03 line.long 0x00 "GPIOB_PDDR,Port B Data Direction Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" newline endif bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" width 0x0B tree.end tree "GPIOC" base ad:0x400FF080 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_set/clr,Port C Data Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO11 ,Port data output 11" "Logic 0,Logic 1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO10 ,Port data output 10" "Logic 0,Logic 1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO9 ,Port data output 9" "Logic 0,Logic 1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO8 ,Port data output 8" "Logic 0,Logic 1" endif newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port C Toggle Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PTTO11 ,Port toggle output 11" "No change,Inverse logic" bitfld.long 0x00 10. " PTTO10 ,Port toggle output 10" "No change,Inverse logic" bitfld.long 0x00 9. " PTTO9 ,Port toggle output 9" "No change,Inverse logic" bitfld.long 0x00 8. " PTTO8 ,Port toggle output 8" "No change,Inverse logic" endif newline bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port C Data Input Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PDI11 ,Port data input 11" "Logic 0,Logic 1" bitfld.long 0x00 10. " PDI10 ,Port data input 10" "Logic 0,Logic 1" bitfld.long 0x00 9. " PDI9 ,Port data input 9" "Logic 0,Logic 1" bitfld.long 0x00 8. " PDI8 ,Port data input 8" "Logic 0,Logic 1" endif newline bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port C Data Direction Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PDD11 ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " PDD10 ,Port data direction 10" "Input,Output" bitfld.long 0x00 9. " PDD9 ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " PDD8 ,Port data direction 8" "Input,Output" endif newline bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree "GPIOD" base ad:0x400FF0C0 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOD_PDOR_set/clr,Port D Data Output Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOD_PTOR,Port D Toggle Output Register" bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_PDIR,Port D Data Input Register" bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOD_PDDR,Port D Data Direction Register" bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree "GPIOE" base ad:0x400FF100 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOE_PDOR_set/clr,Port E Data Output Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO31 ,Port data output 31" "Logic 0,Logic 1" endif setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO30 ,Port data output 30" "Logic 0,Logic 1" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO29 ,Port data output 29" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO25 ,Port data output 25" "Logic 0,Logic 1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO24 ,Port data output 24" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO23 ,Port data output 23" "Logic 0,Logic 1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO22 ,Port data output 22" "Logic 0,Logic 1" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO21 ,Port data output 21" "Logic 0,Logic 1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port data output 20" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOE_PTOR,Port E Toggle Output Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PTTO31 ,Port toggle output 31" "No change,Inverse logic" endif bitfld.long 0x00 30. " PTTO30 ,Port toggle output 30" "No change,Inverse logic" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PTTO29 ,Port toggle output 29" "No change,Inverse logic" newline endif bitfld.long 0x00 25. " PTTO25 ,Port toggle output 25" "No change,Inverse logic" bitfld.long 0x00 24. " PTTO24 ,Port toggle output 24" "No change,Inverse logic" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PTTO23 ,Port toggle output 23" "No change,Inverse logic" bitfld.long 0x00 22. " PTTO22 ,Port toggle output 22" "No change,Inverse logic" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PTTO21 ,Port toggle output 21" "No change,Inverse logic" bitfld.long 0x00 20. " PTTO20 ,Port toggle output 20" "No change,Inverse logic" newline endif bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No change,Inverse logic" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif newline rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_PDIR,Port E Data Input Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PDI31 ,Port data input 31" "Logic 0,Logic 1" endif bitfld.long 0x00 30. " PDI30 ,Port data input 30" "Logic 0,Logic 1" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PDI29 ,Port data input 29" "Logic 0,Logic 1" newline endif bitfld.long 0x00 25. " PDI25 ,Port data input 25" "Logic 0,Logic 1" bitfld.long 0x00 24. " PDI24 ,Port data input 24" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PDI23 ,Port data input 23" "Logic 0,Logic 1" bitfld.long 0x00 22. " PDI22 ,Port data input 22" "Logic 0,Logic 1" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PDI21 ,Port data input 21" "Logic 0,Logic 1" bitfld.long 0x00 20. " PDI20 ,Port data input 20" "Logic 0,Logic 1" newline endif bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif newline group.long 0x14++0x03 line.long 0x00 "GPIOE_PDDR,Port E Data Direction Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PDD31 ,Port data direction 31" "Input,Output" endif bitfld.long 0x00 30. " PDD30 ,Port data direction 30" "Input,Output" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PDD29 ,Port data direction 29" "Input,Output" newline endif bitfld.long 0x00 25. " PDD25 ,Port data direction 25" "Input,Output" bitfld.long 0x00 24. " PDD24 ,Port data direction 24" "Input,Output" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PDD23 ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " PDD22 ,Port data direction 22" "Input,Output" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PDD21 ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " PDD20 ,Port data direction 20" "Input,Output" newline endif bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree.end tree.open "FGPIO (Fast General Purpose Input/Output)" tree "FGPIOA" base ad:0xF8000000 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOA_PDOR_set/clr,Port A Data Output Register" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port data output 20" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO13 ,Port data output 13" "Logic 0,Logic 1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO12 ,Port data output 12" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOA_PTOR,Port A Toggle Output Register" bitfld.long 0x00 20. " PTTO20 ,Port toggle output 20" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PTTO13 ,Port toggle output 13" "No change,Inverse logic" bitfld.long 0x00 12. " PTTO12 ,Port toggle output 12" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" newline endif bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" newline bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_PDIR,Port A Data Input Register" bitfld.long 0x00 20. " PDI20 ,Port data input 20" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PDI13 ,Port data input 13" "Logic 0,Logic 1" bitfld.long 0x00 12. " PDI12 ,Port data input 12" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" newline endif bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" newline bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" group.long 0x14++0x03 line.long 0x00 "GPIOA_PDDR,Port A Data Direction Register" bitfld.long 0x00 20. " PDD20 ,Port data direction 20" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" newline sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 13. " PDD13 ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " PDD12 ,Port data direction 12" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" newline endif bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" newline bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" width 0x0B tree.end tree "FGPIOB" base ad:0xF8000040 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOB_PDOR_set/clr,Port B Data Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOB_PTOR,Port B Toggle Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" newline endif bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_PDIR,Port B Data Input Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" newline endif bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" group.long 0x14++0x03 line.long 0x00 "GPIOB_PDDR,Port B Data Direction Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" newline endif sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" newline endif bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" width 0x0B tree.end tree "FGPIOC" base ad:0xF8000080 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_set/clr,Port C Data Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO11 ,Port data output 11" "Logic 0,Logic 1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO10 ,Port data output 10" "Logic 0,Logic 1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO9 ,Port data output 9" "Logic 0,Logic 1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO8 ,Port data output 8" "Logic 0,Logic 1" endif newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port C Toggle Output Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PTTO11 ,Port toggle output 11" "No change,Inverse logic" bitfld.long 0x00 10. " PTTO10 ,Port toggle output 10" "No change,Inverse logic" bitfld.long 0x00 9. " PTTO9 ,Port toggle output 9" "No change,Inverse logic" bitfld.long 0x00 8. " PTTO8 ,Port toggle output 8" "No change,Inverse logic" endif newline bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port C Data Input Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PDI11 ,Port data input 11" "Logic 0,Logic 1" bitfld.long 0x00 10. " PDI10 ,Port data input 10" "Logic 0,Logic 1" bitfld.long 0x00 9. " PDI9 ,Port data input 9" "Logic 0,Logic 1" bitfld.long 0x00 8. " PDI8 ,Port data input 8" "Logic 0,Logic 1" endif newline bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port C Data Direction Register" sif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 11. " PDD11 ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " PDD10 ,Port data direction 10" "Input,Output" bitfld.long 0x00 9. " PDD9 ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " PDD8 ,Port data direction 8" "Input,Output" endif newline bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree "FGPIOD" base ad:0xF80000C0 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOD_PDOR_set/clr,Port D Data Output Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOD_PTOR,Port D Toggle Output Register" bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_PDIR,Port D Data Input Register" bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOD_PDDR,Port D Data Direction Register" bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline sif cpuis("MKV10Z32VLF7")||cpuis("MKV10Z16VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree "FGPIOE" base ad:0xF8000100 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOE_PDOR_set/clr,Port E Data Output Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO31 ,Port data output 31" "Logic 0,Logic 1" endif setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO30 ,Port data output 30" "Logic 0,Logic 1" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO29 ,Port data output 29" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO25 ,Port data output 25" "Logic 0,Logic 1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO24 ,Port data output 24" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO23 ,Port data output 23" "Logic 0,Logic 1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO22 ,Port data output 22" "Logic 0,Logic 1" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO21 ,Port data output 21" "Logic 0,Logic 1" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port data output 20" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port data output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif width 12. newline wgroup.long 0x0C++0x03 line.long 0x00 "GPIOE_PTOR,Port E Toggle Output Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PTTO31 ,Port toggle output 31" "No change,Inverse logic" endif bitfld.long 0x00 30. " PTTO30 ,Port toggle output 30" "No change,Inverse logic" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PTTO29 ,Port toggle output 29" "No change,Inverse logic" newline endif bitfld.long 0x00 25. " PTTO25 ,Port toggle output 25" "No change,Inverse logic" bitfld.long 0x00 24. " PTTO24 ,Port toggle output 24" "No change,Inverse logic" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PTTO23 ,Port toggle output 23" "No change,Inverse logic" bitfld.long 0x00 22. " PTTO22 ,Port toggle output 22" "No change,Inverse logic" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PTTO21 ,Port toggle output 21" "No change,Inverse logic" bitfld.long 0x00 20. " PTTO20 ,Port toggle output 20" "No change,Inverse logic" newline endif bitfld.long 0x00 19. " PTTO19 ,Port toggle output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No change,Inverse logic" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif newline rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_PDIR,Port E Data Input Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PDI31 ,Port data input 31" "Logic 0,Logic 1" endif bitfld.long 0x00 30. " PDI30 ,Port data input 30" "Logic 0,Logic 1" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PDI29 ,Port data input 29" "Logic 0,Logic 1" newline endif bitfld.long 0x00 25. " PDI25 ,Port data input 25" "Logic 0,Logic 1" bitfld.long 0x00 24. " PDI24 ,Port data input 24" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PDI23 ,Port data input 23" "Logic 0,Logic 1" bitfld.long 0x00 22. " PDI22 ,Port data input 22" "Logic 0,Logic 1" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PDI21 ,Port data input 21" "Logic 0,Logic 1" bitfld.long 0x00 20. " PDI20 ,Port data input 20" "Logic 0,Logic 1" newline endif bitfld.long 0x00 19. " PDI19 ,Port data input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif newline group.long 0x14++0x03 line.long 0x00 "GPIOE_PDDR,Port E Data Direction Register" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 31. " PDD31 ,Port data direction 31" "Input,Output" endif bitfld.long 0x00 30. " PDD30 ,Port data direction 30" "Input,Output" sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 29. " PDD29 ,Port data direction 29" "Input,Output" newline endif bitfld.long 0x00 25. " PDD25 ,Port data direction 25" "Input,Output" bitfld.long 0x00 24. " PDD24 ,Port data direction 24" "Input,Output" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 23. " PDD23 ,Port data direction 23" "Input,Output" bitfld.long 0x00 22. " PDD22 ,Port data direction 22" "Input,Output" endif sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 21. " PDD21 ,Port data direction 21" "Input,Output" bitfld.long 0x00 20. " PDD20 ,Port data direction 20" "Input,Output" newline endif bitfld.long 0x00 19. " PDD19 ,Port data direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output" newline sif cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree.end elif cpuis("MKV3*") tree.open "PORT (Port control and interrupts)" tree "PORTA" base ad:0x40049000 width 13. group.long 0x00++0x13 line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,UART0_CTS_b,FTM0_CH5,,EWM_IN,,JTAG_TCLK/SWD_CLK" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif (cpuis("MKV30F*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM2_CH0,CMP0_OUT,FTM2_QD_PHA,FTM1_CH1,JTAG_TDI" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM0_CH6,CMP0_OUT,FTM2_QD_PHA,FTM1_CH1,JTAG_TDI" endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV30F*") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM2_CH1,CMP1_OUT,FTM2_QD_PHB,FTM1_CH0,JTAG_TDO/TRACE_SWO" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM0_CH7,CMP1_OUT,FTM2_QD_PHB,FTM1_CH0,JTAG_TDO/TRACE_SWO" endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,UART0_RTS_b,FTM0_CH0,FTM2_FLT0,EWM_OUT_b,,JTAG_TMS/SWD_DIO" bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4/LLWU_P3,,FTM0_CH1,,FTM0_FLT3,,NMI_b" bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA5,,FTM0_CH2,,,,JTAG_TRST_b" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x30++0x07 line.long 0x00 "PORTA_PCR12,Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA12,,FTM1_CH0,,,,FTM1_QD_PHA" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR13,Pin Control Register 13" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA13/LLWU_P4,,FTM1_CH1,,,,FTM1_QD_PHB" bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") group.long 0x38++0x0F line.long 0x00 "PORTA_PCR14,Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA14,SPI0_PCS0,UART0_TX,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR15,Pin Control Register 15" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA15,SPI0_SCK,UART0_RX,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR16,Pin Control Register 16" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA16,SPI0_SOUT,UART0_CTS_b,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR17,Pin Control Register 17" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE17,PTA17,SPI0_SIN,UART0_RTS_b,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x48++0x07 line.long 0x00 "PORTA_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,,FTM0_FLT2,FTM_CLKIN0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,FTM0_FLT0,FTM1_FLT0,FTM_CLKIN1,,LPTMR0_ALT1,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin 14 write enable" "Disabled,Enabled" newline endif sif !cpuis("MKV30F128VLF10P") bitfld.long 0x00 29. " GPWE[13] ,Global pin 13 write enable" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" newline endif bitfld.long 0x00 20. " GPWE[4] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " GPWE[2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" sif cpuis("MKV31F512VLL12P") newline bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" endif newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" bitfld.long 0x00 15. " GPWD15 ,Global pin 15 write data" "Low,High" bitfld.long 0x00 14. " GPWD14 ,Global pin 14 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 13. " GPWD13 ,Global pin 13 write data" "Low,High" bitfld.long 0x00 12. " GPWD12 ,Global pin 12 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" newline endif bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" newline bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" bitfld.long 0x04 15. " GPWD15 ,Global pin 15 write data" "Low,High" bitfld.long 0x04 14. " GPWD14 ,Global pin 14 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x04 13. " GPWD13 ,Global pin 13 write data" "Low,High" bitfld.long 0x04 12. " GPWD12 ,Global pin 12 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" newline endif bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 19. " ISF[19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 15. " [15] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 14. " [14] ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") newline eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 12. " [12] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" endif newline eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" bitfld.long 0x00 19. " DFE[19] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Digital filter enable" "Disabled,Enabled" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline bitfld.long 0x00 17. " [17] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") newline bitfld.long 0x00 13. " [13] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 4. " [4] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)" line.long 0x08 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTB" base ad:0x4004A000 width 13. group.long 0x00++0x07 line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE8/ADC1_SE8,PTB0/LLWU_P5,I2C0_SCL,FTM1_CH0,,,FTM1_QD_PHA,UART0_RX" bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE9/ADC1_SE9,PTB1,I2C0_SDA,FTM1_CH1,FTM0_FLT2,EWM_IN,FTM1_QD_PHB,UART0_TX" bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") group.long 0x08++0x07 line.long 0x00 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTB2,I2C0_SCL,UART0_RTS_b,FTM0_FLT1,,FTM0_FLT3,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTB3,I2C0_SDA,UART0_CTS_b,,,FTM0_FLT0,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") group.long 0x24++0x0B line.long 0x00 "PORTB_PCR9,Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB9,SPI1_PCS1,LPUART0_CTS_b,,FB_AD20,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB9,SPI1_PCS1,LPUART0_CTS_b,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR10,Pin Control Register 10" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE14,PTB10,SPI1_PCS0,LPUART0_RX,,FB_AD19,FTM0_FLT1,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE14,PTB10,SPI1_PCS0,LPUART0_RX,,,FTM0_FLT1,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR11,Pin Control Register 11" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE15,PTB11,SPI1_SCK,LPUART0_TX,,FB_AD18,FTM0_FLT2,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE15,PTB11,SPI1_SCK,LPUART0_TX,,,FTM0_FLT2,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") group.long 0x40++0x07 line.long 0x00 "PORTB_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,SPI1_SOUT,UART0_RX,FTM_CLKIN0,,EWM_IN,?..." elif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,SPI1_SOUT,UART0_RX,FTM_CLKIN0,FB_AD17,EWM_IN,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,UART0_RX,FTM_CLKIN0,,EWM_IN,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,SPI1_SIN,UART0_TX,FTM_CLKIN1,,EWM_OUT_b,?..." elif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,SPI1_SIN,UART0_TX,FTM_CLKIN1,FB_AD16,EWM_OUT_b,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,UART0_TX,FTM_CLKIN1,,EWM_OUT_b,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") group.long 0x48++0x07 line.long 0x00 "PORTB_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB18,,FTM2_CH0,,FB_AD15,FTM2_QD_PHA,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB18,,FTM2_CH0,,,FTM2_QD_PHA,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB19,,FTM2_CH1,,FB_OE_b,FTM2_QD_PHB,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB19,,FTM2_CH1,,,FTM2_QD_PHB,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") group.long 0x50++0x0F line.long 0x00 "PORTB_PCR20,Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB20,,,,FB_AD31,CMP0_OUT,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB20,,,,,CMP0_OUT,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR21,Pin Control Register 21" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB21,,,,FB_AD30,CMP1_OUT,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB21,,,,,CMP1_OUT,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR22,Pin Control Register 22" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB22,,,,FB_AD29,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTB22,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR23,Pin Control Register 23" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTB23,,SPI0_PCS5,,FB_AD28,?..." else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTB23,,SPI0_PCS5,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" else bitfld.long 0x00 19. " GPWE[3] ,Global pin 3 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x04 23. " GPWE[23] ,Global pin 23 write enable" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Global pin 22 write enable" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Global pin 21 write enable" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Global pin 20 write enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" else bitfld.long 0x04 17. " GPWE[17] ,Global pin 17 write enable" "Disabled,Enabled" endif newline bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 23. " GPWE23 ,Global pin 23 write enable" "No,Yes" bitfld.long 0x00 22. " GPWE22 ,Global pin 22 write enable" "No,Yes" bitfld.long 0x00 21. " GPWE21 ,Global pin 21 write enable" "No,Yes" bitfld.long 0x00 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10") bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 11. " GPWD11 ,Global pin 11 write data" "Low,High" bitfld.long 0x00 10. " GPWD10 ,Global pin 10 write data" "Low,High" bitfld.long 0x00 9. " GPWD9 ,Global pin 9 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10") bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" endif bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" newline bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "No,Yes" bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "No,Yes" bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "No,Yes" bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "No,Yes" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "No,Yes" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10") bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 11. " GPWD11 ,Global pin 11 write data" "Low,High" bitfld.long 0x04 10. " GPWD10 ,Global pin 10 write data" "Low,High" bitfld.long 0x04 9. " GPWD9 ,Global pin 9 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10") bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" endif bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" newline bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") eventfld.long 0x00 23. " ISF23 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 22. " ISF22 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 21. " ISF21 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 20. " ISF20 ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") newline eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline eventfld.long 0x00 11. " ISF11 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") newline eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" endif newline eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 23. " DFE23 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 22. " DFE22 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 21. " DFE21 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 20. " DFE20 ,Digital filter enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") newline bitfld.long 0x00 19. " DFE19 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") newline bitfld.long 0x00 17. " DFE17 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital filter enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline bitfld.long 0x00 11. " DFE11 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") newline bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)" line.long 0x08 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTC" base ad:0x4004B000 width 13. sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") group.long 0x00++0x03 line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,SPI0_PCS4,PDB0_EXTRG,,FB_AD14,FTM0_FLT1,SPI0_PCS0" elif cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,SPI0_PCS4,PDB0_EXTRG,,,FTM0_FLT1,SPI0_PCS0" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTC0,SPI0_PCS4,PDB0_EXTRG,,CMP0_OUT,FTM0_FLT1,SPI0_PCS0" endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x1B line.long 0x00 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,FB_AD13,,LPUART0_RTS_b" elif cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,,,LPUART0_RTS_b" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,FTM2_CH0,?..." textfld " " endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE4b/CMP1_IN0,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,FB_AD12,,LPUART0_CTS_b" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE4b/CMP1_IN0,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,,,LPUART0_CTS_b" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE4b/CMP1_IN0,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,FTM2_CH1,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,,LPUART0_RX" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,FB_AD11,CMP1_OUT,LPUART0_TX" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,LPUART0_TX" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,FB_AD10,CMP0_OUT,FTM0_CH2" else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,,,CMP0_OUT,FTM0_CH2" endif bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,,FB_AD9,,I2C0_SCL" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,,,,I2C0_SCL" elif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,,UART0_RX,,I2C0_SCL" else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,,UART0_RX,,I2C0_SCL" endif bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,,,FB_AD8,,I2C0_SDA" elif cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,,,,,I2C0_SDA" elif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTC7,SPI0_SIN,,,UART0_TX,,I2C0_SDA" else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTC7,SPI0_SIN,,,UART0_TX,,I2C0_SDA" endif bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") group.long 0x20++0x0F line.long 0x00 "PORTC_PCR8,Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE4B/CMP0_IN2,PTC8,,FTM3_CH4,,FB_AD7,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE4B/CMP0_IN2,PTC8,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR9,Pin Control Register 9" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE5B/CMP0_IN3,PTC9,,FTM3_CH5,,FB_AD6,FTM2_FLT0,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE5B/CMP0_IN3,PTC9,,,,,FTM2_FLT0,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR10,Pin Control Register 10" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE6b,PTC10,I2C1_SCL,FTM3_CH6,,FB_AD5,?..." elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE6b,PTC10,I2C1_SCL,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC1_SE6b,PTC10,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR11,Pin Control Register 11" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE7b,PTC11/LLWU_P11,I2C1_SDA,FTM3_CH7,,FB_RW_B,?..." elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE7b,PTC11/LLWU_P11,I2C1_SDA,?..." else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC1_SE7b,PTC11/LLWU_P11,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") group.long 0x30++0x1B line.long 0x00 "PORTC_PCR12,Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC12,,,,FB_AD27,FTM3_FLT0,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTC12,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR13,Pin Control Register 13" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC13,,,,FB_AD26,?..." else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTC13,?..." endif newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR14,Pin Control Register 14" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTC14,,,,FB_AD25,?..." else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTC14,?..." endif newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR15,Pin Control Register 15" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC15,,,,FB_AD24,?..." else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTC15,?..." endif newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTC_PCR16,Pin Control Register 16" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC16,,LPUART0_RX,,FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b,?..." else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC16,,LPUART0_RX,?..." endif newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTC_PCR17,Pin Control Register 17" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC17,,LPUART0_TX,,FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b,?..." else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC17,,LPUART0_TX,?..." endif newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTC_PCR18,Pin Control Register 18" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTC18,,LPUART0_RTS_b,,FB_TBST_B/FB_CS2_b/FB_BE15_8_BLS23_16_b,?..." else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTC18,,LPUART0_RTS_b,?..." endif newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" endif newline sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") wgroup.long 0x80++0x03 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Disabled,Enabled" bitfld.long 0x00 30. " [14] ,Global pin 14 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " [13] ,Global pin 13 write enable" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [11] ,Global pin 11 write enable" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Disabled,Enabled" elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Disabled,Enabled" else bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" sif cpuis("MKV31F512VLL12P") wgroup.long 0x80++0x03 line.long 0x00 "PORTC_GPCHR,Global Pin Control High Register" bitfld.long 0x00 18. " GPWE[18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" endif else wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x00 16. " GPWE16 ,Global pin 16 write enable" "No,Yes" newline bitfld.long 0x00 15. " GPWD15 ,Global pin 15 write data" "Low,High" bitfld.long 0x00 14. " GPWD14 ,Global pin 14 write data" "Low,High" bitfld.long 0x00 13. " GPWD13 ,Global pin 13 write data" "Low,High" bitfld.long 0x00 12. " GPWD12 ,Global pin 12 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 11. " GPWD11 ,Global pin 11 write data" "Low,High" bitfld.long 0x00 10. " GPWD10 ,Global pin 10 write data" "Low,High" bitfld.long 0x00 9. " GPWD9 ,Global pin 9 write data" "Low,High" bitfld.long 0x00 8. " GPWD8 ,Global pin 8 write data" "Low,High" newline endif bitfld.long 0x00 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10") bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif line.long 0x04 "PORTC_GPCLR,Global Pin Control High Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x04 16. " GPWE16 ,Global pin 17 write enable" "No,Yes" newline bitfld.long 0x04 15. " GPWD15 ,Global pin 15 write data" "Low,High" bitfld.long 0x04 14. " GPWD14 ,Global pin 14 write data" "Low,High" bitfld.long 0x04 13. " GPWD13 ,Global pin 13 write data" "Low,High" bitfld.long 0x04 12. " GPWD12 ,Global pin 12 write data" "Low,High" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 11. " GPWD11 ,Global pin 11 write data" "Low,High" bitfld.long 0x04 10. " GPWD10 ,Global pin 10 write data" "Low,High" bitfld.long 0x04 9. " GPWD9 ,Global pin 9 write data" "Low,High" bitfld.long 0x04 8. " GPWD8 ,Global pin 8 write data" "Low,High" newline endif bitfld.long 0x04 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x04 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif endif group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") eventfld.long 0x00 18. " ISF[18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 15. " [15] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 14. " [14] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 12. " [12] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 11. " [11] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" elif cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") eventfld.long 0x00 11. " ISF[11] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" else eventfld.long 0x00 7. " ISF[7] ,Interrupt status flag" "Not detected,Detected" endif newline eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F64VLF10R") newline eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 18. " DFE[18] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " [10] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Digital filter enable" "Disabled,Enabled" elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.long 0x00 11. " DFE[11] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Digital filter enable" "Disabled,Enabled" else bitfld.long 0x00 7. " DFE[7] ,Digital filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " [6] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter enable" "Disabled,Enabled" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F64VLF10R") newline bitfld.long 0x00 0. " [0] ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F512VLH12R") bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)" endif line.long 0x08 "PORTC_DFWR,Digital Filter Width Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10")||cpuis("MKV31F512VLH12R") bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x08 1.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "PORTD" base ad:0x4004C000 width 13. sif !cpuis("MKV31F512VLL12") group.long 0x00++0x0F line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0,UART2_RTS_b,FTM3_CH0,FB_ALE/FB_CS1_b/FB_TS_b,LPUART0_RTS_b,?..." elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0,UART2_RTS_b,FTM0_CH0,,LPUART0_RTS_b,?..." textfld " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0,UART0_RTS_b,FTM0_CH0,UART1_RX,?..." textfld " " endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5b,PTD1,SPI0_SCK,UART2_CTS_b,FTM3_CH1,FB_CS0_b,LPUART0_CTS_b,?..." elif cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5b,PTD1,SPI0_SCK,UART2_CTS_b,FTM0_CH1,,LPUART0_CTS_b,?..." elif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5b,PTD1,SPI0_SCK,UART0_CTS_b,FTM0_CH1,UART1_TX,?..." textfld " " endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART2_RX,FTM3_CH2,FB_AD4,LPUART0_RX,I2C0_SCL" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART2_RX,FTM0_CH2,,LPUART0_RX,I2C0_SCL" else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,UART0_RX,FTM0_CH2,,,I2C0_SCL" endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART2_TX,FTM3_CH3,FB_AD3,LPUART0_TX,I2C0_SDA" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART2_TX,FTM0_CH3,,LPUART0_TX,I2C0_SDA" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,UART0_TX,FTM0_CH3,,,I2C0_SDA" textfld " " endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x10++0x0F line.long 0x00 "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FB_AD2,EWM_IN,SPI1_PCS0" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,,EWM_IN,SPI1_PCS0" else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FTM2_CH0,EWM_IN,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6b,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,FB_AD1,EWM_OUT_b,SPI1_SCK" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6b,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,,EWM_OUT_b,SPI1_SCK" elif cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6b,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,FTM2_CH1,EWM_OUT_b,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE7b,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH6,FB_AD0,FTM0_FLT0,SPI1_SOUT" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE7b,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH6,,FTM0_FLT0,SPI1_SOUT" elif cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE7b,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH0,FTM1_CH0,FTM0_FLT0,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,,UART0_TX,FTM0_CH7,,FTM0_FLT1,SPI1_SIN" elif cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,,UART0_TX,FTM0_CH7,,FTM0_FLT1,SPI1_SIN" else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD7,,UART0_TX,FTM0_CH1,FTM1_CH1,FTM0_FLT1,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") wgroup.long 0x80++0x03 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" sif !cpuis("MKV31F512VLL12") newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif line.long 0x04 "PORTD_GPCLR,Global Pin Control High Register" bitfld.long 0x04 7. " GPWD7 ,Global pin 7 write data" "Low,High" bitfld.long 0x04 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" sif !cpuis("MKV31F512VLL12") newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif endif group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" sif !cpuis("MKV31F512VLL12") newline eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" sif !cpuis("MKV31F512VLL12") newline bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register" sif !cpuis("MKV31F512VLL12") bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO Clock(1kHz)" endif line.long 0x08 "PORTD_DFWR,Digital Filter Width Register" sif !cpuis("MKV31F512VLL12") bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0x0B tree.end tree "PORTE" base ad:0x4004D000 width 13. sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R") group.long 0x00++0x07 line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE4a,PTE0/CLKOUT32K,SPI1_PCS1,UART1_TX,,,I2C1_SDA,?..." else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE4a,PTE0/CLKOUT32K,,UART1_TX,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE5a,PTE1/LLWU_P0,SPI1_SOUT,UART1_RX,,,I2C1_SCL,SPI1_SIN" else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE5a,PTE1/LLWU_P0,,UART1_RX,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12R")&&!cpuis("MKV31F512VLH12R") group.long 0x08++0x13 line.long 0x00 "PORTE_PCR2,Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC1_SE6a,PTE2/LLWU_P1,SPI1_SCK,UART1_CTS_b,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR3,Pin Control Register 3" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC1_SE7a,PTE3,SPI1_SIN,UART1_RTS_b,,,,SPI1_SOUT" bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR4,Pin Control Register 4" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTE4/LLWU_P2,SPI1_PCS0,LPUART0_TX,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR5,Pin Control Register 5" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE5,SPI1_PCS2,LPUART0_RX,,,FTM3_CH0,?..." else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTE5,SPI1_PCS2,LPUART0_RX,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTE_PCR6,Pin Control Register 6" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTE6,SPI1_PCS3,LPUART0_CTS_b,,,FTM3_CH1,?..." else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTE6,SPI1_PCS3,LPUART0_CTS_b,?..." endif bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x40++0x0F line.long 0x00 "PORTE_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4a,PTE16,SPI0_PCS0,UART2_TX,FTM_CLKIN0,,FTM0_FLT3,?..." textfld " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4a/ADC0_DP1/ADC1_DP2,PTE16,SPI0_PCS0,UART1_TX,FTM_CLKIN0,,FTM0_FLT3,?..." endif bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5a,PTE17,SPI0_SCK,UART2_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." textfld " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5a/ADC0_DM1/ADC1_DM2,PTE17,SPI0_SCK,UART1_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." endif bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR18,Pin Control Register 18" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6a,PTE18,SPI0_SOUT,UART2_CTS_b,I2C0_SDA,?..." textfld " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE6a/ADC1_DP1/ADC0_DP2,PTE18,SPI0_SOUT,UART1_CTS_b,I2C0_SDA,?..." endif bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR19,Pin Control Register 19" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE7a,PTE19,SPI0_SIN,UART2_RTS_b,I2C0_SCL,?..." textfld " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE7a/ADC1_DM1/ADC0_DM2,PTE19,SPI0_SIN,UART1_RTS_b,I2C0_SCL,?..." endif bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x60++0x07 line.long 0x00 "PORTE_PCR24,Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE17,PTE24,,FTM0_CH0,,I2C0_SCL,EWM_OUT_b,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR25,Pin Control Register 25" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE18,PTE25,,FTM0_CH1,,I2C0_SDA,EWM_IN,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") group.long 0x68++0x03 line.long 0x00 "PORTE_PCR26,Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE26/CLKOUT32K,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") wgroup.long 0x80++0x03 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 22. " GPWE[6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" else bitfld.long 0x00 17. " GPWE[1] ,Global pin 1 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" endif wgroup.long 0x84++0x03 line.long 0x00 "PORTE_GPCHR,Global Pin Control High Register" sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 26. " GPWE[26] ,Global pin 26 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Global pin 25 write enable" "Disabled,Enabled" else bitfld.long 0x00 25. " GWPE[25] ,Global pin 25 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " [24] ,Global pin 24 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" else wgroup.long 0x80++0x07 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 26. " GPWE26 ,Global pin 26 write enable" "No,Yes" endif bitfld.long 0x00 25. " GPWE25 ,Global pin 5 write enable" "No,Yes" bitfld.long 0x00 24. " GPWE24 ,Global pin 24 write enable" "No,Yes" newline bitfld.long 0x00 19. " GPWE19 ,Global pin 3 write enable" "No,Yes" bitfld.long 0x00 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x00 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x00 16. " GPWE0 ,Global pin 16 write enable" "No,Yes" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x00 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD2 ,Global pin 2 write data" "Low,High" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif line.long 0x04 "PORTE_GPCHR,Global Pin Control High Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "No,Yes" endif bitfld.long 0x04 25. " GPWE25 ,Global pin 5 write enable" "No,Yes" bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "No,Yes" newline bitfld.long 0x04 19. " GPWE19 ,Global pin 3 write enable" "No,Yes" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "No,Yes" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "No,Yes" bitfld.long 0x04 16. " GPWE0 ,Global pin 16 write enable" "No,Yes" newline sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x04 6. " GPWD6 ,Global pin 6 write data" "Low,High" bitfld.long 0x04 5. " GPWD5 ,Global pin 5 write data" "Low,High" bitfld.long 0x04 4. " GPWD4 ,Global pin 4 write data" "Low,High" newline bitfld.long 0x04 3. " GPWD3 ,Global pin 3 write data" "Low,High" bitfld.long 0x04 2. " GPWD2 ,Global pin 2 write data" "Low,High" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x04 1. " GPWD1 ,Global pin 1 write data" "Low,High" bitfld.long 0x04 0. " GPWD0 ,Global pin 0 write data" "Low,High" endif endif group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") eventfld.long 0x00 26. " ISF26 ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 25. " ISF25 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 24. " ISF24 ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "Not detected,Detected" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") newline eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 26. " DFE26 ,Digital Filter Enable" "Disabled,Enabled" newline endif bitfld.long 0x00 25. " DFE25 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " DFE24 ,Digital Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " DFE19 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital Filter Enable" "Disabled,Enabled" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") newline bitfld.long 0x00 6. " DFE6 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital Filter Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " DFE2 ,Digital Filter Enable" "Disabled,Enabled" endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") newline bitfld.long 0x00 1. " DFE1 ,Digital Filter Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital Filter Enable" "Disabled,Enabled" endif line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") newline bitfld.long 0x04 0. " CS ,Clock Source" "Bus clock,LPO Clock(1kHz)" endif line.long 0x08 "PORTE_DFWR,Digital Filter Width Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV31F512VLH12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x08 0.--1. " FILT ,Filter length" "0,1,2,3" endif width 0x0B tree.end tree.end tree "SIM (System Integration Module)" base ad:0x40047000 width 9. group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "System,,,LPO" bitfld.long 0x00 16.--17. " OSC32KOUT ,32K oscillator clock output" "Disabled,Output on PTE0,Output on PTE26,?..." rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",8 kB,,16 kB,24 kB,32 kB,48 kB,64 kB,96 kB,128 kB,,256 kB,?..." base ad:0x40048000 group.long 0x04++0x03 line.long 0x00 "SOPT2,System Options Register 2" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock source select" "Disabled,SOPT2[PLLFLLSEL],OSCERCLK,MCGIRCLK" endif newline sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,,,IRC48 MHz" else bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,,IRC48 MHz" endif bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" newline sif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12") bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level" "All off-chip dis.,All off-chip dis.,Off-chip opcode dis./Data all.,Off-chip opcode all./Data all." bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" "FlexBus CLKOUT,,Flash,LPO,MCGIRCLK,OSC0ERCLK0,IRC 48 MHz," elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Flash,LPO,MCGIRCLK,,OSC0ERCLK0,IRC 48 MHz" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" "FlexBus CLKOUT,,Flash,LPO,MCGIRCLK,,OSC0ERCLK0,IRC 48 MHz" else bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" "FlexBus CLKOUT,,Flash,LPO,MCGIRCLK,OSC0ERCLK0,IRC 48 MHz," endif group.long 0x0C++0x07 line.long 0x00 "SOPT4,System Options Register 4" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 31. " FTM3TRG1SRC ,FlexTimer 3 hardware trigger 1 source select" ",FTM2" bitfld.long 0x00 30. " FTM3TRG0SRC ,FlexTimer 3 hardware trigger 0 source select" ",FTM1" bitfld.long 0x00 29. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB,FTM2" newline bitfld.long 0x00 28. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "HSCMP0,FTM1" bitfld.long 0x00 27. " FTM3CLKSEL ,FlexTimer 3 external clock pin" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 26. " FTM2CLKSEL ,FlexTimer 2 external clock pin select" "FTM_CLK0,FTM_CLK1" newline bitfld.long 0x00 25. " FTM1CLKSEL ,FlexTimer 1 external clock pin select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 24. " FTM0CLKSEL ,FlexTimer 0 external clock pin select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 22. " FTM2CH1SRC ,FTM2 channel 1 input capture source select" "FTM2_CH1,XOR(FTM2_CH1/0-FTM1_CH1)" newline bitfld.long 0x00 20.--21. " FTM2CH0SRC ,Flextimer 2 channel 0 input capture source select" "FTM2_CH0 signal,CMP0 output,CMP1 output," bitfld.long 0x00 18.--19. " FTM1CH0SRC ,Flextimer 1 channel 0 input capture source select" "FTM1_CH0,CMP0 output,CMP1 output," bitfld.long 0x00 12. " FTM3FLT0 ,Flextimer 3 fault 0 select" "FTM3_FLT0 pin,CMP0 out" newline bitfld.long 0x00 8. " FTM2FLT0 ,Flextimer 2 fault 0 select" "FTM2_FLT0 pin,CMP0 out" bitfld.long 0x00 4. " FTM1FLT0 ,FlexTimer 1 fault 0 select" "FTM1_FLT0 pin,CMP0 out" bitfld.long 0x00 1. " FTM0FLT1 ,FlexTimer 0 fault 1 select" "FTM0_FLT1,CMP1 out" newline bitfld.long 0x00 0. " FTM0FLT0 ,FlexTimer 0 fault 0 select" "FTM0_FLT0,CMP0 out" else bitfld.long 0x00 29. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB,FTM2" bitfld.long 0x00 28. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "HSCMP0,FTM1" bitfld.long 0x00 26. " FTM2CLKSEL ,FlexTimer 2 external clock pin select" "FTM_CLK0,FTM_CLK1" newline bitfld.long 0x00 25. " FTM1CLKSEL ,FlexTimer 1 External Clock Pin Select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 24. " FTM0CLKSEL ,FlexTimer 0 external clock pin select" "FTM_CLK0,FTM_CLK1" bitfld.long 0x00 22. " FTM2CH1SRC ,FTM2 channel 1 input capture source select" "FTM2_CH1,XOR(FTM2_CH1/0-FTM1_CH1)" newline bitfld.long 0x00 20.--21. " FTM2CH0SRC ,Flextimer 2 channel 0 input capture source select" "FTM2_CH0 signal,CMP0 output,CMP1 output,?..." bitfld.long 0x00 18.--19. " FTM1CH0SRC ,Flextimer 1 channel 0 input capture source select" "FTM1_CH0,CMP0 output,CMP1 output,?..." bitfld.long 0x00 8. " FTM2FLT0 ,Flextimer 2 fault 0 select" "FTM2_FLT0 pin,CMP0 out" newline bitfld.long 0x00 4. " FTM1FLT0 ,FlexTimer 1 fault 0 select" "FTM1_FLT0 pin,CMP0 out" bitfld.long 0x00 1. " FTM0FLT1 ,FlexTimer 0 fault 1 select" "FTM0_FLT1,CMP1 out" bitfld.long 0x00 0. " FTM0FLT0 ,FlexTimer 0 fault 0 select" "FTM0_FLT0,CMP0 out" endif line.long 0x04 "SOPT5,System Options Register 5" sif cpuis("MKV31F*") bitfld.long 0x04 18.--19. " LPUART0RXSRC ,LPUART0 receive data source select" "LPUART0_RX,CMP0,CMP1,?..." newline endif bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..." bitfld.long 0x04 4.--5. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX/FTM1 ch.0,UART1_TX/FTM2 ch.0,?..." bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX,CMP0,CMP1,?..." newline bitfld.long 0x04 0.--1. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX,UART0_TX/FTM1 ch.0,UART0_TX/FTM2 ch.0,?..." group.long 0x18++0x07 line.long 0x00 "SOPT7,System Options Register 7" bitfld.long 0x00 15. " ADC1ALTTRGEN ,ADC1 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x00 12. " ADC1PRETRGSEL ,ADC1 pre-trigger select" "Pre-trigger A,Pre-trigger B" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " ADC1TRGSEL ,ADC1 trigger select" "PDB0_EXTRG,HS comparator 0 Out,HS comparator 1 Out,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,,,Low-power timer trigger,?..." else bitfld.long 0x00 8.--11. " ADC1TRGSEL ,ADC1 trigger select" "PDB0_EXTRG,HS comparator 0 Out,HS comparator 1 Out,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,,,,Low-power timer trigger,?..." endif newline bitfld.long 0x00 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,HS comparator 0 Out,HS comparator 1 Out,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,,,Low-power timer trigger,?..." else bitfld.long 0x00 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,HS comparator 0 Out,HS comparator 1 Out,,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,,,,Low-power timer trigger,?..." endif line.long 0x04 "SOPT8,System Options Register 8" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x04 31. " FTM3OCH7SRC ,FTM3 channel 7 output source" "FTM3_CH7,FTM3_CH7 mod FTM2_CH1" bitfld.long 0x04 30. " FTM3OCH6SRC ,FTM3 channel 6 output source" "FTM3_CH6,FTM3_CH6 mod FTM2_CH1" bitfld.long 0x04 29. " FTM3OCH5SRC ,FTM3 channel 5 output source" "FTM3_CH5,FTM3_CH5 mod FTM2_CH1" newline bitfld.long 0x04 28. " FTM3OCH4SRC ,FTM3 channel 4 output source" "FTM3_CH4,FTM3_CH4 mod FTM2_CH1" bitfld.long 0x04 27. " FTM3OCH3SRC ,FTM3 channel 3 output source" "FTM3_CH3,FTM3_CH3 mod FTM2_CH1" bitfld.long 0x04 26. " FTM3OCH2SRC ,FTM3 channel 2 output source" "FTM3_CH2,FTM3_CH2 mod FTM2_CH1" newline bitfld.long 0x04 25. " FTM3OCH1SRC ,FTM3 channel 1 output source" "FTM3_CH1,FTM3_CH1 mod FTM2_CH1" bitfld.long 0x04 24. " FTM3OCH0SRC ,FTM3 channel 0 output source" "FTM3_CH0,FTM3_CH0 mod FTM2_CH1" bitfld.long 0x04 23. " FTM0OCH7SRC ,FTM0 channel 7 output source" "FTM0_CH7,FTM0_CH7 mod FTM2_CH1" newline bitfld.long 0x04 22. " FTM0OCH6SRC ,FTM0 channel 6 output source" "FTM0_CH6,FTM0_CH6 mod FTM2_CH1" bitfld.long 0x04 21. " FTM0OCH5SRC ,FTM0 channel 5 output source" "FTM0_CH5,FTM0_CH5 mod FTM2_CH1" bitfld.long 0x04 20. " FTM0OCH4SRC ,FTM0 channel 4 output source" "FTM0_CH4,FTM0_CH4 mod FTM2_CH1" newline bitfld.long 0x04 19. " FTM0OCH3SRC ,FTM0 channel 3 output source" "FTM0_CH3,FTM0_CH3 mod FTM2_CH1" bitfld.long 0x04 18. " FTM0OCH2SRC ,FTM0 channel 2 output source" "FTM0_CH2,FTM0_CH2 mod FTM2_CH1" bitfld.long 0x04 17. " FTM0OCH1SRC ,FTM0 channel 1 output source" "FTM0_CH1,FTM0_CH1 mod FTM2_CH1" newline bitfld.long 0x04 16. " FTM0OCH0SRC ,FTM0 channel 0 output source" "FTM0_CH0,FTM0_CH0 mod FTM2_CH1" bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM3" bitfld.long 0x04 2. " FTM2SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM2" newline bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM1" bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM0" else sif !cpuis("MKV30F*") bitfld.long 0x04 23. " FTM0OCH7SRC ,FTM0 channel 7 output source" "FTM0_CH7,FTM0_CH7 mod FTM2_CH1" bitfld.long 0x04 22. " FTM0OCH6SRC ,FTM0 channel 6 output source" "FTM0_CH6,FTM0_CH6 mod FTM2_CH1" newline endif bitfld.long 0x04 21. " FTM0OCH5SRC ,FTM0 channel 5 output source" "FTM0_CH5,FTM0_CH5 mod FTM2_CH1" bitfld.long 0x04 20. " FTM0OCH4SRC ,FTM0 channel 4 output source" "FTM0_CH4,FTM0_CH4 mod FTM2_CH1" bitfld.long 0x04 19. " FTM0OCH3SRC ,FTM0 channel 3 output source" "FTM0_CH3,FTM0_CH3 mod FTM2_CH1" newline bitfld.long 0x04 18. " FTM0OCH2SRC ,FTM0 channel 2 output source" "FTM0_CH2,FTM0_CH2 mod FTM2_CH1" bitfld.long 0x04 17. " FTM0OCH1SRC ,FTM0 channel 1 output source" "FTM0_CH1,FTM0_CH1 mod FTM2_CH1" bitfld.long 0x04 16. " FTM0OCH0SRC ,FTM0 channel 0 output source" "FTM0_CH0,FTM0_CH0 mod FTM2_CH1" newline sif !cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM3" newline endif bitfld.long 0x04 2. " FTM2SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM2" bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM1" bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,TRIG0 to FTM0" endif rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis family ID" ",KV1x,KV2x,KV3x,KV4x,,KV6x,KV7x,?..." bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" "KVx0,KVx1,KVx2,KVx3,KVx4,KVx5,KVx6,?..." bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" "Kinetis K,Kinetis L,,,,Kinetis W,Kinetis V,?..." newline bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,32-pin,,48-pin,64-pin,80-pin,81/121-pin,100-pin,121-pin,144-pin,Custom,169-pin,,256-pin,?..." group.long 0x34++0x0F line.long 0x00 "SCGC4,System Clock Gating Control Register 4" bitfld.long 0x00 20. " VREF ,VREF clock gate control" "Disabled,Enabled" bitfld.long 0x00 19. " CMP ,Comparator clock gate control" "Disabled,Enabled" sif !cpuis("MKV30F*") newline bitfld.long 0x00 12. " UART2 ,UART2 clock gate control" "Disabled,Enabled" endif newline bitfld.long 0x00 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 7. " I2C1 ,I2C1 clock gate control" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled" bitfld.long 0x00 1. " EWM ,EWM clock gate control" "Disabled,Enabled" line.long 0x04 "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x04 13. " PORTE ,Port E clock gate control" "Disabled,Enabled" bitfld.long 0x04 12. " PORTD ,Port D clock gate control" "Disabled,Enabled" bitfld.long 0x04 11. " PORTC ,Port C clock gate control" "Disabled,Enabled" newline bitfld.long 0x04 10. " PORTB ,Port B clock gate control" "Disabled,Enabled" bitfld.long 0x04 9. " PORTA ,Port A clock gate control" "Disabled,Enabled" bitfld.long 0x04 0. " LPTMR ,Low power timer access control" "Disabled,Enabled" line.long 0x08 "SCGC6,System Clock Gating Control Register 6" bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 27. " ADC0 ,ADC0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 26. " FTM2 ,FTM2 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 25. " FTM1 ,FTM1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 24. " FTM0 ,FTM0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 23. " PIT ,PIT clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 22. " PDB ,PDB clock gate control" "Disabled,Enabled" bitfld.long 0x08 18. " CRC ,CRC clock gate control" "Disabled,Enabled" sif !cpuis("MKV30F*") newline bitfld.long 0x08 13. " SPI1 ,DSPI1 clock gate control" "Disabled,Enabled" endif newline bitfld.long 0x08 12. " SPI0 ,DSPI0 clock gate control" "Disabled,Enabled" sif !cpuis("MKV30F*") newline bitfld.long 0x08 10. " LPUART0 ,LPUART0 clock gate control" "Disabled,Enabled" sif !cpuis("MKV31F128VLH10P") newline bitfld.long 0x08 9. " RNGA , RNGA clock gate control" "Disabled,Enabled" endif endif newline sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") bitfld.long 0x08 8. " DAC1 ,DAC1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 7. " ADC1 ,ADC1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 3. " FTM3 ,FTM3 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" else bitfld.long 0x08 7. " ADC1 ,ADC1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" endif line.long 0x0C "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x0C 1. " DMA ,DMA clock gate control" "Disabled,Enabled" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x0C 0. " FLEXBUS ,FlexBus clock gate control" "Disabled,Enabled" endif if (((per.b(ad:0x4007E001))&0x60)==0x40) rgroup.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 20.--23. " OUTDIV3 ,Clock 3 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif newline bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else group.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 20.--23. " OUTDIV3 ,Clock 3 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif newline bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif group.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,256 KB" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,128 KB" else rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,32 KB,,64 KB,,128 KB,,256 KB,,512 KB,,1024 KB,,512 KB" endif newline bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "No,Yes" bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes" rgroup.long 0x50++0x13 line.long 0x00 "FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block 0" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") newline hexmask.long.byte 0x00 16.--22. 1. " MAXADDR1 ,Max address block 1" endif line.long 0x04 "UIDH,Unique Identification Register High" line.long 0x08 "UIDMH,Unique Identification Register Mid-High" line.long 0x0C "UIDML,Unique Identification Register Mid Low" line.long 0x10 "UIDL,Unique Identification Register Low" width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "No reset,Reset" bitfld.byte 0x00 6. " PIN ,External reset pin" "No reset,Reset" bitfld.byte 0x00 5. " WDOG ,Watchdog" "No reset,Reset" newline sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "No reset,Reset" endif newline bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "No reset,Reset" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "No reset,Reset" bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "No reset,Reset" line.byte 0x01 "SRS1,System Reset Status Register 1" bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") bitfld.byte 0x01 4. " EZPT ,EzPort reset" "No reset,Reset" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "No reset,Reset" else bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "No reset,Reset" endif bitfld.byte 0x01 2. " SW ,Software" "No reset,Reset" newline bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "No reset,Reset" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "No reset,Reset" group.byte 0x04++0x01 line.byte 0x00 "RPFC,Reset Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All filtering disabled,LPO clock filter enabled" bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All filtering disabled,Bus clock filter enabled,LPO clock filter enabled,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") rgroup.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1. " EZP_MS ,EZP_MS_B pin state" "Negated,Asserted" endif group.byte 0x08++0x01 line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "No reset,Reset" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "No reset,Reset" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV31F128VLH10P") eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "No reset,Reset" eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset" newline eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "No reset,Reset" else eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset" eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "No reset,Reset" endif line.byte 0x01 "SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") eventfld.byte 0x01 4. " SEZPT ,Sticky EzPort reset" "No reset,Reset" eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset" else eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset" endif newline eventfld.byte 0x01 2. " SSW ,Sticky software" "No reset,Reset" eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "No reset,Reset" eventfld.byte 0x01 0. " SJTAG ,Sticky JTAG generated reset" "No reset,Reset" width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" bitfld.byte 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" sif !cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") newline bitfld.byte 0x00 3. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" endif newline bitfld.byte 0x00 1. " AVLLS ,Allow very low leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High Speed Run mode" rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,,VLLSx,?..." else sif cpuis("MKV31F512*") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High Speed Run mode" else bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,?..." endif rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLSx,VLLSx,?..." endif sif cpuis("MKV58F1M0V??24")||cpuis("MKV56F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "No,Yes" bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif else if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?" bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12*") bitfld.byte 0x00 7. " HSRUN ,Current power mode is HSRUN" "No,Yes" bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "No,Yes" bitfld.byte 0x00 5. " LLS ,Current power mode is LLS" "No,Yes" newline bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "No,Yes" bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "No,Yes" bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "No,Yes" newline bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "No,Yes" bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "No,Yes" endif width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip,High trip,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status and Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Clear" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip,Mid 1 trip,Mid 2 trip,High trip" line.byte 0x02 "REGSC,Regulator Status and Control Register" sif cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*") bitfld.byte 0x02 6. " VLPO ,VLPx option" "Restricted,Unrestricted" newline endif sif !cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*") bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Enabled,Disabled" newline endif eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled" rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stopped,Running" bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" width 0x0B tree.end tree "LLWU (Low-Leakage Wakeup Unit)" base ad:0x4007C000 width 7. sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") group.byte 0x00++0x00 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE[3] ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any change" newline sif !cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x00 4.--5. " [2] ,Wakeup pin enable for LLWU_P2" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x00 2.--3. " [1] ,Wakeup pin enable for LLWU_P1" "Disabled,Rising edge,Falling edge,Any change" newline endif bitfld.byte 0x00 0.--1. " [0] ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any change" endif group.byte 0x01++0x05 line.byte 0x00 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x00 6.--7. " WUPE[7] ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x00 4.--5. " [6] ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x00 2.--3. " [5] ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any change" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") newline bitfld.byte 0x00 0.--1. " [4] ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x01 "PE3,LLWU Pin Enable 3 Register" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") bitfld.byte 0x01 6.--7. " WUPE[11] ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 4.--5. " [10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" else bitfld.byte 0x01 4.--5. " WUPE[10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" endif newline bitfld.byte 0x01 2.--3. " [9] ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 0.--1. " [8] ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x02 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x02 6.--7. " WUPE[15] ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 4.--5. " [14] ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 2.--3. " [13] ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 0.--1. " [12] ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x03 "ME,LLWU Module Enable Register" bitfld.byte 0x03 2. " WUME[2] ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x03 1. " [1] ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x03 0. " [0] ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x04 "F1,LLWU Flag 1 Register" eventfld.byte 0x04 7. " WUF[7] ,Wakeup flag for LLWU_P7" "Disabled,Enabled" eventfld.byte 0x04 6. " [6] ,Wakeup flag for LLWU_P6" "Disabled,Enabled" eventfld.byte 0x04 5. " [5] ,Wakeup flag for LLWU_P5" "Disabled,Enabled" newline sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") eventfld.byte 0x04 4. " [4] ,Wakeup flag for LLWU_P4" "Disabled,Enabled" eventfld.byte 0x04 3. " [3] ,Wakeup flag for LLWU_P3" "Disabled,Enabled" sif cpuis("MKV31F512VLL12P") newline eventfld.byte 0x04 2. " [2] ,Wakeup flag for LLWU_P2" "Disabled,Enabled" eventfld.byte 0x04 1. " [1] ,Wakeup flag for LLWU_P1" "Disabled,Enabled" endif newline eventfld.byte 0x04 0. " [0] ,Wakeup flag for LLWU_P0" "Disabled,Enabled" endif line.byte 0x05 "F2,LLWU Flag 2 Register" eventfld.byte 0x05 7. " WUF[15] ,Wakeup flag for LLWU_P15" "Disabled,Enabled" eventfld.byte 0x05 6. " [14] ,Wakeup flag for LLWU_P14" "Disabled,Enabled" eventfld.byte 0x05 5. " [13] ,Wakeup flag for LLWU_P13" "Disabled,Enabled" eventfld.byte 0x05 4. " [12] ,Wakeup flag for LLWU_P12" "Disabled,Enabled" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") newline eventfld.byte 0x05 3. " [11] ,Wakeup flag for LLWU_P11" "Disabled,Enabled" endif newline eventfld.byte 0x05 2. " [10] ,Wakeup flag for LLWU_P10" "Disabled,Enabled" eventfld.byte 0x05 1. " [9] ,Wakeup flag for LLWU_P9" "Disabled,Enabled" eventfld.byte 0x05 0. " [8] ,Wakeup flag for LLWU_P8" "Disabled,Enabled" rgroup.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 Register" bitfld.byte 0x00 2. " MWUF[2] ,Wakeup flag for module 2" "Disabled,Enabled" bitfld.byte 0x00 1. " [1] ,Wakeup flag for module 1" "Disabled,Enabled" bitfld.byte 0x00 0. " [0] ,Wakeup flag for module 0" "Disabled,Enabled" newline group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" sif cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" else bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" endif line.byte 0x01 "FILT2,LLWU Pin Filter 2 register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" sif cpuis("MKV31F512VLL12P") bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" else bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12R")&&!cpuis("MKV31F512VLH12R")&&!cpuis("MKV31F512VLL12P") bitfld.word 0x00 7. " ASC[7] ,Connection to the crossbar switch's slave input port 7" "Not connected,Connected" bitfld.word 0x00 6. " [6] ,Connection to the crossbar switch's slave input port 5" "Not connected,Connected" bitfld.word 0x00 5. " [5] ,Connection to the crossbar switch's slave input port 6" "Not connected,Connected" bitfld.word 0x00 4. " [4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected" newline bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.word 0x00 4. " ASC[4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected" bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" newline bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" else bitfld.word 0x00 3. " ASC[3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" endif line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12R")&&!cpuis("MKV31F512VLH12R")&&!cpuis("MKV31F512VLL12P") bitfld.word 0x02 7. " AMC[7] ,Connection to the AXBS master input port 7" "Not connected,Connected" bitfld.word 0x02 6. " [6] ,Connection to the AXBS master input port 6" "Not connected,Connected" bitfld.word 0x02 5. " [5] ,Connection to the AXBS master input port 5" "Not connected,Connected" bitfld.word 0x02 4. " [4] ,Connection to the AXBS master input port 4" "Not connected,Connected" newline bitfld.word 0x02 3. " [3] ,Connection to the AXBS master input port 3" "Not connected,Connected" bitfld.word 0x02 2. " [2] ,Connection to the AXBS master input port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected" else bitfld.word 0x02 2. " AMC[2] ,Connection to the AXBS master input port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected" endif group.long 0x0C++0x07 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin" line.long 0x04 "ISSR,Interrupt Status Register" bitfld.long 0x04 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" rbitfld.long 0x04 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x04 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x04 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x04 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x04 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x04 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clear CPOREQ" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge [entry/exit]" "Not completed/Completed,Completed/Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" width 0x0B tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 9. sif !cpuis("MKV31F128VLH10P")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") group.byte 0x0++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x1++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x2++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x3++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x4++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 7 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 7 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 7 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x5++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 6 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 6 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 6 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x6++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 5 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 5 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 5 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x7++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 4 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 4 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 4 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x8++0x00 line.byte 0x00 "CHCFG11,Channel 11 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 11 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 11 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 11 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x9++0x00 line.byte 0x00 "CHCFG10,Channel 10 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 10 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 10 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 10 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xA++0x00 line.byte 0x00 "CHCFG9,Channel 9 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 9 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 9 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 9 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xB++0x00 line.byte 0x00 "CHCFG8,Channel 8 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 8 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 8 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 8 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xC++0x00 line.byte 0x00 "CHCFG15,Channel 15 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 15 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 15 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 15 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xD++0x00 line.byte 0x00 "CHCFG14,Channel 14 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 14 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 14 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 14 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xE++0x00 line.byte 0x00 "CHCFG13,Channel 13 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 13 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 13 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 13 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0xF++0x00 line.byte 0x00 "CHCFG12,Channel 12 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 12 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 12 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,FTM3 ch.0,FTM3 ch.1,FTM3 ch.2,FTM3 ch.3,FTM3 ch.4,FTM3 ch.5,FTM3 ch.6,FTM3 ch.7,ADC0,ADC1,CMP0,CMP1,,DAC0,DAC1,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 12 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif else group.byte 0x0++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 0 trigger enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 0 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x1++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 1 trigger enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 1 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x2++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 2 trigger enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 2 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif group.byte 0x3++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel 3 trigger enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,UART2 Receive,UART2 Transmit,,,,,,,SPI0 Receive,SPI0 Transmit,SPI1,,I2C0,I2C1,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,FTM0 ch.6,FTM0 ch.7,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,LPUART0 Receive,LPUART0 Transmit,DMA MUX,DMA MUX,DMA MUX,DMA MUX" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel 3 source" ",,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,,,,,,,,,SPI0 Receive,SPI0 Transmit,,,I2C0,,FTM0 ch.0,FTM0 ch.1,FTM0 ch.2,FTM0 ch.3,FTM0 ch.4,FTM0 ch.5,,,FTM1 ch.0,FTM1 ch.1,FTM2 ch.0,FTM2 ch.1,,,,,,,,,ADC0,ADC1,CMP0,CMP1,,DAC0,,,PDB,PortA,PortB,PortC,PortD,PortE,,,,,,,DMA MUX,DMA MUX,DMA MUX,DMA MUX" endif endif width 0x0B tree.end tree "eDMA (Enhanced Direct Memory Access)" base ad:0x40008000 sif cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B else width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 4" group.long 0x80++0x03 line.long 0x00 "TCD4_SADDR,TCD Source Address" group.word (0x80+0x04)++0x03 line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD4_DADDR,TCD Destination Address" group.word (0x80+0x14)++0x01 line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x80+0x18)++0x03 line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x80+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 5" group.long 0xA0++0x03 line.long 0x00 "TCD5_SADDR,TCD Source Address" group.word (0xA0+0x04)++0x03 line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD5_DADDR,TCD Destination Address" group.word (0xA0+0x14)++0x01 line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xA0+0x18)++0x03 line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xA0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 6" group.long 0xC0++0x03 line.long 0x00 "TCD6_SADDR,TCD Source Address" group.word (0xC0+0x04)++0x03 line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD6_DADDR,TCD Destination Address" group.word (0xC0+0x14)++0x01 line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xC0+0x18)++0x03 line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xC0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 7" group.long 0xE0++0x03 line.long 0x00 "TCD7_SADDR,TCD Source Address" group.word (0xE0+0x04)++0x03 line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD7_DADDR,TCD Destination Address" group.word (0xE0+0x14)++0x01 line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xE0+0x18)++0x03 line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xE0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 8" group.long 0x100++0x03 line.long 0x00 "TCD8_SADDR,TCD Source Address" group.word (0x100+0x04)++0x03 line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x100+0x08))&0xC0000000)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x100+0x0C)++0x07 line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD8_DADDR,TCD Destination Address" group.word (0x100+0x14)++0x01 line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x100+0x16))&0x8000)==0x00) group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x100+0x18)++0x03 line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x100+0x1C)++0x01 line.word 0x00 "TCD8_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x100+0x1E))&0x8000)==0x00) group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 9" group.long 0x120++0x03 line.long 0x00 "TCD9_SADDR,TCD Source Address" group.word (0x120+0x04)++0x03 line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x120+0x08))&0xC0000000)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x120+0x0C)++0x07 line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD9_DADDR,TCD Destination Address" group.word (0x120+0x14)++0x01 line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x120+0x16))&0x8000)==0x00) group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x120+0x18)++0x03 line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x120+0x1C)++0x01 line.word 0x00 "TCD9_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x120+0x1E))&0x8000)==0x00) group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 10" group.long 0x140++0x03 line.long 0x00 "TCD10_SADDR,TCD Source Address" group.word (0x140+0x04)++0x03 line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x140+0x08))&0xC0000000)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x140+0x0C)++0x07 line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD10_DADDR,TCD Destination Address" group.word (0x140+0x14)++0x01 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x140+0x16))&0x8000)==0x00) group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x140+0x18)++0x03 line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x140+0x1E))&0x8000)==0x00) group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 11" group.long 0x160++0x03 line.long 0x00 "TCD11_SADDR,TCD Source Address" group.word (0x160+0x04)++0x03 line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x160+0x08))&0xC0000000)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x160+0x0C)++0x07 line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD11_DADDR,TCD Destination Address" group.word (0x160+0x14)++0x01 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x160+0x16))&0x8000)==0x00) group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x160+0x18)++0x03 line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x160+0x1E))&0x8000)==0x00) group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 12" group.long 0x180++0x03 line.long 0x00 "TCD12_SADDR,TCD Source Address" group.word (0x180+0x04)++0x03 line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x180+0x08))&0xC0000000)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x180+0x0C)++0x07 line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD12_DADDR,TCD Destination Address" group.word (0x180+0x14)++0x01 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x180+0x16))&0x8000)==0x00) group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x180+0x18)++0x03 line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x180+0x1E))&0x8000)==0x00) group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 13" group.long 0x1A0++0x03 line.long 0x00 "TCD13_SADDR,TCD Source Address" group.word (0x1A0+0x04)++0x03 line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1A0+0x08))&0xC0000000)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1A0+0x0C)++0x07 line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD13_DADDR,TCD Destination Address" group.word (0x1A0+0x14)++0x01 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1A0+0x16))&0x8000)==0x00) group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1A0+0x18)++0x03 line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00) group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 14" group.long 0x1C0++0x03 line.long 0x00 "TCD14_SADDR,TCD Source Address" group.word (0x1C0+0x04)++0x03 line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1C0+0x08))&0xC0000000)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1C0+0x0C)++0x07 line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD14_DADDR,TCD Destination Address" group.word (0x1C0+0x14)++0x01 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1C0+0x16))&0x8000)==0x00) group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1C0+0x18)++0x03 line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00) group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 15" group.long 0x1E0++0x03 line.long 0x00 "TCD15_SADDR,TCD Source Address" group.word (0x1E0+0x04)++0x03 line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1E0+0x08))&0xC0000000)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1E0+0x0C)++0x07 line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD15_DADDR,TCD Destination Address" group.word (0x1E0+0x14)++0x01 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1E0+0x16))&0x8000)==0x00) group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1E0+0x18)++0x03 line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00) group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B endif tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Clock source select" "LPO_CLK[0],LPO_CLK[1],LPO_CLK[2],LPO_CLK[3]" endif sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,Allows the WDOG functional test mode to be disabled permanently" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested when the watchdog is in the byte test mode" "0,1,2,3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick,Byte" newline bitfld.word 0x00 10. " TESTWDOG ,Puts the watchdog in the functional test mode" "Disabled,Enabled" bitfld.word 0x00 7. " WAITEN ,Enables or disables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables or disables WDOG in stop mode" "Disabled,Enabled" newline bitfld.word 0x00 5. " DBGEN ,Enables or disables WDOG in debug mode" "Disabled,Enabled" bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" newline bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables or disables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F128VLH10P") eventfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" else bitfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" endif line.word 0x04 "TOVALH,Watchdog Time-Out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-Out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. sif (cpuis("MKV10Z*"))||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif elif cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12?")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)!=0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif else if (((per.b(ad:0x40064000+0x01))&0x30)==0x00||((per.b(ad:0x40064000+0x0C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" else bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" endif line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x03))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20-25 mHz,24 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "40-50 mHz,48 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60-75 mHz,72 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80-100 mHz,96 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" endif sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV10Z*") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN0 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN0 ,PLL stop enable" "Disabled,Enabled" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." newline endif newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV0 ,VCO 0 divider" "24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55" else group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV ,VCO divider" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif cpuis("MKV10Z*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" else bitfld.byte 0x00 7. " LOLS0 ,Loss of lock status" "Not locked,Locked" bitfld.byte 0x00 6. " LOCK0 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,Output PLL" bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" endif group.byte 0x08++0x00 sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" eventfld.byte 0x00 0. " LOCS0 ,OSC0 loss of clock status" "Not occurred,Occurred" else line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" rbitfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred" endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32khz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" newline hgroup.byte 0x11++0x00 hide.long 0x00 "C12,MCG Control 12 Register" hgroup.byte 0x12++0x00 hide.long 0x00 "S2,MCG Status 2 Register" hgroup.byte 0x13++0x00 hide.long 0x00 "T3,MCG Test 3 Register" elif (!cpuis("MKV10Z*"))&&(!cpuis("MKV5*"))&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif cpuis("MK65FN2M0CAF18")||cpuis("MK65FN2M0VMF18")||cpuis("MK65FX1M0CAF18")||cpuis("MK65FX1M0VMF18")||cpuis("MK66FN2M0VLQ18")||cpuis("MK66FN2M0VMD18")||cpuis("MK66FX1M0VLQ18")||cpuis("MK66FX1M0VMD18") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Disabled,Enabled" rbitfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" endif else sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" elif !cpuis("MKV10Z*")&&!cpuis("MKV11Z*") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif endif width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40065000 width 5. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x02++0x00 line.byte 0x00 "DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "FMC (Flash Memory Controller)" base ad:0x4001F000 width 8. group.long 0x00++0x07 line.long 0x00 "PFAPR,Flash Access Protection Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MKV31F*")||cpuis("MKV30F*") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" newline bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" else bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" newline bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" endif line.long 0x04 "PFB0CR,Flash Bank 0 Control Register" rbitfld.long 0x04 28.--31. " B0RWSC ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 27. " CLCK_WAY3 ,Cache lock way 3" "Not locked,Locked" newline bitfld.long 0x04 26. " CLCK_WAY2 ,Cache lock way 2" "Not locked,Locked" bitfld.long 0x04 25. " CLCK_WAY1 ,Cache lock way 1" "Not locked,Locked" newline bitfld.long 0x04 24. " CLCK_WAY0 ,Cache lock way 0" "Not locked,Locked" bitfld.long 0x04 23. " CINV_WAY3 ,Cache invalidate way 3" "No effect,Invalidate" newline bitfld.long 0x04 22. " CINV_WAY2 ,Cache invalidate way 2" "No effect,Invalidate" bitfld.long 0x04 21. " CINV_WAY1 ,Cache invalidate way 1" "No effect,Invalidate" newline bitfld.long 0x04 20. " CINV_WAY0 ,Cache invalidate way 0" "No effect,Invalidate" bitfld.long 0x04 19. " S_B_INV ,Invalidate prefetch speculation buffer" "No effect,Invalidate" newline sif cpuis("MKV31F*")||cpuis("MKV30F*") rbitfld.long 0x04 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,?..." else rbitfld.long 0x04 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..." endif newline bitfld.long 0x04 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline bitfld.long 0x04 4. " B0DCE ,Bank 0 data cache enable" "Disabled,Enabled" bitfld.long 0x04 3. " B0ICE ,Bank 0 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled" bitfld.long 0x04 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " B0SEBE ,Bank 0 single entry buffer enable" "Disabled,Enabled" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV30F64VLF10*")&&!cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16*") group.long 0x08++0x03 line.long 0x00 "PFB1CR,Flash Bank 1 Control Register" rbitfld.long 0x00 28.--31. " B1RWSC ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" sif cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12*") rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,?..." else rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..." endif newline bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B1SEBE ,Bank 1 single entry buffer enable" "Disabled,Enabled" endif width 13. tree "Cache Directory Storage Registers" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage Way 0 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage Way 0 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage Way 1 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage Way 1 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage Way 2 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage Way 2 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage Way 3 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage Way 3 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW0S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW0S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW0S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW0S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW0S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW0S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x120++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x124++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x128++0x03 line.long 0x00 "TAGVDW1S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x12C++0x03 line.long 0x00 "TAGVDW1S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x130++0x03 line.long 0x00 "TAGVDW1S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x134++0x03 line.long 0x00 "TAGVDW1S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x138++0x03 line.long 0x00 "TAGVDW1S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x13C++0x03 line.long 0x00 "TAGVDW1S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x140++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x144++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x148++0x03 line.long 0x00 "TAGVDW2S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x14C++0x03 line.long 0x00 "TAGVDW2S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x150++0x03 line.long 0x00 "TAGVDW2S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x154++0x03 line.long 0x00 "TAGVDW2S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x158++0x03 line.long 0x00 "TAGVDW2S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x15C++0x03 line.long 0x00 "TAGVDW2S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x160++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x164++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x168++0x03 line.long 0x00 "TAGVDW3S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x16C++0x03 line.long 0x00 "TAGVDW3S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x170++0x03 line.long 0x00 "TAGVDW3S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x174++0x03 line.long 0x00 "TAGVDW3S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x178++0x03 line.long 0x00 "TAGVDW3S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x17C++0x03 line.long 0x00 "TAGVDW3S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW0S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW0S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW1S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW1S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x120++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x124++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x128++0x03 line.long 0x00 "TAGVDW2S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x12C++0x03 line.long 0x00 "TAGVDW2S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x130++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x134++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x138++0x03 line.long 0x00 "TAGVDW3S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x13C++0x03 line.long 0x00 "TAGVDW3S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif tree.end tree "Cache Data Storage Registers" sif cpuis("MKV31F128VLH10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long (0x0+0x200)++0x0F line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)" group.long (0x10+0x200)++0x0F line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)" group.long (0x20+0x200)++0x0F line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)" group.long (0x30+0x200)++0x0F line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)" group.long (0x40+0x200)++0x0F line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)" group.long (0x50+0x200)++0x0F line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)" group.long (0x60+0x200)++0x0F line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)" group.long (0x70+0x200)++0x0F line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW0S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S4L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW0S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S5L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW0S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S6L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW0S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S7L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW1S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S4L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW1S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S5L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW1S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S6L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW1S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S7L,Cache Data Storage (Lower Word)" group.long 0x280++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x288++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x290++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x298++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x2A0++0x07 line.long 0x00 "DATAW2S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S4L,Cache Data Storage (Lower Word)" group.long 0x2A8++0x07 line.long 0x00 "DATAW2S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S5L,Cache Data Storage (Lower Word)" group.long 0x2B0++0x07 line.long 0x00 "DATAW2S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S6L,Cache Data Storage (Lower Word)" group.long 0x2B8++0x07 line.long 0x00 "DATAW2S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S7L,Cache Data Storage (Lower Word)" group.long 0x2C0++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x2C8++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x2D0++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x2D8++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" group.long 0x2E0++0x07 line.long 0x00 "DATAW3S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S4L,Cache Data Storage (Lower Word)" group.long 0x2E8++0x07 line.long 0x00 "DATAW3S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S5L,Cache Data Storage (Lower Word)" group.long 0x2F0++0x07 line.long 0x00 "DATAW3S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S6L,Cache Data Storage (Lower Word)" group.long 0x2F8++0x07 line.long 0x00 "DATAW3S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S7L,Cache Data Storage (Lower Word)" endif tree.end width 0x0B tree.end tree "FTFA (Flash Memory Module)" base ad:0x40020000 sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rgroup.byte 0x1C++0x03 line.byte 0x00 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Execute-only access control" "Yes,No" rgroup.byte 0x24++0x03 line.byte 0x00 "SACCL3,Supervisor-Only Access Regisster 3" bitfld.byte 0x00 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x01 "SACCL2,Supervisor-Only Access Regisster 2" bitfld.byte 0x01 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x02 "SACCL1,Supervisor-Only Access Regisster 1" bitfld.byte 0x02 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x03 "SACCL0,Supervisor-Only Access Regisster 0" bitfld.byte 0x03 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Supervisor-only access control" "Yes,No" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-Only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-Only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-Only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-Only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-Only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-Only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-Only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-Only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif sif !cpuis("MKV10Z32VLC7*")&&!cpuis("MKV10Z32VFM7*") rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif width 0x0B else width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" newline eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif (cpuis("MKV5*")) newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready" elif (cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block" rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..." newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" else newline rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..." rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif rgroup.byte 0x02++0x00 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" newline bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" sif cpuis("MKV5*") rgroup.byte 0x03++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" sif !cpuis("MKV5*") group.byte 0x10++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x18++0x03 line.byte 0x00 "FPROTH3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTH2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTH1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTH0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV31F*")&&cpuis("MKV30F*") group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" line.byte 0x01 "FDPROT,Data Flash Protection Register" endif newline sif cpuis("MKV31F*")||cpuis("MKV30F*") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif width 0x0B endif tree.end sif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") tree "FLEXBUS (External Bus Interface)" base ad:0x4000C000 width 8. group.long 0x0++0x07 line.long 0x00 "CSAR0,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR0,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x0+0x08))&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0xC++0x07 line.long 0x00 "CSAR1,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR1,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0xC+0x08))&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x18++0x07 line.long 0x00 "CSAR2,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR2,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x18+0x08))&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x24++0x07 line.long 0x00 "CSAR3,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR3,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x24+0x08))&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x30++0x07 line.long 0x00 "CSAR4,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR4,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x30+0x08))&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x3C++0x07 line.long 0x00 "CSAR5,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR5,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x3C+0x08))&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP1 ,FlexBus signal group 1 multiplex control" "FB_ALE,FB_CS1,FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP2 ,FlexBus signal group 2 multiplex control" "FB_CS4,FB_TSIZ0,FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP3 ,FlexBus signal group 3 multiplex control" "FB_CS5,FB_TSIZ1,FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP4 ,FlexBus signal group 4 multiplex control" "FB_TBST,FB_CS2,FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP5 ,FlexBus signal group 5 multiplex control" "FB_TA,FB_CS3,FB_BE_7_0,?..." width 0x0B tree.end endif tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x00) group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" else group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal half-word" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" endif width 0x0B tree.end sif !cpuis("MKV30F*")&&!cpuis("MKV31F128VLH10P") tree "RNGA (Random Number Generator Accelerator)" base ad:0x40029000 width 6. group.long 0x00++0x03 line.long 0x00 "CR,RNGA Control Register" bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled" sif cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 3. " CLRI ,Clear interrupt" "Not cleared,Cleared" else eventfld.long 0x00 3. " CLRI ,Clear interrupt" "Not cleared,Cleared" endif newline bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " HA ,High assurance (Enable notification of security violations)" "Disabled,Enabled" newline bitfld.long 0x00 0. " GO ,Random-data generation and loading enable" "Disabled,Enabled" newline sif cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P") hgroup.long 0x04++0x03 hide.long 0x00 "SR,RNGA Status Register" in else rgroup.long 0x04++0x03 line.long 0x00 "SR,RNGA Status Register" hexmask.long.byte 0x00 16.--23. 1. " OREG_SIZE ,Output register size" hexmask.long.byte 0x00 8.--15. 1. " OREG_LVL ,Output register level" newline bitfld.long 0x00 4. " SLP ,Sleep mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " ERRI ,Error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " ORU ,Output register underflow" "No underflow,Underflow" bitfld.long 0x00 1. " LRS ,Status of the most recent read of the RNGA output register" "Not empty,Empty" newline bitfld.long 0x00 0. " SECV ,Security violation" "Not occurred,Occurred" endif wgroup.long 0x08++0x03 line.long 0x00 "ER,RNGA Entropy Register" sif cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P") hgroup.long 0x0C++0x03 hide.long 0x00 "OR,RNGA Output Register" in else rgroup.long 0x0C++0x03 line.long 0x00 "OR,RNGA Output Register" endif width 0x0B tree.end endif tree.open "ADC (Analog-to-Digital Converter)" tree "ADC 0" base ad:0x4003B000 sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") width 15. sif !cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") if ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x20)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003B000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif if ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x20)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x4003B000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x4003B000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,SE18,DM0,DM1,,,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,SE18,DM0,DM1,SE21,SE22,12-bit DAC0/SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif else if (((per.l(ad:0x4003B000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,,SE10,SE11,SE12,SE13,SE14,,,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,,SE10,SE11,SE12,SE13,SE14,,,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif endif group.long 0x08++0x07 line.long 0x00 "CFG1,Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection DIFF=0/DIFF=1" "8-bit/9-bit,12-bit/13-bit,10-bit/11-bit,16-bit" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,BUSCLK/2,ALTCK,ADACK" else bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,ALTCLK2,ALTCLK,ADACK" endif line.long 0x04 "CFG2,Configuration Register 2" sif !cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "ADCA,ADCB" newline endif bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "RA,Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "CV1,Compare Value Registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" line.long 0x04 "CV2,Compare Value Registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare value" line.long 0x08 "SC2,Status And Control Register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "SC3,Status And Control Register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" newline bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "OFS,Offset Correction Register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "PG,Plus-Side Gain Register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "MG,Minus-Side Gain Register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side gain" line.long 0x1C "CLPD,Plus-Side General Calibration Value Register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CLPS,Plus-Side General Calibration Value Register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CLP4,Plus-Side General Calibration Value Register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "CLP3,Plus-Side General Calibration Value Register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "CLP2,Plus-Side General Calibration Value Register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "CLP1,Plus-Side General Calibration Value Register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "CLP0,Plus-Side General Calibration Value Register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "CLMD,Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B else width 15. if (((per.l(ad:0x4003B000+0x0))&0x20)==0x0) group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x0) group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000))&0x20)==0x0) group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "ADC0_CFG2,ADC Configuration register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "ADC0_RA,ADC data result register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "ADC0_RB,ADC data result register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "ADC0_CV1,Compare value registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value" line.long 0x04 "ADC0_CV2,Compare value registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value" line.long 0x08 "ADC0_SC2,Status and control register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "ADC0_SC3,Status and control register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" sif (cpuis("MKV5*")) newline eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" else newline rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" endif newline bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "ADC0_OFS,ADC offset correction register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "ADC0_PG,ADC plus-side gain register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "ADC0_MG,ADC minus-side gain register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain" line.long 0x1C "ADC0_CLPD,ADC plus-side general calibration value register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ADC0_CLPS,ADC plus-side general calibration value register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ADC0_CLP4,ADC plus-side general calibration value register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "ADC0_CLP3,ADC plus-side general calibration value register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "ADC0_CLP2,ADC plus-side general calibration value register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "ADC0_CLP1,ADC plus-side general calibration value register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "ADC0_CLP0,ADC plus-side general calibration value register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "ADC0_CLMD,ADC minus-side general calibration value register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ADC0_CLMS,ADC minus-side general calibration value register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ADC0_CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "ADC0_CLM3,CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "ADC0_CLM2,ADC minus-side general calibration value register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "ADC0_CLM1,ADC minus-side general calibration value register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "ADC0_CLM0,ADC minus-side general calibration value register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B endif tree.end tree "ADC 1" base ad:0x40027000 sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") width 15. sif !cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") if ((((per.l(ad:0x40027000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x40027000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,,,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x40027000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x40027000+0x0))&0x20)==0x20)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x40027000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x40027000+0x0))&0x20)==0x00)) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif if ((((per.l(ad:0x40027000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x40027000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,,,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif elif ((((per.l(ad:0x40027000+0x0C))&0x10)==0x00)&&(((per.l(ad:0x40027000+0x4))&0x20)==0x20)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif elif ((((per.l(ad:0x40027000+0x0C))&0x10)==0x10)&&(((per.l(ad:0x40027000+0x4))&0x20)==0x00)) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,,,,,SE8,SE9,SE10,SE11,,,,,,,,,,,,,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,,,,,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F128VLH10P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF Output/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" elif cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,SE23,,,Temperature sensor (SE),Bandgap (SE),,VREFH (S.E),VREFL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temperature sensor (diff),Bandgap (diff),,-VREFH (diff),,Disabled" endif endif else if (((per.l(ad:0x40027000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x0++0x03 line.long 0x00 "SC1A,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif if (((per.l(ad:0x40027000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "SE0,SE1,SE2,SE3,SE4,SE5,SE6,SE7,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,,,,,,,,VREFH,Temperature sensor (SE),Bandgap (SE),,,,Disabled" else group.long 0x4++0x03 line.long 0x00 "SC1B,Status And Control Registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,-VREFH (diff),Temperature sensor (diff),Bandgap (diff),,,,Disabled" endif endif group.long 0x08++0x07 line.long 0x00 "CFG1,Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection DIFF=0/DIFF=1" "8-bit/9-bit,12-bit/13-bit,10-bit/11-bit,16-bit" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,BUSCLK/2,ALTCK,ADACK" else bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "BUSCLK,ALTCLK2,ALTCLK,ADACK" endif line.long 0x04 "CFG2,Configuration Register 2" sif !cpuis("MKV10Z64VFM7")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z64VLH7") bitfld.long 0x00 4. " MUXSEL ,ADC mux select" "ADCA,ADCB" newline endif bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "RA,Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "CV1,Compare Value Registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" line.long 0x04 "CV2,Compare Value Registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare value" line.long 0x08 "SC2,Status And Control Register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "SC3,Status And Control Register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" newline bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "OFS,Offset Correction Register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "PG,Plus-Side Gain Register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "MG,Minus-Side Gain Register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side gain" line.long 0x1C "CLPD,Plus-Side General Calibration Value Register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "CLPS,Plus-Side General Calibration Value Register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "CLP4,Plus-Side General Calibration Value Register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "CLP3,Plus-Side General Calibration Value Register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "CLP2,Plus-Side General Calibration Value Register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "CLP1,Plus-Side General Calibration Value Register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "CLP0,Plus-Side General Calibration Value Register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "CLMD,Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,CLM4,Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B else width 15. if (((per.l(ad:0x40027000+0x0))&0x20)==0x0) group.long 0x0++0x03 line.long 0x00 "ADC1_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "ADC1_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x40027000+0x4))&0x20)==0x0) group.long 0x4++0x03 line.long 0x00 "ADC1_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "ADC1_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x40027000))&0x20)==0x0) group.long 0x08++0x03 line.long 0x00 "ADC1_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "ADC1_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "ADC1_CFG2,ADC Configuration register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "ADC1_RA,ADC data result register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "ADC1_RB,ADC data result register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "ADC1_CV1,Compare value registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value" line.long 0x04 "ADC1_CV2,Compare value registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value" line.long 0x08 "ADC1_SC2,Status and control register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "ADC1_SC3,Status and control register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" sif (cpuis("MKV5*")) newline eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" else newline rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" endif newline bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "ADC1_OFS,ADC offset correction register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "ADC1_PG,ADC plus-side gain register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "ADC1_MG,ADC minus-side gain register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain" line.long 0x1C "ADC1_CLPD,ADC plus-side general calibration value register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ADC1_CLPS,ADC plus-side general calibration value register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ADC1_CLP4,ADC plus-side general calibration value register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "ADC1_CLP3,ADC plus-side general calibration value register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "ADC1_CLP2,ADC plus-side general calibration value register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "ADC1_CLP1,ADC plus-side general calibration value register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "ADC1_CLP0,ADC plus-side general calibration value register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "ADC1_CLMD,ADC minus-side general calibration value register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ADC1_CLMS,ADC minus-side general calibration value register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ADC1_CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "ADC1_CLM3,CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "ADC1_CLM2,ADC minus-side general calibration value register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "ADC1_CLM1,ADC minus-side general calibration value register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "ADC1_CLM0,ADC minus-side general calibration value register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B endif tree.end tree.end tree.open "CMP (Comparator)" tree "CMP 0" base ad:0x40073000 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP 1" base ad:0x40073008 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree.end sif cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLL12")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") tree "DAC (Digital-to-Analog Converter)" base ad:0x4003F000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC0_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC0_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end elif cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12R") tree.open "DAC (Digital-to-Analog Converter)" tree "Module 0" base ad:0x4003F000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC0_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC0_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "Module 1" base ad:0x40028000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC1_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC1_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAC1_DAT2L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAC1_DAT3L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAC1_DAT4L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAC1_DAT5L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAC1_DAT6L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAC1_DAT7L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAC1_DAT8L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAC1_DAT9L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAC1_DAT10L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAC1_DAT11L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAC1_DAT12L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAC1_DAT13L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAC1_DAT14L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAC1_DAT15L,DAC Data Low Register" line.byte 0x01 "DAC1_DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC1_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC1_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x40028000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC1_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC1_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC1_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC1_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC1_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC1_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC1_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC1_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC1_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC1_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.end endif tree "VREF1 (Voltage Reference)" base ad:0x40074000 width 10. group.byte 0x00++0x01 line.byte 0x00 "VREF_TRM,VREF Trim Register" bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max" line.byte 0x01 "SC,VREF Status And Control Register" bitfld.byte 0x01 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled" bitfld.byte 0x01 6. " REGEN ,Internal 1.75V regulator enable" "Disabled,Enabled" bitfld.byte 0x01 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled" newline rbitfld.byte 0x01 2. " VREFST ,Internal voltage reference stable" "Disabled|not stable,Stable" bitfld.byte 0x01 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High-power,Low-power,?..." width 0x0B tree.end tree "PDB (Programmable Delay Block)" base ad:0x40036000 sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB elif cpuis("MKV31F128VLH10P") width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB elif cpuis("MKV31F256VLH12*") width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x48++0x07 line.long 0x00 "CH1_DLY2,Channel 1 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH1_DLY3,Channel 1 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB else width 11. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,PDB reached MOD,Trigger detected,Trigger detected/PDB mod" bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 16. " SWTRIG,Software trigger" "No effect,Trigger" else bitfld.long 0x00 16. " SWTRIG,Software trigger" "Not triggered,Triggered" endif newline bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler factor" "/1*MULT,/2*MULT,/4*MULT,/8*MULT,/16*MULT,/32*MULT,/64*MULT,/128*MULT" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "PDB_EXTRG0,CMP0,CMP1,PDB_EXTRG1,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR,Software trigger" elif cpuis("MKV10Z*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV30F*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" elif (cpuis("MKV5*")) bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,XBARA_OUT38,,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV5*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV30F*")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" else group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*") else bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" newline endif bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0x0B endif tree.end tree.open "FTM (FlexTimer Module)" tree "Module 0" base ad:0x40038000 sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P") width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register" in newline else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM0_CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM0_MOD,FTM0 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM0_CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B else width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register" in newline else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM0_CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM0_MOD,FTM0 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM0_CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B endif tree.end tree "Module 1" base ad:0x40039000 sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register" in newline else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM1_CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM1_MOD,FTM1 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM1_CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B else width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register" in newline else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM1_CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM1_MOD,FTM1 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM1 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM1 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM1_C2SC,FTM1 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C2V,FTM1 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM1_C2SC,FTM1 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C2V,FTM1 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM1 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM1 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM1_C3SC,FTM1 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C3V,FTM1 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM1_C3SC,FTM1 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C3V,FTM1 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM1 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM1 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM1_C4SC,FTM1 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C4V,FTM1 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM1_C4SC,FTM1 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C4V,FTM1 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM1 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM1 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM1_C5SC,FTM1 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C5V,FTM1 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM1_C5SC,FTM1 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C5V,FTM1 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM1 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM1 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM1_C6SC,FTM1 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C6V,FTM1 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM1_C6SC,FTM1 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C6V,FTM1 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM1 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM1 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM1_C7SC,FTM1 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C7V,FTM1 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM1_C7SC,FTM1 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C7V,FTM1 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM1_CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B endif tree.end tree "Module 2" base ad:0x4003A000 sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register" in newline else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM2_CNT,FTM2 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM2_MOD,FTM2 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM2_CONF,FTM2 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B else width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register" in newline else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM2_CNT,FTM2 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM2_MOD,FTM2 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM2 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM2 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C2V,FTM2 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM2_C2SC,FTM2 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C2V,FTM2 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM2 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM2 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C3V,FTM2 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM2_C3SC,FTM2 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C3V,FTM2 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM2 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM2 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C4V,FTM2 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM2_C4SC,FTM2 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C4V,FTM2 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM2 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM2 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C5V,FTM2 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM2_C5SC,FTM2 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C5V,FTM2 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM2 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM2 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM2_C6SC,FTM2 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C6V,FTM2 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM2_C6SC,FTM2 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C6V,FTM2 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM2 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM2 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM2_C7SC,FTM2 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C7V,FTM2 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM2_C7SC,FTM2 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C7V,FTM2 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM2_CONF,FTM2 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B endif tree.end sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12*") tree "Module 3" base ad:0x40036000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM3_SC,FTM3 Status And Control Register" in newline else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM3_CNT,FTM3 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM3_MOD,FTM3 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM3_CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM3_SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM3_OUTINIT,FTM3 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM3_OUTMASK,FTM3 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM3_EXTTRIG,FTM3 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM3_FMS,FTM3 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM3_FILTER,FTM3 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM3_CONF,FTM3 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM3_SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM3_INVCTRL,FTM3 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM3_SWOCTRL,FTM3 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM3_PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end endif tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x40037000 width 9. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" sif cpuis("MKV5*") rgroup.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" endif group.long 0x100++0x03 "PIT0 Registers" line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CVAL0,PIT0 Current Timer Value Register" group.long (0x100+0x08)++0x07 line.long 0x00 "TCTRL0,PIT0 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG0,PIT0 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x110++0x03 "PIT1 Registers" line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register" rgroup.long (0x110+0x04)++0x03 line.long 0x00 "CVAL1,PIT1 Current Timer Value Register" group.long (0x110+0x08)++0x07 line.long 0x00 "TCTRL1,PIT1 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG1,PIT1 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x120++0x03 "PIT2 Registers" line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register" rgroup.long (0x120+0x04)++0x03 line.long 0x00 "CVAL2,PIT2 Current Timer Value Register" group.long (0x120+0x08)++0x07 line.long 0x00 "TCTRL2,PIT2 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG2,PIT2 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x130++0x03 "PIT3 Registers" line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register" rgroup.long (0x130+0x04)++0x03 line.long 0x00 "CVAL3,PIT3 Current Timer Value Register" group.long (0x130+0x08)++0x07 line.long 0x00 "TCTRL3,PIT3 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG3,PIT3 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" width 0x0B tree.end tree "LPTMR (Low-Power Timer)" base ad:0x40040000 width 5. if (((per.l(ad:0x40040000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x40040000))&0x01)==0x00) if (((per.l(ad:0x40040000))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif else if (((per.l(ad:0x40040000))&0x02)==0x00) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif endif if (((per.l(ad:0x40040000))&0x01)==0x00)||(((per.l(ad:0x40040000))&0x81)==0x81) group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif else rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif sif cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end sif cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") tree.open "SPI (Serial Peripheral Interface)" tree "Module 0" base ad:0x4002C000 width 13. if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline rbitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline rbitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline bitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" endif group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4002C000)+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EQQ ,End of queue" "Not last,Last" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not cleared,Cleared" newline sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "Module 1" base ad:0x4002D000 width 13. if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline rbitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline rbitfld.long 0x00 17. " PCSIS[1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 19. " PCSIS[3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline bitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 17. " PCSIS[1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 19. " PCSIS[3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" endif group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif if (((per.l(ad:0x4002D000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4002D000)+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x4002D000))&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EQQ ,End of queue" "Not last,Last" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not cleared,Cleared" newline sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 17. " PCS[1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 19. " PCS[3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" if (((per.l(ad:0x4002D000))&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002D000))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002D000))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002D000))&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.end elif cpuis("MKV31F*") tree.open "SPI (Serial Peripheral Interface)" tree "Module 0" base ad:0x4002C000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpu()=="MKV30F128VFM10"||cpu()=="MKV30F64VFM10"||cpuis("MKW2?D*")) bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "Module 1" base ad:0x4002D000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.end elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") tree "SPI (Serial Peripheral Interface)" base ad:0x4002C000 width 13. if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline rbitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline rbitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline bitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" endif group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4002C000)+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EQQ ,End of queue" "Not last,Last" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not cleared,Cleared" newline sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end else tree "SPI (Serial Peripheral Interface)" base ad:0x4002C000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpu()=="MKV30F128VFM10"||cpu()=="MKV30F64VFM10"||cpuis("MKW2?D*")) bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end endif tree.open "I2C (Inter-Integrated Circuit)" tree "Module 0" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" newline in newline if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" width 0x0B tree.end sif !cpuis("MKV30F*") tree "Module 1" base ad:0x40067000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C1 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C1 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C1 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C1 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C1 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C1 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C1 Data I/O Register" newline in newline if ((per.b(ad:0x40067000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C1 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC1 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C1 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C1 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C1 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C1 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C1 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C1 SCL Low Timeout Low Register" width 0x0B tree.end endif tree.end tree.open "UART (Universal Asynchronous Receiver Transmitter)" tree "Module 0" base ad:0x4006A000 width 17. tree "UART 0 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART0_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" endif newline bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART0_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode" else bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif newline bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART0_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" newline bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif (cpuis("MKW01Z128*")) group.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART0_S1,UART Status Register 1" newline in newline else rgroup.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif group.byte 0x05++0x01 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" newline bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" newline bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART0_C3,UART Control Register 3" sif (cpuis("MKW01Z128*")) bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX" bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX" else rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" endif newline bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART0_D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "UART0_MA1,UART Match Address Registers 1" line.byte 0x01 "UART0_MA2,UART Match Address Registers 2" line.byte 0x02 "UART0_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) bitfld.byte 0x02 0.--4. " OSR ,Over sampling ratio" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" endif line.byte 0x03 "UART0_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes" endif sif (!cpuis("MKW01Z128*")) rgroup.byte 0x0C++0x00 line.byte 0x00 "UART0_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART0_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted" newline bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART0_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif tree.end sif (!cpuis("MKW01Z128*")) tree "UART 0 FIFO Registers" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006A000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006A000+0x12))&0xC0)==0xC0) group.byte 0x10++0x02 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x02 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x02 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" newline bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" newline eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006A000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" rgroup.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count" rgroup.byte 0x16++0x00 line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count" tree.end endif width 19. sif (cpuis("MKW2?D*")) tree "ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART0_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" newline bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02) group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte 0x1C++0x02 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02) group.byte 0x1F++0x00 line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" else hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" endif tree.end else sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*"))) tree "UART 0 ISO7816 Registers" if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00) group.byte 0x18++0x02 line.byte 0x00 "UART0_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" newline bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" else rgroup.byte 0x18++0x02 line.byte 0x00 "UART0_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" newline bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" endif group.byte 0x19++0x01 line.byte 0x00 "UART0_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x00 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")) bitfld.byte 0x00 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" else bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" endif newline bitfld.byte 0x00 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x01 "UART0_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x01 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x01 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")) eventfld.byte 0x01 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" else eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" endif newline eventfld.byte 0x01 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D256VHA5R")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")) if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register" endif else if ((per.b(ad:0x4006A000+0x18)&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00) group.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" else rgroup.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" endif else group.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" endif sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") if ((((per.b(ad:0x4006A000+0x18)&0x02)==0x00))&&(((per.b(ad:0x4006A000+0x18)&0x08)==0x08))) if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00) group.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif ((per.b(ad:0x4006A000+0x18)&0x02)==0x00) if (((per.b(ad:0x4006A000+0x18))&0x01)==0x00) group.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else hgroup.byte 0x1E++0x00 hide.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" endif else group.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02) group.byte 0x1F++0x00 line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" else hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" endif width 19. sif ((cpu()!="MKW21D256VHA5")&&(cpu()!="MKW21D512VHA5")&&(cpu()!="MKW22D512VHA5")&&(cpu()!="MKW24D512VHA5")&&cpu()!="MKW21D256VHA5R") if ((per.b(ad:0x4006A000+0x18)&0x02)==0x02) if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00) hgroup.byte 0x3A++0x01 hide.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" hide.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" group.byte 0x3C++0x03 line.byte 0x00 "UART0_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART0_WP7816B_T1,UART 7816 Wait Parameter Register B" line.byte 0x02 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.byte 0x3A++0x01 hide.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" hide.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" rgroup.byte 0x3C++0x03 line.byte 0x00 "UART0_WP7816A_T1,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART0_WP7816B_T1,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00) group.byte 0x3A++0x03 line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART0_WP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x03 "UART0_WP7816B_T0,UART 7816 ATR Duration Timer Register B" hgroup.byte 0x3E++0x01 hide.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register" hide.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" else rgroup.byte 0x3A++0x03 line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART0_WP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x03 "UART0_WP7816B_T0,UART 7816 ATR Duration Timer Register B" hgroup.byte 0x3E++0x01 hide.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait And Guard Parameter Register" hide.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" endif endif endif tree.end endif endif width 0x0B tree.end tree "Module 1" base ad:0x4006B000 width 17. tree "UART 1 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART1_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" endif newline bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART1_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode" else bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif newline bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART1_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" newline bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif (cpuis("MKW01Z128*")) group.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART1_S1,UART Status Register 1" newline in newline else rgroup.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif group.byte 0x05++0x01 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" newline bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" newline bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART1_C3,UART Control Register 3" sif (cpuis("MKW01Z128*")) bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX" bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX" else rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" endif newline bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART1_D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "UART1_MA1,UART Match Address Registers 1" line.byte 0x01 "UART1_MA2,UART Match Address Registers 2" line.byte 0x02 "UART1_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) else bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" endif line.byte 0x03 "UART1_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes" endif sif (!cpuis("MKW01Z128*")) rgroup.byte 0x0C++0x00 line.byte 0x00 "UART1_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART1_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted" newline bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART1_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif tree.end sif (!cpuis("MKW01Z128*")) tree "UART 1 FIFO Registers" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006B000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006B000+0x12))&0xC0)==0xC0) group.byte 0x10++0x02 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x02 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x02 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" newline bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" newline eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006B000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" rgroup.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count" rgroup.byte 0x16++0x00 line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count" tree.end endif width 19. sif (cpuis("MKW2?D*")) tree "ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" newline bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006B000+0x18)&0x02)==0x02) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.b(ad:0x4006B000+0x18)&0x02)==0x02) group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif tree.end else sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*"))) endif endif width 0x0B tree.end sif !cpuis("MKV30F*") tree "Module 2" base ad:0x4006C000 width 17. tree "UART 2 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART2_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" endif newline bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART2_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) bitfld.byte 0x02 6. " DOZEEN ,Doze enable" "Enabled in wait mode,Disabled in wait mode" else bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif newline bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. Loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.byte 0x02 2. " ILT ,Idle line type select" "After started bit,After stopped bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART2_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" newline bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif (cpuis("MKW01Z128*")) group.byte 0x04++0x00 line.byte 0x00 "UART2_S1,UART Status Register 1" rbitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" rbitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" rbitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline eventfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" eventfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" eventfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline eventfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" eventfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART2_S1,UART Status Register 1" newline in newline else rgroup.byte 0x04++0x00 line.byte 0x00 "UART2_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" newline bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif group.byte 0x05++0x01 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" newline bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" newline bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (Detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART2_C3,UART Control Register 3" sif (cpuis("MKW01Z128*")) bitfld.byte 0x01 7. " R8T9 ,Received bit 8/transmit bit 9" "No RX/TX,RX/TX" bitfld.byte 0x01 6. " R9T8 ,Transmit bit 8" "No TX/RX,TX/RX" else rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" endif newline bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in Single-Wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART2_D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "UART2_MA1,UART Match Address Registers 1" line.byte 0x01 "UART2_MA2,UART Match Address Registers 2" line.byte 0x02 "UART2_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" newline sif (cpuis("MKW01Z128*")) else bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" endif line.byte 0x03 "UART2_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" sif (cpuis("MKW01Z128*")) newline bitfld.byte 0x03 1. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.byte 0x03 0. " RESYNCDIS ,Resynchronization disable" "No,Yes" endif sif (!cpuis("MKW01Z128*")) rgroup.byte 0x0C++0x00 line.byte 0x00 "UART2_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART2_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg Fifo>=rwfifo(Rxwater)/num of char in RCV data reg Fifo<=rwfifo(Rxwater))" "No effect,Deasserted/asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (Char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/deasserted" newline bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART2_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif tree.end sif (!cpuis("MKW01Z128*")) tree "UART 2 FIFO Registers" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006C000+0x03))&0x0C)==0x00)&&(((per.b(ad:0x4006C000+0x12))&0xC0)==0xC0) group.byte 0x10++0x02 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x02 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x02 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." newline bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART2_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" newline bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART2_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" newline eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") if (((per.b(ad:0x4006C000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" rgroup.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count" rgroup.byte 0x16++0x00 line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count" tree.end endif width 19. sif (cpuis("MKW2?D*")) tree "ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART2_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" newline bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART2_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART2_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006C000+0x18)&0x02)==0x02) group.byte 0x1B++0x00 line.byte 0x00 "UART2_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART2_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte 0x1C++0x02 line.byte 0x00 "UART2_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART2_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART2_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.b(ad:0x4006C000+0x18)&0x02)==0x02) group.byte 0x1F++0x00 line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register" else hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register" endif tree.end else sif ((cpu()!="MKV30F128VLH10")&&(cpu()!="MKV30F128VLF10")&&(cpu()!="MKV30F128VFM10")&&(cpu()!="MKV30F64VLH10")&&(cpu()!="MKV30F64VLF10")&&(cpu()!="MKV30F64VFM10")&&(!cpuis("MKW01Z128*"))) endif endif width 0x0B tree.end endif tree.end sif !cpuis("MKV30F*") tree "LPUART (Low Power Universal Asynchronous Receiver Transmitter)" base ad:0x4002A000 width 11. if (((per.l(ad:0x4002A000+0x08))&0xC0000)==0x00000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif (((per.l(ad:0x4002A000+0x08))&0x40000)==0x00000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8bit/9bit,10bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif if (((per.l(ad:0x4002A000))&0x20002000)==0x20002000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART0 Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13bit,16bit" newline bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13bit,15bit" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected" newline eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x00 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((((per.l(ad:0x4002A000+0x08))&0x10)==0x10)&&(((per.l(ad:0x4002A000))&0x2000)==0x2000))||(((per.l(ad:0x4002A000))&0x20002000)==0x20000000)) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART0 Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12bit,15bit" newline bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12bit,14bit" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected" newline eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x00 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((((per.l(ad:0x4002A000+0x08))&0x10)==0x10)&&(((per.l(ad:0x4002A000))&0x2000)==0x0000))||(((((per.l(ad:0x4002A000+0x08))&0x10)==0x00)&&(((per.l(ad:0x4002A000))&0x2000)==0x2000)))) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART0 Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11bit,14bit" newline bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11bit,12bit" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected" newline eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x00 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART0 Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10bit,13bit" newline bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10bit,11bit" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "Not detected,Detected" newline eventfld.long 0x00 16. " PF ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x00 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x4002A000))&0x20000000)==0x20000000) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" elif ((((per.l(ad:0x4002A000))&0x20000000)==0x00000000)&&(((per.l(ad:0x4002A000+0x08))&0x10)==0x10)) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1char,2char,4char,8char,16char,32char,64char,128char" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Enabled,Disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8bit,9bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART0 Data Register" in newline group.long 0x10++0x07 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 0x01 " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 0x01 " MA1 ,Match address 1" line.long 0x04 "MODIR,LPUART0 Modem IrDA Register" bitfld.long 0x04 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x04 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x04 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x04 4. " TXCTSC ,Transmit CTS configuration" "Each character,When idle" bitfld.long 0x04 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x04 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x04 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x04 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" width 0x0B tree.end endif tree.open "GPIO (General Purpose Input/Output)" tree "GPIOA" base ad:0x400FF000 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOA_PDOR_set/clr,Port A Data Output Register" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" newline setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO15 ,Port Data Output 15" "Logic 0,Logic 1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO14 ,Port Data Output 14" "Logic 0,Logic 1" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO13 ,Port Data Output 13" "Logic 0,Logic 1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO12 ,Port Data Output 12" "Logic 0,Logic 1" sif !cpuis("MKV31F512VLL12P") setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1" endif newline setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P")) setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO13 ,Port Data Output 13" "Logic 0,Logic 1" newline setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO12 ,Port Data Output 12" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1" newline endif sif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P") setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" endif newline width 12. wgroup.long 0x0C++0x03 line.long 0x00 "GPIOA_PTOR,Port A Toggle Output Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" newline bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" bitfld.long 0x00 15. " PTTO15 ,Port Toggle Output 15" "No change,Inverse logic" bitfld.long 0x00 14. " PTTO14 ,Port Toggle Output 14" "No change,Inverse logic" newline bitfld.long 0x00 13. " PTTO13 ,Port Toggle Output 13" "No change,Inverse logic" bitfld.long 0x00 12. " PTTO12 ,Port Toggle Output 12" "No change,Inverse logic" sif !cpuis("MKV31F512VLL12P") bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No change,Inverse logic" endif newline bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No change,Inverse logic" bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" newline bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P")) bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" bitfld.long 0x00 13. " PTTO13 ,Port Toggle Output 13" "No change,Inverse logic" newline bitfld.long 0x00 12. " PTTO12 ,Port Toggle Output 12" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No change,Inverse logic" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" endif sif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" newline bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_PDIR,Port A Data Input Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" newline bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" bitfld.long 0x00 15. " PDI15 ,Port Data Input 15" "Logic 0,Logic 1" bitfld.long 0x00 14. " PDI14 ,Port Data Input 14" "Logic 0,Logic 1" newline bitfld.long 0x00 13. " PDI13 ,Port Data Input 13" "Logic 0,Logic 1" bitfld.long 0x00 12. " PDI12 ,Port Data Input 12" "Logic 0,Logic 1" sif !cpuis("MKV31F512VLL12P") bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1" endif newline bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1" bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" newline bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P")) bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" bitfld.long 0x00 13. " PDI13 ,Port Data Input 13" "Logic 0,Logic 1" newline bitfld.long 0x00 12. " PDI12 ,Port Data Input 12" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" endif sif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" newline bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOA_PDDR,Port A Data Direction Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" newline bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" bitfld.long 0x00 15. " PDD15 ,Port Data Direction 15" "Input,Output" bitfld.long 0x00 14. " PDD14 ,Port Data Direction 14" "Input,Output" newline bitfld.long 0x00 13. " PDD13 ,Port Data Direction 13" "Input,Output" bitfld.long 0x00 12. " PDD12 ,Port Data Direction 12" "Input,Output" sif !cpuis("MKV31F512VLL12P") bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output" endif newline bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output" bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" newline bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P")) bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" bitfld.long 0x00 13. " PDD13 ,Port Data Direction 13" "Input,Output" newline bitfld.long 0x00 12. " PDD12 ,Port Data Direction 12" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" endif sif cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" newline bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" endif width 0x0B tree.end tree "GPIOB" base ad:0x400FF040 width 20. sif cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") group.long 0x00++0x03 line.long 0x00 "GPIOB_PDOR_set/clr,Port B Data Output Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO23 ,Port Data Output 23" "Logic 0,Logic 1" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO22 ,Port Data Output 22" "Logic 0,Logic 1" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO21 ,Port Data Output 21" "Logic 0,Logic 1" newline setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO20 ,Port Data Output 20" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO11 ,Port Data Output 11" "Logic 0,Logic 1" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO10 ,Port Data Output 10" "Logic 0,Logic 1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO9 ,Port Data Output 9" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12?")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")) sif !cpuis("MKV30F64VLF10")&&!cpuis("MKV30F128VLF10")&&!cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" newline endif sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" endif newline width 12. wgroup.long 0x0C++0x03 line.long 0x00 "GPIOB_PTOR,Port B Toggle Output Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 23. " PTTO23 ,Port Toggle Output 23" "No change,Inverse logic" bitfld.long 0x00 22. " PTTO22 ,Port Toggle Output 22" "No change,Inverse logic" bitfld.long 0x00 21. " PTTO21 ,Port Toggle Output 21" "No change,Inverse logic" newline bitfld.long 0x00 20. " PTTO20 ,Port Toggle Output 20" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" newline bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" bitfld.long 0x00 11. " PTTO11 ,Port Toggle Output 11" "No change,Inverse logic" newline bitfld.long 0x00 10. " PTTO10 ,Port Toggle Output 10" "No change,Inverse logic" bitfld.long 0x00 9. " PTTO9 ,Port Toggle Output 9" "No change,Inverse logic" bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" newline bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12?")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")) sif !cpuis("MKV30F64VLF10")&&!cpuis("MKV30F128VLF10")&&!cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" newline endif sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" newline bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" newline endif bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_PDIR,Port B Data Input Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 23. " PDI23 ,Port Data Input 23" "Logic 0,Logic 1" bitfld.long 0x00 22. " PDI22 ,Port Data Input 22" "Logic 0,Logic 1" bitfld.long 0x00 21. " PDI21 ,Port Data Input 21" "Logic 0,Logic 1" newline bitfld.long 0x00 20. " PDI20 ,Port Data Input 20" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" newline bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" bitfld.long 0x00 11. " PDI11 ,Port Data Input 11" "Logic 0,Logic 1" newline bitfld.long 0x00 10. " PDI10 ,Port Data Input 10" "Logic 0,Logic 1" bitfld.long 0x00 9. " PDI9 ,Port Data Input 9" "Logic 0,Logic 1" bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" newline bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12?")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")) sif !cpuis("MKV30F64VLF10")&&!cpuis("MKV30F128VLF10")&&!cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" newline endif sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" newline bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" newline endif bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOB_PDDR,Port B Data Direction Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLL12P")) bitfld.long 0x00 23. " PDD23 ,Port Data Direction 23" "Input,Output" bitfld.long 0x00 22. " PDD22 ,Port Data Direction 22" "Input,Output" bitfld.long 0x00 21. " PDD21 ,Port Data Direction 21" "Input,Output" newline bitfld.long 0x00 20. " PDD20 ,Port Data Direction 20" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" newline bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" bitfld.long 0x00 11. " PDD11 ,Port Data Direction 11" "Input,Output" newline bitfld.long 0x00 10. " PDD10 ,Port Data Direction 10" "Input,Output" bitfld.long 0x00 9. " PDD9 ,Port Data Direction 9" "Input,Output" bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" newline bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10")||cpuis("MKV31F256VLH12?")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")) sif !cpuis("MKV30F64VLF10")&&!cpuis("MKV30F128VLF10")&&!cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R") bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" newline endif sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" newline bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" newline endif bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" endif endif width 0x0B tree.end tree "GPIOC" base ad:0x400FF080 width 20. sif cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F64VLF10R")||cpuis("MKV30F128VLF10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VFM10") group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_set/clr,Port C Data Output Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port data output 18" "Logic 0,Logic 1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port data output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port data output 16" "Logic 0,Logic 1" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO15 ,Port data output 15" "Logic 0,Logic 1" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO14 ,Port data output 14" "Logic 0,Logic 1" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO13 ,Port data output 13" "Logic 0,Logic 1" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO12 ,Port data output 12" "Logic 0,Logic 1" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO11 ,Port data output 11" "Logic 0,Logic 1" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO10 ,Port data output 10" "Logic 0,Logic 1" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO9 ,Port data output 9" "Logic 0,Logic 1" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO8 ,Port data output 8" "Logic 0,Logic 1" newline endif setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" newline sif !cpuis("MKV30F128VFM10")&&!cpuis("MKV30F64VFM10") setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif newline width 12. wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port C Toggle Output Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 18. " PTTO18 ,Port toggle output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port toggle output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port toggle output 16" "No change,Inverse logic" newline bitfld.long 0x00 15. " PTTO15 ,Port toggle output 15" "No change,Inverse logic" bitfld.long 0x00 14. " PTTO14 ,Port toggle output 14" "No change,Inverse logic" bitfld.long 0x00 13. " PTTO13 ,Port toggle output 13" "No change,Inverse logic" bitfld.long 0x00 12. " PTTO12 ,Port toggle output 12" "No change,Inverse logic" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 11. " PTTO11 ,Port toggle output 11" "No change,Inverse logic" bitfld.long 0x00 10. " PTTO10 ,Port toggle output 10" "No change,Inverse logic" bitfld.long 0x00 9. " PTTO9 ,Port toggle output 9" "No change,Inverse logic" bitfld.long 0x00 8. " PTTO8 ,Port toggle output 8" "No change,Inverse logic" newline endif bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" newline sif !cpuis("MKV30F128VFM10")&&!cpuis("MKV30F64VFM10") bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port C Data Input Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 18. " PDI18 ,Port data input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port data input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port data input 16" "Logic 0,Logic 1" newline bitfld.long 0x00 15. " PDI15 ,Port data input 15" "Logic 0,Logic 1" bitfld.long 0x00 14. " PDI14 ,Port data input 14" "Logic 0,Logic 1" bitfld.long 0x00 13. " PDI13 ,Port data input 13" "Logic 0,Logic 1" bitfld.long 0x00 12. " PDI12 ,Port data input 12" "Logic 0,Logic 1" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 11. " PDI11 ,Port data input 11" "Logic 0,Logic 1" bitfld.long 0x00 10. " PDI10 ,Port data input 10" "Logic 0,Logic 1" bitfld.long 0x00 9. " PDI9 ,Port data input 9" "Logic 0,Logic 1" bitfld.long 0x00 8. " PDI8 ,Port data input 8" "Logic 0,Logic 1" newline endif bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" newline sif !cpuis("MKV30F128VFM10")&&!cpuis("MKV30F64VFM10") bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port C Data Direction Register" sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10") bitfld.long 0x00 18. " PDD18 ,Port data direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port data direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port data direction 16" "Input,Output" newline bitfld.long 0x00 15. " PDD15 ,Port data direction 15" "Input,Output" bitfld.long 0x00 14. " PDD14 ,Port data direction 14" "Input,Output" bitfld.long 0x00 13. " PDD13 ,Port data direction 13" "Input,Output" bitfld.long 0x00 12. " PDD12 ,Port data direction 12" "Input,Output" newline endif sif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 11. " PDD11 ,Port data direction 11" "Input,Output" bitfld.long 0x00 10. " PDD10 ,Port data direction 10" "Input,Output" bitfld.long 0x00 9. " PDD9 ,Port data direction 9" "Input,Output" bitfld.long 0x00 8. " PDD8 ,Port data direction 8" "Input,Output" newline endif bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" newline sif !cpuis("MKV30F128VFM10")&&!cpuis("MKV30F64VFM10") bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif endif width 0x0B tree.end tree "GPIOD" base ad:0x400FF0C0 width 20. group.long 0x00++0x03 line.long 0x00 "GPIOD_PDOR_set/clr,Port D Data Output Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO7 ,Port data output 7" "Logic 0,Logic 1" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port data output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port data output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port data output 4" "Logic 0,Logic 1" newline sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port data output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port data output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port data output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port data output 0" "Logic 0,Logic 1" endif newline width 12. wgroup.long 0x0C++0x03 line.long 0x00 "GPIOD_PTOR,Port D Toggle Output Register" bitfld.long 0x00 7. " PTTO7 ,Port toggle output 7" "No change,Inverse logic" bitfld.long 0x00 6. " PTTO6 ,Port toggle output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port toggle output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port toggle output 4" "No change,Inverse logic" newline sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 3. " PTTO3 ,Port toggle output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port toggle output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port toggle output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port toggle output 0" "No change,Inverse logic" endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_PDIR,Port D Data Input Register" bitfld.long 0x00 7. " PDI7 ,Port data input 7" "Logic 0,Logic 1" bitfld.long 0x00 6. " PDI6 ,Port data input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port data input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port data input 4" "Logic 0,Logic 1" newline sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 3. " PDI3 ,Port data input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port data input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port data input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port data input 0" "Logic 0,Logic 1" endif group.long 0x14++0x03 line.long 0x00 "GPIOD_PDDR,Port D Data Direction Register" bitfld.long 0x00 7. " PDD7 ,Port data direction 7" "Input,Output" bitfld.long 0x00 6. " PDD6 ,Port data direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port data direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port data direction 4" "Input,Output" newline sif !cpuis("MKV30F64VFM10")&&!cpuis("MKV30F128VFM10") bitfld.long 0x00 3. " PDD3 ,Port data direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port data direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port data direction 1" "Input,Output" bitfld.long 0x00 0. " PDD0 ,Port data direction 0" "Input,Output" endif width 0x0B tree.end tree "GPIOE" base ad:0x400FF100 width 20. sif cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.long 0x00++0x03 line.long 0x00 "GPIOE_PDOR_set/clr,Port E Data Output Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")) setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO26 ,Port Data Output 26" "Logic 0,Logic 1" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO25 ,Port Data Output 25" "Logic 0,Logic 1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO24 ,Port Data Output 24" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" newline setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port Data Output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F64VFM10")) setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO25 ,Port Data Output 25" "Logic 0,Logic 1" newline setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO24 ,Port Data Output 24" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" sif cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") sif cpuis("MKV31F512VLL12P") setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO26 ,Port Data Output 26" "Logic 0,Logic 1" endif newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO25 ,Port Data Output 25" "Logic 0,Logic 1" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO24 ,Port Data Output 24" "Logic 0,Logic 1" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO19 ,Port Data Output 19" "Logic 0,Logic 1" newline setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO18 ,Port Data Output 18" "Logic 0,Logic 1" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO17 ,Port Data Output 17" "Logic 0,Logic 1" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO16 ,Port Data Output 16" "Logic 0,Logic 1" sif cpuis("MKV31F512VLL12P") newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO6 ,Port Data Output 6" "Logic 0,Logic 1" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO5 ,Port Data Output 5" "Logic 0,Logic 1" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO4 ,Port Data Output 4" "Logic 0,Logic 1" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO3 ,Port Data Output 3" "Logic 0,Logic 1" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO2 ,Port Data Output 2" "Logic 0,Logic 1" endif sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO1 ,Port Data Output 1" "Logic 0,Logic 1" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO0 ,Port Data Output 0" "Logic 0,Logic 1" endif endif newline width 12. wgroup.long 0x0C++0x03 line.long 0x00 "GPIOE_PTOR,Port E Toggle Output Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")) bitfld.long 0x00 26. " PTTO26 ,Port Toggle Output 26" "No change,Inverse logic" newline bitfld.long 0x00 25. " PTTO25 ,Port Toggle Output 25" "No change,Inverse logic" bitfld.long 0x00 24. " PTTO24 ,Port Toggle Output 24" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" newline bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" newline bitfld.long 0x00 6. " PTTO6 ,Port Toggle Output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" newline bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F64VFM10")) bitfld.long 0x00 25. " PTTO25 ,Port Toggle Output 25" "No change,Inverse logic" newline bitfld.long 0x00 24. " PTTO24 ,Port Toggle Output 24" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" newline bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" sif cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" newline bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 26. " PTTO26 ,Port Toggle Output 26" "No change,Inverse logic" endif newline bitfld.long 0x00 25. " PTTO25 ,Port Toggle Output 25" "No change,Inverse logic" bitfld.long 0x00 24. " PTTO24 ,Port Toggle Output 24" "No change,Inverse logic" bitfld.long 0x00 19. " PTTO19 ,Port Toggle Output 19" "No change,Inverse logic" newline bitfld.long 0x00 18. " PTTO18 ,Port Toggle Output 18" "No change,Inverse logic" bitfld.long 0x00 17. " PTTO17 ,Port Toggle Output 17" "No change,Inverse logic" bitfld.long 0x00 16. " PTTO16 ,Port Toggle Output 16" "No change,Inverse logic" sif cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 6. " PTTO6 ,Port Toggle Output 6" "No change,Inverse logic" bitfld.long 0x00 5. " PTTO5 ,Port Toggle Output 5" "No change,Inverse logic" bitfld.long 0x00 4. " PTTO4 ,Port Toggle Output 4" "No change,Inverse logic" newline bitfld.long 0x00 3. " PTTO3 ,Port Toggle Output 3" "No change,Inverse logic" bitfld.long 0x00 2. " PTTO2 ,Port Toggle Output 2" "No change,Inverse logic" endif sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 1. " PTTO1 ,Port Toggle Output 1" "No change,Inverse logic" bitfld.long 0x00 0. " PTTO0 ,Port Toggle Output 0" "No change,Inverse logic" endif endif rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_PDIR,Port E Data Input Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")) bitfld.long 0x00 26. " PDI26 ,Port Data Input 26" "Logic 0,Logic 1" newline bitfld.long 0x00 25. " PDI25 ,Port Data Input 25" "Logic 0,Logic 1" bitfld.long 0x00 24. " PDI24 ,Port Data Input 24" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" newline bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" newline bitfld.long 0x00 6. " PDI6 ,Port Data Input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" newline bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F64VFM10")) bitfld.long 0x00 25. " PDI25 ,Port Data Input 25" "Logic 0,Logic 1" newline bitfld.long 0x00 24. " PDI24 ,Port Data Input 24" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" newline bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" sif cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" newline bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 26. " PDI26 ,Port Data Input 26" "Logic 0,Logic 1" endif newline bitfld.long 0x00 25. " PDI25 ,Port Data Input 25" "Logic 0,Logic 1" bitfld.long 0x00 24. " PDI24 ,Port Data Input 24" "Logic 0,Logic 1" bitfld.long 0x00 19. " PDI19 ,Port Data Input 19" "Logic 0,Logic 1" newline bitfld.long 0x00 18. " PDI18 ,Port Data Input 18" "Logic 0,Logic 1" bitfld.long 0x00 17. " PDI17 ,Port Data Input 17" "Logic 0,Logic 1" bitfld.long 0x00 16. " PDI16 ,Port Data Input 16" "Logic 0,Logic 1" sif cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 6. " PDI6 ,Port Data Input 6" "Logic 0,Logic 1" bitfld.long 0x00 5. " PDI5 ,Port Data Input 5" "Logic 0,Logic 1" bitfld.long 0x00 4. " PDI4 ,Port Data Input 4" "Logic 0,Logic 1" newline bitfld.long 0x00 3. " PDI3 ,Port Data Input 3" "Logic 0,Logic 1" bitfld.long 0x00 2. " PDI2 ,Port Data Input 2" "Logic 0,Logic 1" endif sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 1. " PDI1 ,Port Data Input 1" "Logic 0,Logic 1" bitfld.long 0x00 0. " PDI0 ,Port Data Input 0" "Logic 0,Logic 1" endif endif group.long 0x14++0x03 line.long 0x00 "GPIOE_PDDR,Port E Data Direction Register" sif (cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F128VLL10")) bitfld.long 0x00 26. " PDD26 ,Port Data Direction 26" "Input,Output" newline bitfld.long 0x00 25. " PDD25 ,Port Data Direction 25" "Input,Output" bitfld.long 0x00 24. " PDD24 ,Port Data Direction 24" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" newline bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" newline bitfld.long 0x00 6. " PDD6 ,Port Data Direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" newline bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" elif (cpuis("MKV31F256VLH12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F128VLH10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLF10")||cpuis("MKV30F128VFM10")||cpuis("MKV30F64VFM10")) bitfld.long 0x00 25. " PDD25 ,Port Data Direction 25" "Input,Output" newline bitfld.long 0x00 24. " PDD24 ,Port Data Direction 24" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" newline bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" sif cpuis("MKV30F128VLH10")||cpuis("MKV30F64VLH10") bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" newline bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 26. " PDD26 ,Port Data Direction 26" "Input,Output" endif newline bitfld.long 0x00 25. " PDD25 ,Port Data Direction 25" "Input,Output" bitfld.long 0x00 24. " PDD24 ,Port Data Direction 24" "Input,Output" bitfld.long 0x00 19. " PDD19 ,Port Data Direction 19" "Input,Output" newline bitfld.long 0x00 18. " PDD18 ,Port Data Direction 18" "Input,Output" bitfld.long 0x00 17. " PDD17 ,Port Data Direction 17" "Input,Output" bitfld.long 0x00 16. " PDD16 ,Port Data Direction 16" "Input,Output" newline sif cpuis("MKV31F512VLL12P") bitfld.long 0x00 6. " PDD6 ,Port Data Direction 6" "Input,Output" bitfld.long 0x00 5. " PDD5 ,Port Data Direction 5" "Input,Output" bitfld.long 0x00 4. " PDD4 ,Port Data Direction 4" "Input,Output" newline bitfld.long 0x00 3. " PDD3 ,Port Data Direction 3" "Input,Output" bitfld.long 0x00 2. " PDD2 ,Port Data Direction 2" "Input,Output" endif sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 1. " PDD1 ,Port Data Direction 1" "Input,Output" newline bitfld.long 0x00 0. " PDD0 ,Port Data Direction 0" "Input,Output" endif endif endif width 0x0B tree.end tree.end elif cpuis("MKV5*") tree.open "PORT (Port control and interrupts)" tree "PORTA" base ad:0x40049000 width 13. group.long 0x00++0x17 line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTA0,UART0_CTS_b/UART0_COL_b,FTM0_CH5,XB_IN4,EWM_IN,,JTAG_TCLK/SWD_CLK,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTA1,UART0_RX,FTM0_CH6,CMP0_OUT,FTM2_QD_PHA,FTM1_CH1,JTAG_TDI,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTA2,UART0_TX,FTM0_CH7,CMP1_OUT,FTM2_QD_PHB,FTM1_CH0,JTAG_TDO/TRACE_SWO,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTA3,UART0_RTS_b,FTM0_CH0,XB_IN9,EWM_OUT_b,FLEXPWM0_A0,JTAG_TMS/SWD_DIO,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTA4/LLWU_P3,,FTM0_CH1,XB_IN10,FTM0_FLT3,FLEXPWM0_B0,NMI_b,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTA5,,FTM0_CH2,RMII0_RXER/MII0_RXER,CMP2_OUT,,JTAG_TRST_b,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x18++0x17 line.long 0x00 "PORTA_PCR6,Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTA6,,FTM0_CH3,,CLKOUT,,TRACE_CLKOUT,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR7,Pin Control Register 7" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTA7,,FTM0_CH4,,RMII0_MDIO/MII0_MDIO,,TRACE_D3,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR8,Pin Control Register 8" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTA8,,FTM1_CH0,,RMII0_MDC/MII0_MDC,,TRACE_D2,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR9,Pin Control Register 9" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTA9,,FTM1_CH1,,MII0_RXD3,,TRACE_D1,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR10,Pin Control Register 10" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTA10/LLWU_P22,,FTM2_CH0,,MII0_RXD2,FTM2_QD_PHA,TRACE_D0,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTA_PCR11,Pin Control Register 11" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTA11/LLWU_P23,,FTM2_CH1,,MII0_RXCLK,FTM2_QD_PHB,,I2C0_SDA,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x30++0x1F line.long 0x00 "PORTA_PCR12,Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTA12,CAN0_TX,FTM1_CH0,,RMII0_RXD1/MII0_RXD1,,FTM1_QD_PHA,I2C0_SCL,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR13,Pin Control Register 13" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTA13/LLWU_P4,CAN0_RX,FTM1_CH1,,RMII0_RXD1/MII0_RXD0,,FTM1_QD_PHB,I2C1_SDA,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR14,Pin Control Register 14" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTA14,SPI0_PCS0,UART0_TX,CAN2_TX,RMII0_CRS_DV/MII0_RXDV,,,I2C1_SCL,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR15,Pin Control Register 15" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTA15,SPI0_SCK,UART0_RX,CAN2_RX,RMII0_TXEN/MII0_TXEN,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR16,Pin Control Register 16" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTA16,SPI0_SOUT,UART0_CTS_b/UART0_COL_b,,RMII0_TXD0/MII0_TXD0,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTA_PCR17,Pin Control Register 17" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTA17,SPI0_SIN,UART0_RTS_b,,RMII0_TXD1/MII0_TXD1,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTA_PCR18,Pin Control Register 18" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTA18,XB_IN7,FTM0_FLT2,FTM_CLKIN0,XB_OUT8,FTM3_CH2,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTA_PCR19,Pin Control Register 19" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--11. " MUX ,Pin mux control" "Disabled,PTA19,XB_IN8,FTM1_FLT0,FTM_CLKIN1,XB_OUT9,LPTMR0_ALT1,?..." bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x60++0x17 line.long 0x00 "PORTA_PCR24,Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTA24,XB_IN4,,,MII0_TXD2,,,FB_A29,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR25,Pin Control Register 25" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTA25,XB_IN5,,,MII0_TXCLK,,,FB_A28,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR26,Pin Control Register 26" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTA26,,,,MII0_TXD3,,,FB_A27,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR27,Pin Control Register 27" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTA27,,,,MII0_CRS,,,FB_A26,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR28,Pin Control Register 28" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTA28,,,,MII0_TXER,,,FB_A25,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive Filter Enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTA_PCR29,Pin Control Register 29" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTA29,,,,MII0_COL,,,FB_A24,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Not updated,Updated" bitfld.long 0x00 30. " [14] ,Global pin 14 write enable" "Not updated,Updated" bitfld.long 0x00 29. " [13] ,Global pin 13 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 27. " [11] ,Global pin 11 write enable" "Not updated,Updated" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Not updated,Updated" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Not updated,Updated" bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Not updated,Updated" bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Not updated,Updated" textline " " endif bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Not updated,Updated" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Not updated,Updated" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Not updated,Updated" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 15. " GPWD[15] ,Global pin 15 write data" "Low,High" bitfld.long 0x00 14. " [14] ,Global pin 14 write data" "Low,High" bitfld.long 0x00 13. " [13] ,Global pin 13 write data" "Low,High" textline " " bitfld.long 0x00 12. " [12] ,Global pin 12 write data" "Low,High" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 11. " [11] ,Global pin 11 write data" "Low,High" bitfld.long 0x00 10. " [10] ,Global pin 10 write data" "Low,High" bitfld.long 0x00 9. " [9] ,Global pin 9 write data" "Low,High" textline " " bitfld.long 0x00 8. " [8] ,Global pin 8 write data" "Low,High" bitfld.long 0x00 7. " [7] ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " [6] ,Global pin 6 write data" "Low,High" textline " " endif bitfld.long 0x00 5. " [5] ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " [4] ,Global pin 4 write data" "Low,High" bitfld.long 0x00 3. " [3] ,Global pin 3 write data" "Low,High" textline " " bitfld.long 0x00 2. " [2] ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " [1] ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " [0] ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTA_GPCHR,Global pin Control High Register" sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 29. " GPWE[29] ,Global pin 29 write enable" "Not updated,Updated" bitfld.long 0x04 28. " [28] ,Global pin 28 write enable" "Not updated,Updated" bitfld.long 0x04 27. " [27] ,Global pin 27 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 26. " [26] ,Global pin 26 write enable" "Not updated,Updated" bitfld.long 0x04 25. " [25] ,Global pin 25 write enable" "Not updated,Updated" bitfld.long 0x04 24. " [24] ,Global pin 24 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 19. " [19] ,Global pin 19 write enable" "Not updated,Updated" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Not updated,Updated" bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Not updated,Updated" else bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Not updated,Updated" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Not updated,Updated" bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Not updated,Updated" endif textline " " bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 13. " GPWD[29] ,Global pin 29 write data" "Low,High" bitfld.long 0x04 12. " [28] ,Global pin 28 write data" "Low,High" bitfld.long 0x04 11. " [27] ,Global pin 27 write data" "Low,High" textline " " bitfld.long 0x04 10. " [26] ,Global pin 26 write data" "Low,High" bitfld.long 0x04 9. " [25] ,Global pin 25 write data" "Low,High" bitfld.long 0x04 8. " [24] ,Global pin 24 write data" "Low,High" textline " " bitfld.long 0x04 3. " [19] ,Global pin 19 write data" "Low,High" bitfld.long 0x04 2. " [18] ,Global pin 18 write data" "Low,High" bitfld.long 0x04 1. " [17] ,Global pin 17 write data" "Low,High" else bitfld.long 0x04 3. " GPWD[19] ,Global pin 19 write data" "Low,High" bitfld.long 0x04 2. " [18] ,Global pin 18 write data" "Low,High" bitfld.long 0x04 1. " [17] ,Global pin 17 write data" "Low,High" endif textline " " bitfld.long 0x04 0. " [16] ,Global pin 16 write data" "Low,High" group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register" sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 29. " ISF[29] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 28. " [28] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 27. " [27] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 26. " [26] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 25. " [25] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 24. " [24] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 19. " [19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" textline " " else eventfld.long 0x00 19. " ISF[19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 15. " [15] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 14. " [14] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 12. " [12] ,Interrupt status flag" "Not detected,Detected" textline " " sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 11. " [11] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree "PORTB" base ad:0x4004A000 width 13. group.long 0x00++0x0F line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTB0/LLWU_P5,I2C0_SCL,FTM1_CH0,,,FTM1_QD_PHA,UART0_RX,RMII0_MDIO/MII0_MDIO,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTB1,I2C0_SDA,FTM1_CH1,FTM0_FLT2,EWM_IN,FTM1_QD_PHB,UART0_TX,RMII0_MDC/MII0_MDC,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTB2,I2C0_SCL,UART0_RTS_b,FTM0_FLT1,ENET0_1588_TMR0,FTM0_FLT3,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTB3,I2C0_SDA,UART0_CTS_b/UART0_COL_b,,ENET0_1588_TMR1,FTM0_FLT0,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x10++0x013 line.long 0x00 "PORTB_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTB4,,,FLEXPWM1_X0,ENET0_1588_TMR2,FTM1_FLT0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTB5,,,FLEXPWM1_X1,ENET0_1588_TMR3,FTM2_FLT0,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTB6,CAN2_TX,,FLEXPWM1_X2,,,,FB_AD23,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTB7,CAN2_RX,,FLEXPWM1_X3,,,,FB_AD22,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTB_PCR8,Pin Control Register 8" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTB8,,UART3_RTS_b,,,,,FB_AD21,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x24++0x0B line.long 0x00 "PORTB_PCR9,Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTB9,SPI1_PCS1,UART3_CTS_b,,ENET0_1588_TMR2,,,FB_AD20,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR10,Pin Control Register 10" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "HSADC0B_CH6,PTB10,SPI1_PCS0,UART3_RX,,ENET0_1588_TMR3,FTM0_FLT1,,FB_AD19,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR11,Pin Control Register 11" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "HSADC0B_CH7,PTB11,SPI1_SCK,UART3_TX,,,FTM0_FLT2,,FB_AD18,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x40++0x1F line.long 0x00 "PORTB_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "DISABLED,PTB16,SPI1_SOUT,UART0_RX,FTM_CLKIN2,CAN0_TX,EWM_IN,XB_IN5,FB_AD17,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "DISABLED,PTB17,SPI1_SIN,UART0_TX,FTM_CLKIN1,CAN0_RX,EWM_OUT_b,,FB_AD16,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR18,Pin Control Register 18" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "DISABLED,PTB18,CAN0_TX,FTM2_CH0,FTM3_CH2,FLEXPWM1_A1,FTM2_QD_PHA,,FB_AD15,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR19,Pin Control Register 19" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "DISABLED,PTB19,CAN0_RX,FTM2_CH1,FTM3_CH3,FLEXPWM1_B1,FTM2_QD_PHB,,FB_OE_b,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTB_PCR20,Pin Control Register 20" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "DISABLED,PTB20,SPI2_PCS0,,,FLEXPWM0_X0,CMP0_OUT,,FB_AD31,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTB_PCR21,Pin Control Register 21" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "DISABLED,PTB21,SPI2_SCK,,,FLEXPWM0_X1,CMP1_OUT,,FB_AD30,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTB_PCR22,Pin Control Register 22" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "DISABLED,PTB22,SPI2_SOUT,,,FLEXPWM0_X2,CMP2_OUT,,FB_AD29,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTB_PCR23,Pin Control Register 23" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--11. " MUX ,Pin mux control" "DISABLED,PTB23,SPI2_SIN,SPI0_PCS5,,FLEXPWM0_X3,CMP3_OUT,,FB_AD28,?..." bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Not updated,Updated" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Not updated,Updated" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Not updated,Updated" bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Not updated,Updated" bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Not updated,Updated" textline " " endif bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Not updated,Updated" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Not updated,Updated" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 11. " GPWD[11] ,Global pin 11 write data" "Low,High" bitfld.long 0x00 10. " [10] ,Global pin 10 write data" "Low,High" textline " " bitfld.long 0x00 9. " [9] ,Global pin 9 write data" "Low,High" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 8. " [8] ,Global pin 8 write data" "Low,High" bitfld.long 0x00 7. " [7] ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " [6] ,Global pin 6 write data" "Low,High" textline " " bitfld.long 0x00 5. " [5] ,Global pin 5 write data" "Low,High" bitfld.long 0x00 4. " [4] ,Global pin 4 write data" "Low,High" textline " " endif bitfld.long 0x00 3. " [3] ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " [2] ,Global pin 2 write data" "Low,High" bitfld.long 0x00 1. " [1] ,Global pin 1 write data" "Low,High" textline " " bitfld.long 0x00 0. " [0] ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTB_GPCHR,Global pin Control High Register" bitfld.long 0x04 23. " GPWE[23] ,Global pin 23 write enable" "Not updated,Updated" bitfld.long 0x04 22. " [22] ,Global pin 22 write enable" "Not updated,Updated" bitfld.long 0x04 21. " [21] ,Global pin 21 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 20. " [20] ,Global pin 20 write enable" "Not updated,Updated" bitfld.long 0x04 19. " [19] ,Global pin 19 write enable" "Not updated,Updated" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Not updated,Updated" bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 7. " GPWD[23] ,Global pin 23 write data" "Low,High" textline " " bitfld.long 0x04 6. " [22] ,Global pin 22 write data" "Low,High" bitfld.long 0x04 5. " [21] ,Global pin 21 write data" "Low,High" bitfld.long 0x04 4. " [20] ,Global pin 20 write data" "Low,High" textline " " bitfld.long 0x04 3. " [19] ,Global pin 19 write data" "Low,High" bitfld.long 0x04 2. " [18] ,Global pin 18 write data" "Low,High" bitfld.long 0x04 1. " [17] ,Global pin 17 write data" "Low,High" textline " " bitfld.long 0x04 0. " [16] ,Global pin 16 write data" "Low,High" group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 23. " ISF[23] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 22. " [22] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 21. " [21] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 20. " [20] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 19. " [19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 11. " [11] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" textline " " sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree "PORTC" base ad:0x4004B000 width 13. group.long 0x00++0x4B line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTC0,SPI0_PCS4,PDB0_EXTRG,,,FTM0_FLT1,SPI0_PCS0,FB_AD14,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,FLEXPWM0_A3,XB_IN11,,FB_AD13,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,FLEXPWM0_B3,XB_IN6,,FB_AD12,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,FTM3_FLT0,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,,FB_AD11,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,XB_IN2,,CMP0_OUT,FTM0_CH2,FB_AD10,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,XB_IN3,UART0_RX,XB_OUT6,I2C0_SCL,FB_AD9,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--11. " MUX ,Pin mux control" "Disabled,PTC7,SPI0_SIN,,XB_IN4,UART0_TX,XB_OUT7,I2C0_SDA,FB_AD8,?..." bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x20 "PORTC_PCR8,Pin Control Register 8" eventfld.long 0x20 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x20 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x20 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x20 8.--11. " MUX ,Pin mux control" "Disabled,PTC8,,FTM3_CH4,FLEXPWM1_A2,,,,FB_AD7,?..." bitfld.long 0x20 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x20 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x20 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x20 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x24 "PORTC_PCR9,Pin Control Register 9" eventfld.long 0x24 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x24 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x24 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x24 8.--11. " MUX ,Pin mux control" "Disabled,PTC9,,FTM3_CH5,FLEXPWM1_B2,,,,FB_AD6,?..." bitfld.long 0x24 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x24 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x24 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x24 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x24 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x24 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x28 "PORTC_PCR10,Pin Control Register 10" eventfld.long 0x28 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x28 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x28 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x28 8.--11. " MUX ,Pin mux control" "Disabled,PTC10,I2C1_SCL,FTM3_CH6,FLEXPWM1_A3,,,,FB_AD5,?..." bitfld.long 0x28 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x28 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x28 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x28 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x28 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x28 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x2C "PORTC_PCR11,Pin Control Register 11" eventfld.long 0x2C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x2C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x2C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x2C 8.--11. " MUX ,Pin mux control" "Disabled,PTC11/LLWU_P11,I2C1_SDA,FTM3_CH7,FLEXPWM1_B3,,,,FB_RW_b,?..." bitfld.long 0x2C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x2C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x2C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x2C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x2C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x30 "PORTC_PCR12,Pin Control Register 12" eventfld.long 0x30 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x30 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x30 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x30 8.--11. " MUX ,Pin mux control" "Disabled,PTC12,CAN2_TX,,FTM_CLKIN0,FLEXPWM1_A1,FTM3_FLT0,SPI2_PCS1,FB_AD27,UART4_RTS_b,?..." bitfld.long 0x30 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x30 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x30 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x30 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x30 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x30 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x34 "PORTC_PCR13,Pin Control Register 13" eventfld.long 0x34 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x34 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x34 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x34 8.--11. " MUX ,Pin mux control" "Disabled,PTC13,CAN2_RX,,FTM_CLKIN1,FLEXPWM1_B1,,,FB_AD26,UART4_CTS_b,?..." bitfld.long 0x34 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x34 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x34 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x34 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x34 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x34 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x38 "PORTC_PCR14,Pin Control Register 14" eventfld.long 0x38 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x38 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x38 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x38 8.--11. " MUX ,Pin mux control" "Disabled,PTC14,I2C1_SCL,I2C0_SCL,,FLEXPWM1_A0,,,FB_AD25,UART4_RX,?..." bitfld.long 0x38 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x38 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x38 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x38 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x38 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x38 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x3C "PORTC_PCR15,Pin Control Register 15" eventfld.long 0x3C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x3C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x3C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x3C 8.--11. " MUX ,Pin mux control" "Disabled,PTC15,I2C1_SDA,I2C0_SDA,,FLEXPWM1_B0,,,FB_AD24,UART4_TX,?..." textline " " bitfld.long 0x3C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x3C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x3C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x3C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x3C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x3C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x40 "PORTC_PCR16,Pin Control Register 16" eventfld.long 0x40 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x40 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x40 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x40 8.--11. " MUX ,Pin mux control" "Disabled,PTC16,CAN1_RX,UART3_RX,ENET0_1588_TMR0,FLEXPWM1_A2,,,FB_CS5_b/FB_TSIZ1/FB_BE23_16_b,?..." textline " " bitfld.long 0x40 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x40 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x40 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x40 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x40 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x40 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x44 "PORTC_PCR17,Pin Control Register 17" eventfld.long 0x44 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x44 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x44 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x44 8.--11. " MUX ,Pin mux control" "Disabled,PTC17,CAN1_TX,UART3_TX,ENET0_1588_TMR1,FLEXPWM1_B2,,,FB_CS4_b/FB_TSIZ0/FB_BE31_24_b,?..." textline " " bitfld.long 0x44 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x44 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x44 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x44 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x44 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x44 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x48 "PORTC_PCR18,Pin Control Register 18" eventfld.long 0x48 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x48 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x48 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x48 8.--11. " MUX ,Pin mux control" "Disabled,PTC18,,UART3_RTS_b,ENET0_1588_TMR2,FLEXPWM1_A3,,,FB_TBST_b/FB_CS2_b/FB_BE15_8_b,?..." textline " " bitfld.long 0x48 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x48 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x48 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x48 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x48 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x48 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR19,Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTC19,,UART3_CTS_b,ENET0_1588_TMR3,FLEXPWM1_B3,,,FB_CS3_b/FB_BE7_0_b,FB_TA_b,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Not updated,Updated" bitfld.long 0x00 30. " GPWE[14] ,Global pin 14 write enable" "Not updated,Updated" bitfld.long 0x00 29. " GPWE[13] ,Global pin 13 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 28. " GPWE[12] ,Global pin 12 write enable" "Not updated,Updated" bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Not updated,Updated" bitfld.long 0x00 26. " GPWE[10] ,Global pin 10 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 25. " GPWE[9] ,Global pin 9 write enable" "Not updated,Updated" bitfld.long 0x00 24. " GPWE[8] ,Global pin 8 write enable" "Not updated,Updated" bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 22. " GPWE[6] ,Global pin 6 write enable" "Not updated,Updated" bitfld.long 0x00 21. " GPWE[5] ,Global pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " GPWE[4] ,Global pin 4 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 19. " GPWE[3] ,Global pin 3 write enable" "Not updated,Updated" bitfld.long 0x00 18. " GPWE[2] ,Global pin 2 write enable" "Not updated,Updated" bitfld.long 0x00 17. " GPWE[1] ,Global pin 1 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 16. " GPWE[0] ,Global pin 0 write enable" "Not updated,Updated" bitfld.long 0x00 15. " GPWE[15] ,Global pin 15 write enable" "Not updated,Updated" bitfld.long 0x00 14. " GPWE[14] ,Global pin 14 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 13. " GPWE[13] ,Global pin 13 write enable" "Not updated,Updated" bitfld.long 0x00 12. " GPWE[12] ,Global pin 12 write enable" "Not updated,Updated" bitfld.long 0x00 11. " GPWD[11] ,Global pin 11 write data" "Low,High" textline " " bitfld.long 0x00 10. " GPWD[10] ,Global pin 10 write data" "Low,High" bitfld.long 0x00 9. " GPWD[9] ,Global pin 9 write data" "Low,High" bitfld.long 0x00 8. " GPWD[8] ,Global pin 8 write data" "Low,High" textline " " bitfld.long 0x00 7. " GPWD[7] ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " GPWD[6] ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " GPWD[5] ,Global pin 5 write data" "Low,High" textline " " bitfld.long 0x00 4. " GPWD[4] ,Global pin 4 write data" "Low,High" bitfld.long 0x00 3. " GPWD[3] ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " GPWD[2] ,Global pin 2 write data" "Low,High" textline " " bitfld.long 0x00 1. " GPWD[1] ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " GPWD[0] ,Global pin 0 write data" "Low,High" line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register" sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Not updated,Updated" textline " " endif bitfld.long 0x04 18. " GPWE[18] ,Global pin 18 write enable" "Not updated,Updated" bitfld.long 0x04 17. " GPWE[17] ,Global pin 17 write enable" "Not updated,Updated" bitfld.long 0x04 16. " GPWE[16] ,Global pin 16 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 3. " GPWD[19] ,Global pin 19 write data" "Low,High" textline " " endif bitfld.long 0x04 2. " GPWD[18] ,Global pin 18 write data" "Low,High" bitfld.long 0x04 1. " GPWD[17] ,Global pin 17 write data" "Low,High" bitfld.long 0x04 0. " GPWD[16] ,Global pin 16 write data" "Low,High" group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 19. " ISF19 ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 18. " ISF18 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 15. " ISF15 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 14. " ISF14 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 13. " ISF13 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " ISF12 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 11. " ISF11 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 9. " ISF9 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree "PORTD" base ad:0x4004C000 width 13. group.long 0x00++0x1F line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTD0/LLWU_P12,SPI0_PCS0,UART2_RTS_b,FTM3_CH0,FTM0_CH0,FLEXPWM0_A0,,FB_ALE/FB_CS1_b/FB_TS_b,FLEXPWM1_A0,?..." textline " " bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTD1,SPI0_SCK,UART2_CTS_b,FTM3_CH1,FTM0_CH1,FLEXPWM0_B0,,FB_CS0_b,FLEXPWM1_B0,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTD2/LLWU_P13,SPI0_SOUT,UART2_RX,FTM3_CH2,FTM0_CH2,FLEXPWM0_A1,I2C0_SCL,FB_AD4,FLEXPWM1_A1,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTD3,SPI0_SIN,UART2_TX,FTM3_CH3,FTM0_CH3,FLEXPWM0_B1,I2C0_SDA,FB_AD3,FLEXPWM1_B1,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FLEXPWM0_A2,EWM_IN,SPI1_PCS0,FB_AD2,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTD5,SPI0_PCS2,UART0_CTS_b,FTM0_CH5,FLEXPWM0_B2,EWM_OUT_b,SPI1_SCK,FB_AD1,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH6,FTM1_CH0,FTM0_FLT0,SPI1_SOUT,FB_AD0,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--11. " MUX ,Pin mux control" "Disabled,PTD7,,UART0_TX,FTM0_CH7,FTM1_CH1,FTM0_FLT1,SPI1_SIN,?..." bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x20++0x1F line.long 0x00 "PORTD_PCR8,Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTD8/LLWU_P24,I2C1_SCL,UART5_RX,,,FLEXPWM0_A3,,FB_A16,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR9,Pin Control Register 9" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTD9,I2C1_SDA,UART5_TX,,,FLEXPWM0_B3,,FB_A17,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR10,Pin Control Register 10" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTD10,,UART5_RTS_b,,,FLEXPWM0_A2,,FB_A18,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR11,Pin Control Register 11" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTD11/LLWU_P25,SPI2_PCS0,UART5_CTS_b,,,FLEXPWM0_B2,,FB_A19,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTD_PCR12,Pin Control Register 12" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTD12,SPI2_SCK,FTM3_FLT0,XB_IN5,XB_OUT5,FLEXPWM0_A1,,FB_A20,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTD_PCR13,Pin Control Register 13" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTD13,SPI2_SOUT,,XB_IN7,XB_OUT7,FLEXPWM0_B1,,FB_A21,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTD_PCR14,Pin Control Register 14" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTD14,SPI2_SIN,,XB_IN11,XB_OUT11,FLEXPWM0_A0,,FB_A22,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTD_PCR15,Pin Control Register 15" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,,," bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--11. " MUX ,Pin mux control" "Disabled,PTD15,SPI2_PCS1,,,,FLEXPWM0_B0,,FB_A23,?..." bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x03 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE[15] ,Global pin 15 write enable" "Not updated,Updated" bitfld.long 0x00 30. " [14] ,Global pin 14 write enable" "Not updated,Updated" bitfld.long 0x00 29. " [13] ,Global pin 13 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Not updated,Updated" bitfld.long 0x00 27. " [11] ,Global pin 11 write enable" "Not updated,Updated" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Not updated,Updated" bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Not updated,Updated" bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Not updated,Updated" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Not updated,Updated" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Not updated,Updated" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Not updated,Updated" bitfld.long 0x00 15. " [15] ,Global pin 15 write enable" "Not updated,Updated" bitfld.long 0x00 14. " [14] ,Global pin 14 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 13. " [13] ,Global pin 13 write enable" "Not updated,Updated" bitfld.long 0x00 12. " [12] ,Global pin 12 write enable" "Not updated,Updated" bitfld.long 0x00 11. " GPWD[11] ,Global pin 11 write data" "Low,High" textline " " bitfld.long 0x00 10. " [10] ,Global pin 10 write data" "Low,High" bitfld.long 0x00 9. " [9] ,Global pin 9 write data" "Low,High" bitfld.long 0x00 8. " [8] ,Global pin 8 write data" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Global pin 7 write data" "Low,High" bitfld.long 0x00 6. " [6] ,Global pin 6 write data" "Low,High" bitfld.long 0x00 5. " [5] ,Global pin 5 write data" "Low,High" textline " " bitfld.long 0x00 4. " [4] ,Global pin 4 write data" "Low,High" bitfld.long 0x00 3. " [3] ,Global pin 3 write data" "Low,High" bitfld.long 0x00 2. " [2] ,Global pin 2 write data" "Low,High" textline " " bitfld.long 0x00 1. " [1] ,Global pin 1 write data" "Low,High" bitfld.long 0x00 0. " [0] ,Global pin 0 write data" "Low,High" hgroup.long 0x84++0x03 hide.long 0x00 "PORTD_GPCHR,Global Pin Control High Register" group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 15. " ISF[15] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 14. " [14] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 12. " [12] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 11. " [11] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 15. " DFE[15] ,Digital filter enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Digital filter enable 14 write enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " [13] ,Digital filter enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Digital filter enable 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " [10] ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " [7] ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " [4] ,Digital filter enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " [1] ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter enable 0" "Disabled,Enabled" line.long 0x04 "PORTD_DFCR,Digital Clock Enable Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus clock,LPO clock" line.long 0x08 "PORTD_DFWR,Digital Width Enable Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTE" base ad:0x4004D000 width 13. group.long 0x00++0x1B line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE0,SPI1_PCS1,UART1_TX,XB_OUT10,XB_IN11,I2C1_SDA,,TRACE_CLKOUT,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE1/LLWU_P0,SPI1_SOUT,UART1_RX,XB_OUT11,XB_IN7,I2C1_SCL,,TRACE_D3,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTE2/LLWU_P1,SPI1_SCK,UART1_CTS_b,,,,,TRACE_D2,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTE3,SPI1_SIN,UART1_RTS_b,,,,,TRACE_D1,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTE_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTE4/LLWU_P2,SPI1_PCS0,UART3_TX,,,,,TRACE_D0,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTE_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTE5,SPI1_PCS2,UART3_RX,,FLEXPWM1_A0,FTM3_CH0,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTE_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTE6/LLWU_P16,SPI1_PCS3,UART3_CTS_b,,FLEXPWM1_B0,FTM3_CH1,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x1C++0x1B line.long 0x00 "PORTE_PCR7,Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE7,,UART3_RTS_b,,FLEXPWM1_A1,FTM3_CH2,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR8,Pin Control Register 8" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE8,,UART5_TX,,FLEXPWM1_B1,FTM3_CH3,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR9,Pin Control Register 9" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTE9/LLWU_P17,,UART5_RX,,FLEXPWM1_A2,FTM3_CH4,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR10,Pin Control Register 10" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTE10/LLWU_P18,,UART5_CTS_b,,FLEXPWM1_B2,FTM3_CH5,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTE_PCR11,Pin Control Register 11" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTE11,,UART5_RTS_b,,FLEXPWM1_A3,FTM3_CH6,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTE_PCR12,Pin Control Register 12" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTE12,,,,FLEXPWM1_B3,FTM3_CH7,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTE_PCR13,Pin Control Register 13" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--11. " MUX ,Pin mux control" "Disabled,PTE13,?..." bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x40++0x17 line.long 0x00 "PORTE_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE16,SPI0_PCS0,UART2_TX,FTM_CLKIN0,,FTM0_FLT3,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE17/LLWU_P19,SPI0_SCK,UART2_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR18,Pin Control Register 18" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTE18/LLWU_P20,SPI0_SOUT,UART2_CTS_b,I2C0_SDA,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR19,Pin Control Register 19" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--11. " MUX ,Pin mux control" "Disabled,PTE19,SPI0_SIN,UART2_RTS_b,I2C0_SCL,,CMP3_OUT,?..." bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTE_PCR20,Pin Control Register 20" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--11. " MUX ,Pin mux control" "Disabled,PTE20,,FTM1_CH0,UART0_TX,FTM1_QD_PHA,?..." bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTE_PCR21,Pin Control Register 21" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--11. " MUX ,Pin mux control" "Disabled,PTE21,XB_IN9,FTM1_CH1,UART0_RX,FTM1_QD_PHB,?..." bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x58++0x07 line.long 0x00 "PORTE_PCR22,Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE22,,FTM2_CH0,XB_IN2,FTM2_QD_PHA,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR23,Pin Control Register 23" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE23,,FTM2_CH1,XB_IN3,FTM2_QD_PHB,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x60++0x0B line.long 0x00 "PORTE_PCR24,Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE24,CAN1_TX,FTM0_CH0,XB_IN2,I2C0_SCL,EWM_OUT_b,XB_OUT4,UART4_TX,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR25,Pin Control Register 25" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE25/LLWU_P21,CAN1_RX,FTM0_CH1,XB_IN3,I2C0_SDA,EWM_IN,XB_OUT5,UART4_RX,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR26,Pin Control Register 26" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--11. " MUX ,Pin mux control" "Disabled,PTE26,ENET_1588_CLKIN,FTM0_CH4,,,,,UART4_CTS_b,?..." bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" sif (!cpuis("MKV??F???VLL24")) group.long 0x6C++0x07 line.long 0x00 "PORTE_PCR27,Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE27,CAN2_TX,,,,,,UART4_RTS_b,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR28,Pin Control Register 28" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE28,CAN2_RX,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x74++0x07 line.long 0x00 "PORTE_PCR29,Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,PTE29,,FTM0_CH2,,FTM_CLKIN0,?..." bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR30,Pin Control Register 30" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising edge,DMA-falling edge,DMA-either edge,,,,,On logic 0,Rising edge,Falling edge,Either edge,On logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--11. " MUX ,Pin mux control" "Disabled,PTE30,,FTM0_CH3,,FTM_CLKIN1,?..." bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 29. " GPWE[13] ,Global Pin 13 write enable" "Not updated,Updated" bitfld.long 0x00 28. " [12] ,Global Pin 12 write enable" "Not updated,Updated" bitfld.long 0x00 27. " [11] ,Global Pin 11 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 26. " [10] ,Global Pin 10 write enable" "Not updated,Updated" bitfld.long 0x00 25. " [9] ,Global Pin 9 write enable" "Not updated,Updated" bitfld.long 0x00 24. " [8] ,Global Pin 8 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 23. " [7] ,Global Pin 7 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 22. " [6] ,Global Pin 6 write enable" "Not updated,Updated" bitfld.long 0x00 21. " [5] ,Global Pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " [4] ,Global Pin 4 write enable" "Not updated,Updated" else bitfld.long 0x00 22. " GPWE[6] ,Global Pin 6 write enable" "Not updated,Updated" bitfld.long 0x00 21. " [5] ,Global Pin 5 write enable" "Not updated,Updated" bitfld.long 0x00 20. " [4] ,Global Pin 4 write enable" "Not updated,Updated" endif textline " " bitfld.long 0x00 19. " [3] ,Global Pin 3 write enable" "Not updated,Updated" bitfld.long 0x00 18. " [2] ,Global Pin 2 write enable" "Not updated,Updated" bitfld.long 0x00 17. " [1] ,Global Pin 1 write enable" "Not updated,Updated" textline " " bitfld.long 0x00 16. " [0] ,Global Pin 0 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x00 13. " GPWD[13] ,Global Pin 13 write data" "Low,High" bitfld.long 0x00 12. " [12] ,Global Pin 12 write data" "Low,High" bitfld.long 0x00 11. " [11] ,Global Pin 11 write data" "Low,High" textline " " bitfld.long 0x00 10. " [10] ,Global Pin 10 write data" "Low,High" bitfld.long 0x00 9. " [9] ,Global Pin 9 write data" "Low,High" bitfld.long 0x00 8. " [8] ,Global Pin 8 write data" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Global Pin 7 write data" "Low,High" textline " " bitfld.long 0x00 6. " [6] ,Global Pin 6 write data" "Low,High" bitfld.long 0x00 5. " [5] ,Global Pin 5 write data" "Low,High" bitfld.long 0x00 4. " [4] ,Global Pin 4 write data" "Low,High" textline " " else bitfld.long 0x00 6. " GPWD[6] ,Global Pin 6 write data" "Low,High" bitfld.long 0x00 5. " [5] ,Global Pin 5 write data" "Low,High" bitfld.long 0x00 4. " [4] ,Global Pin 4 write data" "Low,High" textline " " endif bitfld.long 0x00 3. " [3] ,Global Pin 3 write data" "Low,High" bitfld.long 0x00 2. " [2] ,Global Pin 2 write data" "Low,High" bitfld.long 0x00 1. " [1] ,Global Pin 1 write data" "Low,High" textline " " bitfld.long 0x00 0. " [0] ,Global Pin 0 write data" "Low,High" line.long 0x04 "PORTE_GPCHR,Global Pin Control High Register" bitfld.long 0x04 30. " GPWE[30] ,Global Pin 30 write enable" "Not updated,Updated" bitfld.long 0x04 29. " [29] ,Global Pin 29 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 28. " [28] ,Global Pin 28 write enable" "Not updated,Updated" bitfld.long 0x04 27. " [27] ,Global Pin 27 write enable" "Not updated,Updated" textline " " endif bitfld.long 0x04 26. " [26] ,Global Pin 26 write enable" "Not updated,Updated" bitfld.long 0x04 25. " [25] ,Global Pin 25 write enable" "Not updated,Updated" bitfld.long 0x04 24. " [24] ,Global Pin 24 write enable" "Not updated,Updated" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 23. " [23] ,Global Pin 23 write enable" "Not updated,Updated" bitfld.long 0x04 22. " [22] ,Global Pin 22 write enable" "Not updated,Updated" textline " " endif bitfld.long 0x04 21. " [21] ,Global Pin 21 write enable" "Not updated,Updated" bitfld.long 0x04 20. " [20] ,Global Pin 20 write enable" "Not updated,Updated" bitfld.long 0x04 19. " [19] ,Global Pin 19 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 18. " [18] ,Global Pin 18 write enable" "Not updated,Updated" bitfld.long 0x04 17. " [17] ,Global Pin 17 write enable" "Not updated,Updated" bitfld.long 0x04 16. " [16] ,Global Pin 16 write enable" "Not updated,Updated" textline " " bitfld.long 0x04 14. " GPWD[30] ,Global Pin 30 write data" "Low,High" bitfld.long 0x04 13. " [29] ,Global Pin 29 write data" "Low,High" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 12. " [28] ,Global Pin 28 write data" "Low,High" bitfld.long 0x04 11. " [27] ,Global Pin 27 write data" "Low,High" textline " " endif bitfld.long 0x04 10. " [26] ,Global Pin 26 write data" "Low,High" bitfld.long 0x04 9. " [25] ,Global Pin 25 write data" "Low,High" bitfld.long 0x04 8. " [24] ,Global Pin 24 write data" "Low,High" textline " " sif (!cpuis("MKV??F???VLL24")) bitfld.long 0x04 7. " [23] ,Global Pin 23 write data" "Low,High" bitfld.long 0x04 6. " [22] ,Global Pin 22 write data" "Low,High" textline " " endif bitfld.long 0x04 5. " [21] ,Global Pin 21 write data" "Low,High" bitfld.long 0x04 4. " [20] ,Global Pin 20 write data" "Low,High" bitfld.long 0x04 3. " [19] ,Global Pin 19 write data" "Low,High" textline " " bitfld.long 0x04 2. " [18] ,Global Pin 18 write data" "Low,High" bitfld.long 0x04 1. " [17] ,Global Pin 17 write data" "Low,High" bitfld.long 0x04 0. " [16] ,Global Pin 16 write data" "Low,High" group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 30. " ISF[30] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 29. " [29] ,Interrupt status flag" "Not detected,Detected" textline " " sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 28. " [28] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 27. " [27] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 26. " [26] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 25. " [25] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 24. " [24] ,Interrupt status flag" "Not detected,Detected" textline " " sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 23. " [23] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 22. " [22] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 21. " [21] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 20. " [20] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 19. " [19] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" textline " " sif (!cpuis("MKV??F???VLL24")) eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 12. " [12] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 11. " [11] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" textline " " endif eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" width 0x0B tree.end tree.end tree "SIM (System Integration Module)" base ad:0x40047000 width 10. group.long 0x00++0x03 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,,LPO 1kHz" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",,,,,,,128 KB,256 KB,?..." base ad:0x40048000 group.long 0x04++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 20.--21. " TIMESRC ,IEEE 1588 timestamp clock source select" "Core/system,MCGFLLCLK/MCGPLLCLK,OSCERCLK,External bypass" bitfld.long 0x00 19. " RMIISRC ,RMII clock source select" "EXTAL,External bypass" bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLLCLK,?..." textline " " bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system" bitfld.long 0x00 8.--9. " FBSL ,FlexBus security level" "disallowed/disallowed,disallowed/disallowed,disallowed/allowed,allowed/allowed" bitfld.long 0x00 5.--7. " CLKOUTSEL ,CLKOUT select" "FlexBus CLKOUT,,Flash clock,LPO clock,MCGIRCLK,OSCERCLK_UNDIV,OSCERCLK,?..." group.long 0x0C++0x07 line.long 0x00 "SOPT4,System Options Register 4" bitfld.long 0x00 30. " FTM3TRG2SRC ,FlexTimer 3 hardware trigger 2 source select" "FTM3_FLT0,XBARA output 37" bitfld.long 0x00 29. " FTM3TRG1SRC ,FlexTimer 3 hardware trigger 1 source select" "PDB1 channel 1 output trigger,FTM1 channel match" bitfld.long 0x00 28. " FTM3TRG0SRC ,FlexTimer 3 hardware trigger 0 source select" "CMP0 output,FTM1 channel match" textline " " bitfld.long 0x00 26. " FTM2TRG2SRC ,FlexTimer 2 hardware trigger 2 source select" "FTM2_FLT0 pin,XBARA output 36" bitfld.long 0x00 24. " FTM2TRG0SRC ,FlexTimer 2 hardware trigger 0 source select" "CMP0 output,FTM0 channel match" bitfld.long 0x00 22. " FTM1TRG2SRC ,FlexTimer 1 hardware trigger 2 source select" "FTM1_FLT0 pin,XBARA output 35" textline " " bitfld.long 0x00 20. " FTM1TRG0SRC ,FlexTimer 1 hardware trigger 0 source select" "CMP0 output,FTM0 channel match" bitfld.long 0x00 18. " FTM0TRG2SRC ,FlexTimer 0 hardware trigger 2 source select" "FTM0_FLT0 pin,XBARA output 34" bitfld.long 0x00 17. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB0 channel 1 output trigger,FTM1 channel match" textline " " bitfld.long 0x00 16. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "CMP0 output,FTM1 channel match" bitfld.long 0x00 12. " FTM3FLT0 ,FTM3 fault 0 select" "0 FTM3_FLT0 pin,CMP0 out" bitfld.long 0x00 8. " FTM2FLT0 ,FTM2 fault 0 select" "FTM2_FLT0 pin,CMP0 out" textline " " bitfld.long 0x00 4. " FTM1FLT0 ,FTM1 fault 0 select" "FTM1_FLT0 pin,CMP0 out" bitfld.long 0x00 3. " FTM0FLT3 ,Selects the source of FTM0 fault 3" "FTM0_FLT3 pin,XBARA output 49" bitfld.long 0x00 2. " FTM0FLT2 ,FTM0 fault 2 select" "FTM0_FLT2 pin,CMP2 out" textline " " bitfld.long 0x00 1. " FTM0FLT1 ,FTM0 fault 1 select" "FTM0_FLT1 pin,CMP1 out" bitfld.long 0x00 0. " FTM0FLT0 ,FTM0 fault 0 select" "FTM0_FLT0 pin,CMP0 out" line.long 0x04 "SOPT5,System Options Register 5" bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..." bitfld.long 0x04 4.--5. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX-FTM1_CH0,UART1_TX-FTM2_CH0,?..." bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX,CMP0,CMP1,?..." textline " " bitfld.long 0x04 0.--1. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX,UART0_TX-FTM1_CH0,UART0_TX-FTM2_CH0,?..." group.long 0x18++0x0B line.long 0x00 "SOPT7,System Options Register 7" bitfld.long 0x00 30.--31. " HSADC1BALTTRGEN ,HSADC1B alternate trigger enable" "XBARA output 43,PDB0 channel 1 trigger,Alternate trigger,Alternate trigger" bitfld.long 0x00 24.--27. " HSADC1BTRGSEL ,HSADC1B trigger select" "PDB0_EXTRG,High speed comparator 0,High speed comparator 1,High speed comparator 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,XBARA output 38,,Low-power timer trigger,?..." bitfld.long 0x00 22.--23. " HSADC1AALTTRGEN ,HSADC1A alternate trigger enable" "XBARA output 42,PDB1 channel 1 trigger,Alternate trigger,Alternate trigger" textline " " bitfld.long 0x00 16.--19. " HSADC1ATRGSEL ,HSADC1A trigger select" ",High speed comparator 0,High speed comparator 1,High speed comparator 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,XBARA output 41,,Low-power timer trigger,?..." bitfld.long 0x00 14.--15. " HSADC0BALTTRGEN ,HSADC0B alternate trigger enable" "XBARA output 13,PDB0 channel 0 trigger,Alternate trigger,Alternate trigger" bitfld.long 0x00 8.--11. " HSADC0BTRGSEL ,HSADC0B trigger select" ",High speed comparator 0,High speed comparator 1,High speed comparator 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,XBARA output 41,,Low-power timer trigger,?..." textline " " bitfld.long 0x00 6.--7. " HSADC0AALTTRGEN ,HSADC0A alternate trigger enable" "XBARA output 12,PDB0 channel 0 trigger,Alternate trigger,Alternate trigger" bitfld.long 0x00 0.--3. " HSADC0ATRGSEL ,HSADC0A trigger select" "PDB0_EXTRG,High speed comparator 0,High speed comparator 1,High speed comparator 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,XBARA output 38,,Low-power timer trigger,?..." line.long 0x04 "SOPT8,System Options Register 8" bitfld.long 0x04 31. " FTM3OCH7SRC ,FTM3 channel 7 output source" "Normal,Modulated" bitfld.long 0x04 30. " FTM3OCH6SRC ,FTM3 channel 6 output source" "Normal,Modulated" bitfld.long 0x04 29. " FTM3OCH5SRC ,FTM3 channel 5 output source" "Normal,Modulated" textline " " bitfld.long 0x04 28. " FTM3OCH4SRC ,FTM3 channel 4 output source" "Normal,Modulated" bitfld.long 0x04 27. " FTM3OCH3SRC ,FTM3 channel 3 output source" "Normal,Modulated" bitfld.long 0x04 26. " FTM3OCH2SRC ,FTM3 channel 2 output source" "Normal,Modulated" textline " " bitfld.long 0x04 25. " FTM3OCH1SRC ,FTM3 channel 1 output source" "Normal,Modulated" bitfld.long 0x04 24. " FTM3OCH0SRC ,FTM3 channel 0 output source" "Normal,Modulated" bitfld.long 0x04 23. " FTM0OCH7SRC ,FTM0 channel 7 output source" "Normal,Modulated" textline " " bitfld.long 0x04 22. " FTM0OCH6SRC ,FTM0 channel 6 output source" "Normal,Modulated" bitfld.long 0x04 21. " FTM0OCH5SRC ,FTM0 channel 5 output source" "Normal,Modulated" bitfld.long 0x04 20. " FTM0OCH4SRC ,FTM0 channel 4 output source" "Normal,Modulated" textline " " bitfld.long 0x04 19. " FTM0OCH3SRC ,FTM0 channel 3 output source" "Normal,Modulated" bitfld.long 0x04 18. " FTM0OCH2SRC ,FTM0 channel 2 output source" "Normal,Modulated" bitfld.long 0x04 17. " FTM0OCH1SRC ,FTM0 channel 1 output source" "Normal,Modulated" textline " " bitfld.long 0x04 16. " FTM0OCH0SRC ,FTM0 channel 0 output source" "Normal,Modulated" bitfld.long 0x04 9. " FTM3CFSEL ,Carrier frequency selection for FTM3 output channel" "FTM1_CH1,LPTMR0" bitfld.long 0x04 8. " FTM0CFSEL ,Carrier frequency selection for FTM0 output channel" "FTM1_CH1,LPTMR0" textline " " bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,Assert TRIG0 to FTM3" bitfld.long 0x04 2. " FTM2SYNCBIT ,FTM2 hardware trigger 0 software synchronization" "No effect,Assert TRIG0 to FTM3" bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM1 hardware trigger 0 software synchronization" "No effect,Assert TRIG0 to FTM3" textline " " bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM0 hardware trigger 0 software synchronization" "No effect,Assert TRIG0 to FTM3" line.long 0x08 "SOPT9,System Options Register 9" bitfld.long 0x08 30.--31. " FTM3CLKSEL ,FlexTimer 3 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." bitfld.long 0x08 28.--29. " FTM2CLKSEL ,FlexTimer 2 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." bitfld.long 0x08 26.--27. " FTM1CLKSEL ,FlexTimer 1 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." textline " " bitfld.long 0x08 24.--25. " FTM0CLKSEL ,FlexTimer 0 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." bitfld.long 0x08 10. " FTM2ICH1SRC ,FTM2 channel 1 input capture source select" "FTM2_CH1 signal,Exclusive OR" bitfld.long 0x08 8.--9. " FTM2ICH0SRC ,FTM2 channel 0 input capture source select" "FTM2_CH0 signal,CMP0 output,CMP1 output,?..." textline " " bitfld.long 0x08 6. " FTM1ICH1SRC ,FTM1 channel 1 input capture source select" "FTM1_CH1 signal,Exclusive OR" bitfld.long 0x08 4.--5. " FTM1ICH0SRC ,FTM1 channel 0 input capture source select" "FTM1_CH0 signal,CMP0 output,CMP1 output,?..." rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis family ID" ",,,,,KV5x series,?..." bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",,,,,,KVx6 Subfamily,,KVx8 Subfamily,?..." bitfld.long 0x00 20.--23. " SERIERID ,Kinetis series ID" ",,,,,,Kinetis V series,?..." textline " " bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--11. " DIEID ,Device die number" ",,,KV5x,?..." bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,,,,100-pin,,144-pin,?..." group.long 0x28++0x1B line.long 0x00 "SCGC1,System Clock Gating Control Register 1" bitfld.long 0x00 27. " PWM1_SM3 ,PWM1 submodule 3 clock gate control" "Disabled,Enabled" bitfld.long 0x00 26. " PWM1_SM2 ,PWM1 submodule 2 clock gate control" "Disabled,Enabled" bitfld.long 0x00 25. " PWM1_SM1 ,PWM1 submodule 1 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PWM1_SM0 ,PWM1 submodule 0 clock gate control" "Disabled,Enabled" bitfld.long 0x00 11. " UART5 ,UART5 clock gate control" "Disabled,Enabled" bitfld.long 0x00 10. " UART4 ,UART4 clock gate control" "Disabled,Enabled" line.long 0x04 "SCGC2,System Clock Gating Control Register 2" bitfld.long 0x04 28. " HSADC1 ,HSADC1 clock gate control" "Disabled,Enabled" bitfld.long 0x04 0. " ENET ,ENET clock gate control" "Disabled,Enabled" line.long 0x08 "SCGC3,System Clock Gating Control Register 3" bitfld.long 0x08 12. " SPI2 ,SPI2 clock gate control" "Disabled,Enabled" bitfld.long 0x08 4. " FLEXCAN2 ,FlexCAN2 clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " TRNG ,TRNG clock gate control" "Disabled,Enabled" line.long 0x0C "SCGC4,System Clock Gating Control Register 4" bitfld.long 0x0C 27. " PWM0_SM3 ,PWM0 submodule 3 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 26. " PWM0_SM2 ,PWM0 submodule 2 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 25. " PWM0_SM1 ,PWM0 submodule 1 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x0C 24. " PWM0_SM0 ,PWM0 submodule 0 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 19. " CMP ,Comparator clock gate control" "Disabled,Enabled" bitfld.long 0x0C 13. " UART3 ,UART3 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " UART2 ,UART2 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " I2C1 ,I2C1 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 6. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled" bitfld.long 0x0C 1. " EWM ,EWM clock gate control" "Disabled,Enabled" line.long 0x10 "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x10 28. " HSADC0 ,HSADC0 clock gate control" "Disabled,Enabled" bitfld.long 0x10 27. " AOI ,AOI clock gate control" "Disabled,Enabled" bitfld.long 0x10 26. " XBARB ,XBARB clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " XBARA ,XBARA clock gate control" "Disabled,Enabled" bitfld.long 0x10 21. " ENC ,This bit controls the clock gate to the ENC module" "Disabled,Enabled" bitfld.long 0x10 13. " PORTE ,Port E clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " PORTD ,Port D clock gate control" "Disabled,Enabled" bitfld.long 0x10 11. " PORTC ,Port C clock gate control" "Disabled,Enabled" bitfld.long 0x10 10. " PORTB ,Port B clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " PORTA ,Port A clock gate control" "Disabled,Enabled" bitfld.long 0x10 0. " LPTMR ,Low power timer access control" "Disabled,Enabled" line.long 0x14 "SCGC6,System Clock Gating Control Register 6" bitfld.long 0x14 31. " DAC0 ,DAC0 clock gate control" "Disabled,Enabled" bitfld.long 0x14 27. " ADC0 ,ADC0 clock gate control" "Disabled,Enabled" bitfld.long 0x14 26. " FTM2 ,FTM2 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x14 25. " FTM1 ,FTM1 clock gate control" "Disabled,Enabled" bitfld.long 0x14 24. " FTM0 ,FTM0 clock gate control" "Disabled,Enabled" bitfld.long 0x14 23. " PIT ,PIT clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x14 22. " PDB0 ,PDB Clock Gate Control" "Disabled,Enabled" bitfld.long 0x14 18. " CRC ,CRC clock gate control" "Disabled,Enabled" bitfld.long 0x14 17. " PDB1 ,PDB1 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x14 13. " SPI1 ,SPI1 Clock Gate Control" "Disabled,Enabled" bitfld.long 0x14 12. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled" bitfld.long 0x14 6. " FTM3 ,FTM3 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " FLEXCAN1 ,FLEXCAN1 clock gate control" "Disabled,Enabled" bitfld.long 0x14 4. " FLEXCAN0 ,FLEXCAN0 clock gate control" "Disabled,Enabled" bitfld.long 0x14 1. " DMAMUX ,DMA Mux clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" line.long 0x18 "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x18 8. " DMA ,DMA clock gate control" "Disabled,Enabled" bitfld.long 0x18 2. " SMPU ,SMPU clock gate control" "Disabled,Enabled" bitfld.long 0x18 0. " FLEXBUS ,FLEXBUS clock gate control" "Disabled,Enabled" if (((per.b(ad:0x4007E000+0x01))&0x60)==0x40) rgroup.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 20.--23. " OUTDIV3 ,Clock 3 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" textline " " bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" else group.long 0x44++0x03 line.long 0x00 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x00 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 20.--23. " OUTDIV3 ,Clock 3 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" textline " " bitfld.long 0x00 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" endif group.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,,,,,,,,,512 KB,,1024 KB,?..." bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "Disabled,Enabled" bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes" rgroup.long 0x50++0x13 line.long 0x00 "FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 0x01 " MAXADDR ,Max address block" line.long 0x04 "UIDH,Unique Identification Register High" line.long 0x08 "UIDMH,Unique Identification Register Mid-High" line.long 0x0C "UIDML,Unique Identification Register Mid Low" line.long 0x10 "UIDL,Unique Identification Register Low" group.long 0x68++0x0B line.long 0x00 "CLKDIV4,System Clock Divider Register 4" bitfld.long 0x00 28. " TRACEDIVEN ,Debug trace divider control" "Disabled,Enabled" bitfld.long 0x00 1.--3. " TRACEDIV ,Trace clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " TRACEFRAC ,Trace clock divider fraction" "0,1" line.long 0x04 "MISCTRL0,Miscellaneous Control Register 0" bitfld.long 0x04 18.--19. " DACTRIGSRC ,DAC0 hardware trigger input source" "XBARA output 15,PDB0/PDB1 interval trigger 0,PDB0 interval trigger 0,PDB1 interval trigger 0" bitfld.long 0x04 16. " EWMINSRC ,EWM_IN source" "XBARA output 58,EWM_IN pin" bitfld.long 0x04 14.--15. " CMPWIN3SRC ,CMP sample/window input 3 source" "XBARA output 19,PDB0/PDB1 pluseout channel 3,PDB0 pluseout channel 3,PDB1 pluseout channel 3" textline " " bitfld.long 0x04 12.--13. " CMPWIN2SRC ,CMP sample/window input 2 source" "XBARA output 18,PDB0/PDB1 pluseout channel 2,PDB0 pluseout channel 2,PDB1 pluseout channel 2" bitfld.long 0x04 10.--11. " CMPWIN1SRC ,CMP sample/window input 1 source" "XBARA output 17,PDB0/PDB1 pluseout channel 1,PDB0 pluseout channel 1,PDB1 pluseout channel 1" bitfld.long 0x04 8.--9. " CMPWIN0SRC ,CMP sample/window input 0 source" "XBARA output 16,PDB0/PDB1 pluseout channel 0,PDB0 pluseout channel 0,PDB1 pluseout channel 0" line.long 0x08 "MISCTRL1,Miscellaneous Control Register 1" bitfld.long 0x08 23. " SYNCCMP3SAMPLEWIN ,Synchronize XBARA's output for CMP3's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 22. " SYNCCMP2SAMPLEWIN ,Synchronize XBARA's output for CMP2's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 21. " SYNCCMP1SAMPLEWIN ,Synchronize XBARA's output for CMP1's sample/window input with flash/slow clock" "Disabled,Enabled" textline " " bitfld.long 0x08 20. " SYNCCMP0SAMPLEWIN ,Synchronize XBARA's output for CMP0's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 17. " SYNCEWMIN ,Synchronize XBARA's output for EWM's ewm_in with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 16. " SYNCDACHWTRIG ,Synchronize XBARA's output for DAC hardware trigger with flash/slow clock" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " SYNCXBARBPITTRIG1 ,Synchronize XBARB's input PIT trigger 1 with fast clock" "Disabled,Enabled" bitfld.long 0x08 12. " SYNCXBARBPITTRIG0 ,Synchronize XBARB's input PIT trigger 0 with fast clock" "Disabled,Enabled" bitfld.long 0x08 11. " SYNCXBARAPITTRIG3 ,Synchronize XBARA's input PIT trigger 3 with fast clock" "Disabled,Enabled" textline " " bitfld.long 0x08 10. " SYNCXBARAPITTRIG2 ,Synchronize XBARA's input PIT trigger 2 with fast clock" "Disabled,Enabled" bitfld.long 0x08 9. " SYNCXBARAPITTRIG1 ,Synchronize XBARA's Input PIT trigger 1 with fast clock" "Disabled,Enabled" bitfld.long 0x08 8. " SYNCXBARAPITTRIG0 ,Synchronize XBARA's input PIT trigger 0 with fast clock" "Disabled,Enabled" group.long 0x100++0x0B line.long 0x00 "WDOGC,WDOG Control Register" bitfld.long 0x00 1. " WDOGCLKS ,WDOG clock select" "1 kHz LPO clock,MCGIRCLK" line.long 0x04 "PWRC,System Clock Divider Register 4" rbitfld.long 0x04 16. " SRPWROK ,Nanoedge PMC status" "Not ready,OK" bitfld.long 0x04 9. " SRPWRRDY ,Nanoedge PMC Power ready" "Not ready,Ready" bitfld.long 0x04 8. " SRPWRDETEN ,Nanoedge PMC power dectect enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6.--7. " SR12STDBY ,Nanoedge regulator 1.2 V supply standby control" "Normal,Standby,Normal protected,Standby protected" bitfld.long 0x04 2.--3. " SR27STDBY ,Nanoedge regulator 1.2 V supply standby control" "Normal,Standby,Normal protected,Standby protected" bitfld.long 0x04 0.--1. " SRPDN ,Nanoedge regulator 2.7 V and 1.2 V supply standby control" "Normal,Standby,Normal protected,Standby protected" line.long 0x08 "ADCOPT,ADC Additional Option Register" bitfld.long 0x08 26. " HSADCSTOPEN ,Enable HSADCs in STOP mode" "Stopsin system,Can be enabled" rbitfld.long 0x08 25. " HSADCIRCLK ,HSADC clock status" "Core/System clock,MCGIRCLK" bitfld.long 0x08 22.--23. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "XBARA output 39,PDB0 channel1 trigger,PDB1 channel0 trigger,ADC0TRGSEL" textline " " bitfld.long 0x08 20. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x08 16.--19. " ADC0TRGSEL ,ADC0 trigger select" "PDB0_EXTRG,High speed comparator 0,High speed comparator 1,High speed comparator 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,XBARA output 38,,Low-power timer trigger,?..." width 0xb tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "No reset,Reset" bitfld.byte 0x00 6. " PIN ,External reset pin" "No reset,Reset" bitfld.byte 0x00 5. " WDOG ,Watchdog" "No reset,Reset" newline sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "No reset,Reset" endif newline bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "No reset,Reset" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "No reset,Reset" bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "No reset,Reset" line.byte 0x01 "SRS1,System Reset Status Register 1" bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24")&&!cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10*") bitfld.byte 0x01 4. " EZPT ,EzPort reset" "No reset,Reset" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "No reset,Reset" else bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "No reset,Reset" endif bitfld.byte 0x01 2. " SW ,Software" "No reset,Reset" newline bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "No reset,Reset" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "No reset,Reset" group.byte 0x04++0x01 line.byte 0x00 "RPFC,Reset Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All filtering disabled,LPO clock filter enabled" bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All filtering disabled,Bus clock filter enabled,LPO clock filter enabled,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") rgroup.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1. " EZP_MS ,EZP_MS_B pin state" "Negated,Asserted" endif group.byte 0x08++0x01 line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "No reset,Reset" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "No reset,Reset" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV31F128VLH10P") eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "No reset,Reset" eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset" newline eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "No reset,Reset" else eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset" eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "No reset,Reset" endif line.byte 0x01 "SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "No reset,Reset" newline sif !cpuis("MKV30F*")&&!cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") eventfld.byte 0x01 4. " SEZPT ,Sticky EzPort reset" "No reset,Reset" eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset" else eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset" endif newline eventfld.byte 0x01 2. " SSW ,Sticky software" "No reset,Reset" eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "No reset,Reset" eventfld.byte 0x01 0. " SJTAG ,Sticky JTAG generated reset" "No reset,Reset" width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" bitfld.byte 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" sif !cpuis("MKV58F1M0V??24")&&!cpuis("MKV58F512V??24")&&!cpuis("MKV56F1M0V??24")&&!cpuis("MKV58F512??24") newline bitfld.byte 0x00 3. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" endif newline bitfld.byte 0x00 1. " AVLLS ,Allow very low leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High Speed Run mode" rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,,VLLSx,?..." else sif cpuis("MKV31F512*") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High Speed Run mode" else bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,?..." endif rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLSx,VLLSx,?..." endif sif cpuis("MKV58F1M0V??24")||cpuis("MKV56F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "No,Yes" bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif else if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?" bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "Normal mode,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12*") bitfld.byte 0x00 7. " HSRUN ,Current power mode is HSRUN" "No,Yes" bitfld.byte 0x00 6. " VLLS ,Current power mode is VLLS" "No,Yes" bitfld.byte 0x00 5. " LLS ,Current power mode is LLS" "No,Yes" newline bitfld.byte 0x00 4. " VLPS ,Current power mode is VLPS" "No,Yes" bitfld.byte 0x00 3. " VLPW ,Current power mode is VLPW" "No,Yes" bitfld.byte 0x00 2. " VLPR ,Current power mode is VLPR" "No,Yes" newline bitfld.byte 0x00 1. " STOP ,Current power mode is STOP" "No,Yes" bitfld.byte 0x00 0. " RUN ,Current power mode is RUN" "No,Yes" endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.long 0x00++0x03 line.long 0x00 "PCT,Processor Core Type" hexmask.long.word 0x00 16.--31. 1. " PCT ,MCM design supports the ARM Cortex M7 core" hexmask.long.word 0x00 0.--15. 1. " PLREV ,Platform revision" group.long 0x0C++0x07 line.long 0x00 "CR,Platform Control Register" bitfld.long 0x00 27. " AHBSPRI ,AHB Slave interface priority" "SW over AHBS,AHBS over SW" line.long 0x04 "ISSR,Interrupt Status Register" bitfld.long 0x04 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" textline " " rbitfld.long 0x4 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x4 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" textline " " rbitfld.long 0x4 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x4 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" textline " " rbitfld.long 0x4 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x4 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" group.long 0x34++0x03 line.long 0x00 "CPO,Compute Operation Control Register" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Cleared,Compute operation" textline " " rgroup.long 0x400++0x03 line.long 0x00 "LMEM0,Local Memory General Descriptor Register" bitfld.long 0x00 31. " LMEM_VALID ,Defines whether the local memory is present" "Not present,Present" bitfld.long 0x00 24.--27. " LMEM_SIZE ,Defines the local memory size" ",,,,8 KB,16 KB,,64 KB,?..." bitfld.long 0x00 20.--23. " LMEM_WAYS ,Defines the ways of set associative" ",,2-way set associative,,4-way set associative,?..." bitfld.long 0x00 17.--19. " LMEM_WIDTH ,Defines the local memory bit width" ",,32-bits,64-bits,?..." bitfld.long 0x00 13.--15. " LMEM_TYPE ,Defines the type of local memory" "ITCM,DTCM,Instruction Cache,Data Cache,?..." rgroup.long 0x404++0x03 line.long 0x00 "LMEM1,Local Memory General Descriptor Register" bitfld.long 0x00 31. " LMEM_VALID ,Defines whether the local memory is present" "Not present,Present" bitfld.long 0x00 24.--27. " LMEM_SIZE ,Defines the local memory size" ",,,,8 KB,16 KB,,64 KB,?..." bitfld.long 0x00 20.--23. " LMEM_WAYS ,Defines the ways of set associative" ",,2-way set associative,,4-way set associative,?..." bitfld.long 0x00 17.--19. " LMEM_WIDTH ,Defines the local memory bit width" ",,32-bits,64-bits,?..." bitfld.long 0x00 13.--15. " LMEM_TYPE ,Defines the type of local memory" "ITCM,DTCM,Instruction Cache,Data Cache,?..." rgroup.long 0x408++0x03 line.long 0x00 "LMEM2,Local Memory General Descriptor Register" bitfld.long 0x00 31. " LMEM_VALID ,Defines whether the local memory is present" "Not present,Present" bitfld.long 0x00 24.--27. " LMEM_SIZE ,Defines the local memory size" ",,,,8 KB,16 KB,,64 KB,?..." bitfld.long 0x00 20.--23. " LMEM_WAYS ,Defines the ways of set associative" ",,2-way set associative,,4-way set associative,?..." bitfld.long 0x00 17.--19. " LMEM_WIDTH ,Defines the local memory bit width" ",,32-bits,64-bits,?..." bitfld.long 0x00 13.--15. " LMEM_TYPE ,Defines the type of local memory" "ITCM,DTCM,Instruction Cache,Data Cache,?..." rgroup.long 0x40C++0x03 line.long 0x00 "LMEM3,Local Memory General Descriptor Register" bitfld.long 0x00 31. " LMEM_VALID ,Defines whether the local memory is present" "Not present,Present" bitfld.long 0x00 24.--27. " LMEM_SIZE ,Defines the local memory size" ",,,,8 KB,16 KB,,64 KB,?..." bitfld.long 0x00 20.--23. " LMEM_WAYS ,Defines the ways of set associative" ",,2-way set associative,,4-way set associative,?..." bitfld.long 0x00 17.--19. " LMEM_WIDTH ,Defines the local memory bit width" ",,32-bits,64-bits,?..." bitfld.long 0x00 13.--15. " LMEM_TYPE ,Defines the type of local memory" "ITCM,DTCM,Instruction Cache,Data Cache,?..." rgroup.long 0x410++0x03 line.long 0x00 "LMEM4,Local Memory General Descriptor Register" bitfld.long 0x00 31. " LMEM_VALID ,Defines whether the local memory is present" "Not present,Present" bitfld.long 0x00 24.--27. " LMEM_SIZE ,Defines the local memory size" ",,,,8 KB,16 KB,,64 KB,?..." bitfld.long 0x00 20.--23. " LMEM_WAYS ,Defines the ways of set associative" ",,2-way set associative,,4-way set associative,?..." bitfld.long 0x00 17.--19. " LMEM_WIDTH ,Defines the local memory bit width" ",,32-bits,64-bits,?..." bitfld.long 0x00 13.--15. " LMEM_TYPE ,Defines the type of local memory" "ITCM,DTCM,Instruction Cache,Data Cache,?..." width 0xb tree.end tree "MSCM (Miscellaneous System Control Module)" base ad:0x40001000 width 13. rgroup.long 0x00++0x0F line.long 0x00 "CPXTYPE,Processor X Type Register" hexmask.long.tbyte 0x00 8.--31. 1. " PERSONALITY ,Processor X personality" hexmask.long.byte 0x00 0.--7. 1. " RYPZ ,Processor X revision" line.long 0x04 "CPXNUM,Processor X Number Register" sif cpuis("S32MTV") bitfld.long 0x04 0. " CPN ,Processor X number" "0,?..." else bitfld.long 0x04 0. " CPN ,Processor X number" "0,1" endif line.long 0x08 "CPXMASTER,Processor X Master Register" bitfld.long 0x08 0.--5. " PPMN ,Processor X physical port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "CPXCOUNT,Processor X Count Register" sif cpuis("S32MTV") bitfld.long 0x0C 0.--1. " PCNT ,Processor count" "Single,?..." elif cpuis("K32W*") bitfld.long 0x0C 0.--1. " PCNT ,Processor count" ",Dual,?..." else bitfld.long 0x0C 0.--1. " PCNT ,Processor count" "Single,Dual,?..." endif sif (cpuis("S32MTV")||cpuis("K32W*")) rgroup.long 0x10++0x03 line.long 0x00 "CPXCFG0,Processor X Configuration 0 Register" hexmask.long.byte 0x00 24.--31. 1. " ICSZ ,Level 1 instruction cache size" hexmask.long.byte 0x00 16.--23. 1. " ICWY ,Level 1 instruction cache ways" textline " " hexmask.long.byte 0x00 8.--15. 1. " DCSZ ,Level 1 data cache size" hexmask.long.byte 0x00 0.--7. 1. " DCWY ,Level 1 data cache ways" endif rgroup.long 0x14++0x03 line.long 0x00 "CPXCFG1,Processor X Configuration 1 Register" hexmask.long.byte 0x00 24.--31. 1. " L2SZ ,Level 2 cache size" hexmask.long.byte 0x00 16.--23. 1. " L2WY ,Level 2 cache ways" sif (cpuis("K32W*")||cpuis("S32MTV")) rgroup.long 0x18++0x03 line.long 0x00 "CPXCFG2,Processor X Configuration 2 Register" hexmask.long.byte 0x00 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size" hexmask.long.byte 0x00 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size" endif rgroup.long 0x1C++0x13 line.long 0x00 "CPXCFG3,Processor X Configuration 3 Register" bitfld.long 0x00 8.--9. " SBP ,System bus ports" "0,1,2,3" bitfld.long 0x00 6. " BB ,Bit banding" "Not supported,Supported" bitfld.long 0x00 5. " CMP ,Core memory protection unit" "Not included,Included" textline " " bitfld.long 0x00 4. " TZ ,Trust zone" "Not included,Included" bitfld.long 0x00 3. " MMU ,Memory management unit" "Not included,Included" bitfld.long 0x00 2. " JAZ ,Jazelle" "Not included,Included" textline " " bitfld.long 0x00 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included" bitfld.long 0x00 0. " FPU ,Floating point unit" "Not included,Included" line.long 0x04 "CP0TYPE,Processor 0 Type Register" hexmask.long.tbyte 0x04 8.--31. 1. " PERSONALITY ,Processor 0 personality" hexmask.long.byte 0x04 0.--7. 1. " RYPZ ,Processor 0 revision" line.long 0x08 "CP0NUM,Processor 0 Number Register" sif cpuis("S32MTV") bitfld.long 0x08 0. " CPN ,Processor X number" "0,?..." else bitfld.long 0x08 0. " CPN ,Processor X number" "0,1" endif line.long 0x0C "CP0MASTER,Processor 0 Master Register" bitfld.long 0x0C 0.--5. " PPMN ,Processor 0 physical port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "CP0COUNT,Processor 0 Count Register" sif cpuis("S32MTV") bitfld.long 0x10 0.--1. " PCNT ,Processor count" "Single,?..." elif cpuis("K32W*") bitfld.long 0x10 0.--1. " PCNT ,Processor count" ",Dual,?..." else bitfld.long 0x10 0.--1. " PCNT ,Processor count" "Single,Dual,?..." endif sif (cpuis("S32MTV")||cpuis("K32W*")) rgroup.long 0x30++0x03 line.long 0x00 "CP0CFG0,Processor 0 Configuration 0 Register" hexmask.long.byte 0x00 24.--31. 1. " ICSZ ,Level 1 instruction cache size" hexmask.long.byte 0x00 16.--23. 1. " ICWY ,Level 1 instruction cache ways" textline " " hexmask.long.byte 0x00 8.--15. 1. " DCSZ ,Level 1 data cache size" hexmask.long.byte 0x00 0.--7. 1. " DCWY ,Level 1 data cache ways" endif rgroup.long 0x34++0x03 line.long 0x00 "CP0CFG1,Processor 0 Configuration 1 Register" hexmask.long.byte 0x00 24.--31. 1. " L2SZ ,Level 2 cache size" hexmask.long.byte 0x00 16.--23. 1. " L2WY ,Level 2 cache ways" sif (cpuis("K32W*")||cpuis("S32MTV")) rgroup.long 0x38++0x03 line.long 0x00 "CP0CFG2,Processor X Configuration 2 Register" hexmask.long.byte 0x00 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size" hexmask.long.byte 0x00 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size" endif rgroup.long 0x3C++0x03 line.long 0x00 "CP0CFG3,Processor 0 Configuration 3 Register" bitfld.long 0x00 8.--9. " SBP ,System bus ports" "0,1,2,3" bitfld.long 0x00 6. " BB ,Bit banding" "Not supported,Supported" bitfld.long 0x00 5. " CMP ,Core memory protection unit" "Not included,Included" textline " " bitfld.long 0x00 4. " TZ ,Trust zone" "Not included,Included" bitfld.long 0x00 3. " MMU ,Memory management unit" "Not included,Included" bitfld.long 0x00 2. " JAZ ,Jazelle" "Not included,Included" textline " " bitfld.long 0x00 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included" bitfld.long 0x00 0. " FPU ,Floating point unit" "Not included,Included" sif (!cpuis("S32MTV")) rgroup.long 0x40++0x0F line.long 0x00 "CP1TYPE,Processor 1 Type Register" hexmask.long.tbyte 0x00 8.--31. 1. " PERSONALITY ,Processor 1 personality" hexmask.long.byte 0x00 0.--7. 1. " RYPZ ,Processor 1 revision" line.long 0x04 "CP1NUM,Processor 1 Number Register" bitfld.long 0x04 0. " CPN ,Processor 1 number" "0,1" line.long 0x08 "CP1MASTER,Processor 1 Master Register" bitfld.long 0x08 0.--5. " PPN ,Processor 1 physical port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "CP1COUNT,Processor 1 Count Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x0C 0.--1. " PCNT ,Processor count" ",Dual,?..." else bitfld.long 0x0C 0.--1. " PCNT ,Processor count" "Single,Dual,?..." endif sif cpuis("K32W0?2S1M*") rgroup.long 0x50++0x03 line.long 0x00 "CP1CFG0,Processor 1 Configuration 0 Register" hexmask.long.byte 0x00 24.--31. 1. " ICSZ ,Level 1 instruction cache size" hexmask.long.byte 0x00 16.--23. 1. " ICWY ,Level 1 instruction cache ways" hexmask.long.byte 0x00 8.--15. 1. " DCSZ ,Level 1 data cache size" hexmask.long.byte 0x00 0.--7. 1. " DCWY ,Level 1 data cache ways" endif rgroup.long 0x54++0x03 line.long 0x00 "CP1CFG1,Processor 1 Configuration 1 Register" hexmask.long.byte 0x00 24.--31. 1. " L2SZ ,Level 2 cache size" hexmask.long.byte 0x00 16.--23. 1. " L2WY ,Level 2 cache ways" sif cpuis("K32W0?2S1M*") rgroup.long 0x58++0x03 line.long 0x00 "CP1CFG2,Processor 1 Configuration 2 Register" hexmask.long.byte 0x00 24.--31. 1. " TMLSZ ,Tightly-coupled memory lower size" hexmask.long.byte 0x00 8.--15. 1. " TMUSZ ,Tightly-coupled memory upper size" endif rgroup.long 0x5C++0x03 line.long 0x00 "CP1CFG3,Processor 1 Configuration 3 Register" bitfld.long 0x00 8.--9. " SBP ,System bus ports" "0,1,2,3" bitfld.long 0x00 6. " BB ,Bit banding" "Not supported,Supported" bitfld.long 0x00 5. " CMP ,Core memory protection unit" "Not included,Included" textline " " bitfld.long 0x00 4. " TZ ,Trust zone" "Not included,Included" bitfld.long 0x00 3. " MMU ,Memory management unit" "Not included,Included" bitfld.long 0x00 2. " JAZ ,Jazelle" "Not included,Included" textline " " bitfld.long 0x00 1. " SIMD ,SIMD/NEON instruction support" "Not included,Included" bitfld.long 0x00 0. " FPU ,Floating point unit" "Not included,Included" endif sif cpuis("K32W0?2S1M*") group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM0,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" bitfld.long 0x00 8.--11. " OCM2 ,OCMEM control field 2" "Flash cache,Instruction cache,Data cache,Clear flash cache,?..." bitfld.long 0x00 4.--7. " OCM1 ,OCMEM control field 1" "Enabled,Flash cache,Instruction cache,Data cache,Clear flash cache,?..." group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM1,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" bitfld.long 0x00 8.--11. " OCM2 ,OCMEM control field 2" "Flash cache,Instruction cache,Data cache,Clear flash cache,?..." bitfld.long 0x00 4.--7. " OCM1 ,OCMEM control field 1" "Enabled,Flash cache,Instruction cache,Data cache,Clear flash cache,?..." group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM2,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" bitfld.long 0x00 8.--11. " OCM2 ,OCMEM control field 2" "Flash cache,Instruction cache,Data cache,Clear flash cache,?..." bitfld.long 0x00 4.--7. " OCM1 ,OCMEM control field 1" "Enabled,Flash cache,Instruction cache,Data cache,Clear flash cache,?..." group.long 0x40C++0x03 line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM3,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " rbitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" bitfld.long 0x00 8.--11. " OCM2 ,OCMEM control field 2" "Flash cache,Instruction cache,Data cache,Clear flash cache,?..." bitfld.long 0x00 4.--7. " OCM1 ,OCMEM control field 1" "Enabled,Flash cache,Instruction cache,Data cache,Clear flash cache,?..." elif (cpuis("S32MTV")) group.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM0,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " bitfld.long 0x00 4.--5. " OCM1 ,OCMEM control field 1" "Disabled,Disabled,Instruction enabled,Instruction/data enabled" group.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM1,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " bitfld.long 0x00 4.--5. " OCM1 ,OCMEM control field 1" "Disabled,Disabled,Instruction enabled,Instruction/data enabled" group.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" rbitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" rbitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" rbitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM2,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" textline " " rbitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 16. " RO ,READ ONLY" "Allowed,Ignored" rbitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." else rgroup.long 0x400++0x03 line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 30. " FMT ,Format" "Local,Global" bitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" textline " " bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM0,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " bitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" rgroup.long 0x404++0x03 line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 30. " FMT ,Format" "Local,Global" bitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" textline " " bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM1,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " bitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" rgroup.long 0x408++0x03 line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register" bitfld.long 0x00 31. " V ,OCMEM valid bit" "Not present,Present" bitfld.long 0x00 30. " FMT ,Format" "Local,Global" bitfld.long 0x00 28. " OCMSZH ,OCMEM size hole" "Power-of-2,Not power-of-2" textline " " bitfld.long 0x00 24.--27. " OCMSZ ,OCMEM size" "No OCMEM2,,,4 KB,8 KB,16K B,32 KB,64 KB,128 KB,256 KB,512 KB,1024 KB,2048 KB,4096 KB,8192 KB,16384 KB" bitfld.long 0x00 17.--19. " OCMW ,OCMEM datapath width" ",,32-bits,64-bits,128-bits,256-bits,?..." bitfld.long 0x00 13.--15. " OCMT ,OCMEM type" "System RAM,Graphics RAM,,ROM,Program flash,Data flash,EEE,?..." textline " " bitfld.long 0x00 12. " OCMPU ,OCMEM memory protection unit" "Not protected,Protected" endif width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip point,High trip point,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Clear" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip point,Mid 1 trip point,Mid 2 trip point,High trip point" line.byte 0x02 "REGSC,Regulator Status And Control register" bitfld.byte 0x02 4. " BGEN ,Bandgap enable VLPx operation" "Disabled,Enabled" eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Normal,Isolated" rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stopped,Running" newline bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" sif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")) group.byte 0x0B++0x00 line.byte 0x00 "HVDSC1,High Voltage Detect Status And Control 1 register" rbitfld.byte 0x00 7. " HVDF ,High-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " HVDACK ,High-voltage detect acknowledge" "No effect,Clear" bitfld.byte 0x00 5. " HVDIE ,High-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " HVDRE ,High-voltage detect reset enable" "Not forced,Forced" bitfld.byte 0x00 0. " HVDV ,High-voltage detect voltage select" "Low,High" endif width 0x0B tree.end tree "LLWU (Low-Leakage Wakeup Unit)" base ad:0x4007C000 width 7. group.byte 0x00++0x0C line.byte 0x00 "PE1,LLWU Pin Enable 1 register" bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x01 "PE2,LLWU Pin Enable 2 register" bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x02 "PE3,LLWU Pin Enable 3 register" bitfld.byte 0x02 6.--7. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x02 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x02 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x02 0.--1. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x03 "PE4,LLWU Pin Enable 4 register" bitfld.byte 0x03 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x03 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x03 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x03 0.--1. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x04 "PE5,LLWU Pin Enable 5 register" bitfld.byte 0x04 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x04 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x04 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x04 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x05 "PE6,LLWU Pin Enable 6 register" bitfld.byte 0x05 6.--7. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x05 4.--5. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x05 2.--3. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x05 0.--1. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x06 "PE7,LLWU Pin Enable 7 register" bitfld.byte 0x06 6.--7. " WUPE27 ,Wakeup pin enable for LLWU_P27" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x06 4.--5. " WUPE26 ,Wakeup pin enable for LLWU_P26" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x06 2.--3. " WUPE25 ,Wakeup pin enable for LLWU_P25" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x06 0.--1. " WUPE24 ,Wakeup pin enable for LLWU_P24" "Disabled,Rising edge,Falling edge,Any edge" line.byte 0x07 "PE8,LLWU Pin Enable 8 register" bitfld.byte 0x07 6.--7. " WUPE31 ,Wakeup pin enable for LLWU_P31" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x07 4.--5. " WUPE30 ,Wakeup pin enable for LLWU_P30" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x07 2.--3. " WUPE29 ,Wakeup pin enable for LLWU_P29" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x07 0.--1. " WUPE28 ,Wakeup pin enable for LLWU_P28" "Disabled,Rising edge,Falling edge,Any edge" textline " " line.byte 0x08 "ME,LLWU Module Enable register" bitfld.byte 0x08 7. " WUME7 ,Wakeup module enable for module 7" "Not used,Used" bitfld.byte 0x08 6. " WUME6 ,Wakeup module enable for module 6" "Not used,Used" bitfld.byte 0x08 5. " WUME5 ,Wakeup module enable for module 5" "Not used,Used" textline " " bitfld.byte 0x08 4. " WUME4 ,Wakeup module enable for module 4" "Not used,Used" bitfld.byte 0x08 3. " WUME3 ,Wakeup module enable for module 3" "Not used,Used" bitfld.byte 0x08 2. " WUME2 ,Wakeup module enable for module 2" "Not used,Used" textline " " bitfld.byte 0x08 1. " WUME1 ,Wakeup module enable for module 1" "Not used,Used" bitfld.byte 0x08 0. " WUME0 ,Wakeup module enable for module 0" "Not used,Used" line.byte 0x09 "F1,LLWU Flag 1 register" eventfld.byte 0x09 7. " WUF7 ,Wakeup flag for LLWU_P7" "Not wake-up source,Wake-up source" eventfld.byte 0x09 6. " WUF6 ,Wakeup flag for LLWU_P6" "Not wake-up source,Wake-up source" eventfld.byte 0x09 5. " WUF5 ,Wakeup flag for LLWU_P5" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x09 4. " WUF4 ,Wakeup flag for LLWU_P4" "Not wake-up source,Wake-up source" eventfld.byte 0x09 3. " WUF3 ,Wakeup flag for LLWU_P3" "Not wake-up source,Wake-up source" eventfld.byte 0x09 2. " WUF2 ,Wakeup flag for LLWU_P2" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x09 1. " WUF1 ,Wakeup flag for LLWU_P1" "Not wake-up source,Wake-up source" eventfld.byte 0x09 0. " WUF0 ,Wakeup flag for LLWU_P0" "Not wake-up source,Wake-up source" line.byte 0x0A "F2,LLWU Flag 2 register" eventfld.byte 0x0A 7. " WUF15 ,Wakeup flag for LLWU_P15" "Not wake-up source,Wake-up source" eventfld.byte 0x0A 6. " WUF14 ,Wakeup flag for LLWU_P14" "Not wake-up source,Wake-up source" eventfld.byte 0x0A 5. " WUF13 ,Wakeup flag for LLWU_P13" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0A 4. " WUF12 ,Wakeup flag for LLWU_P12" "Not wake-up source,Wake-up source" eventfld.byte 0x0A 3. " WUF11 ,Wakeup flag for LLWU_P11" "Not wake-up source,Wake-up source" eventfld.byte 0x0A 2. " WUF10 ,Wakeup flag for LLWU_P10" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0A 1. " WUF9 ,Wakeup flag for LLWU_P9" "Not wake-up source,Wake-up source" eventfld.byte 0x0A 0. " WUF8 ,Wakeup flag for LLWU_P8" "Not wake-up source,Wake-up source" line.byte 0x0B "F3,LLWU Flag 3 register" eventfld.byte 0x0B 7. " WUF23 ,Wakeup flag for LLWU_P23" "Not wake-up source,Wake-up source" eventfld.byte 0x0B 6. " WUF22 ,Wakeup flag for LLWU_P22" "Not wake-up source,Wake-up source" eventfld.byte 0x0B 5. " WUF21 ,Wakeup flag for LLWU_P21" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0B 4. " WUF20 ,Wakeup flag for LLWU_P20" "Not wake-up source,Wake-up source" eventfld.byte 0x0B 3. " WUF19 ,Wakeup flag for LLWU_P19" "Not wake-up source,Wake-up source" eventfld.byte 0x0B 2. " WUF18 ,Wakeup flag for LLWU_P18" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0B 1. " WUF17 ,Wakeup flag for LLWU_P17" "Not wake-up source,Wake-up source" eventfld.byte 0x0B 0. " WUF16 ,Wakeup flag for LLWU_P16" "Not wake-up source,Wake-up source" line.byte 0x0C "F4,LLWU Flag 4 register" eventfld.byte 0x0C 7. " WUF31 ,Wakeup flag for LLWU_P31" "Not wake-up source,Wake-up source" eventfld.byte 0x0C 6. " WUF30 ,Wakeup flag for LLWU_P30" "Not wake-up source,Wake-up source" eventfld.byte 0x0C 5. " WUF29 ,Wakeup flag for LLWU_P29" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0C 4. " WUF28 ,Wakeup flag for LLWU_P28" "Not wake-up source,Wake-up source" eventfld.byte 0x0C 3. " WUF27 ,Wakeup flag for LLWU_P27" "Not wake-up source,Wake-up source" eventfld.byte 0x0C 2. " WUF26 ,Wakeup flag for LLWU_P26" "Not wake-up source,Wake-up source" textline " " eventfld.byte 0x0C 1. " WUF25 ,Wakeup flag for LLWU_P25" "Not wake-up source,Wake-up source" eventfld.byte 0x0C 0. " WUF24 ,Wakeup flag for LLWU_P24" "Not wake-up source,Wake-up source" rgroup.byte 0x0D++0x00 line.byte 0x00 "F5,LLWU Flag 5 register" bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not a wakeup source,Wakeup source" textline " " bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not a wakeup source,Wakeup source" textline " " bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not a wakeup source,Wakeup source" textline " " group.byte 0x0E++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 register" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" textline " " bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" line.byte 0x01 "FILT2,LLWU Pin Filter 2 register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "Not a wakeup source,Wakeup source" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" textline " " bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,LLWU_P16,LLWU_P17,LLWU_P18,LLWU_P19,LLWU_P20,LLWU_P21,LLWU_P22,LLWU_P23,LLWU_P24,LLWU_P25,LLWU_P26,LLWU_P27,LLWU_P28,LLWU_P29,LLWU_P30,LLWU_P31" width 0x0B tree.end tree "AXBS (Crossbar Switch)" base ad:0x40004000 width 8. sif cpuis("K32W0?2S1M*") if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." endif group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." textline " " bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." endif group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." textline " " bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." endif group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." textline " " bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." endif group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." textline " " bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." endif group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." textline " " bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x500+0x10))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x600+0x10))&0x80000000)==0x80000000) rgroup.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." if (((per.l(ad:0x40004000+0x700+0x10))&0x80000000)==0x80000000) rgroup.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." else group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "1 or highest,2,3,4,?..." textline " " bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "1 or highest,2,3,4,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "1 or highest,2,3,4,?..." endif group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "W,RO" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." textline " " bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif sif cpuis("K32W0?2S1M*") group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." else group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 bits,After 8 bits,After 16 bits,?..." endif width 0x0B tree.end tree.open "AIPS-Lite (Peripheral Bridge)" tree "AIPS 0" base ad:0x40000000 width 13. group.long 0x00++0x03 line.long 0x00 "AIPS0_MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master 0 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master 0 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master 0 privilege level" "Forced,Not forced" bitfld.long 0x00 26. " MTR1 ,Master 1 trusted for read" "Not trusted,Trusted" newline bitfld.long 0x00 25. " MTW1 ,Master 1 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master 1 privilege level" "Forced,Not forced" bitfld.long 0x00 22. " MTR2 ,Master 2 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master 2 trusted for writes" "Not trusted,Trusted" newline bitfld.long 0x00 20. " MPL2 ,Master 2 privilege level" "Forced,Not forced" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") bitfld.long 0x00 18. " MTW3 ,Master 3 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MPL3 ,Master 3 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MTR3 ,Master 3 privilege level" "Forced,Not forced" endif newline group.long 0x20++0x03 line.long 0x00 "AIPS0_PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x24++0x03 line.long 0x00 "AIPS0_PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x28++0x03 line.long 0x00 "AIPS0_PACRC,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x2C++0x03 line.long 0x00 "AIPS0_PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x40++0x03 line.long 0x00 "AIPS0_PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x44++0x03 line.long 0x00 "AIPS0_PACRF,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x48++0x03 line.long 0x00 "AIPS0_PACRG,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x4C++0x03 line.long 0x00 "AIPS0_PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x50++0x03 line.long 0x00 "AIPS0_PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x54++0x03 line.long 0x00 "AIPS0_PACRJ,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x58++0x03 line.long 0x00 "AIPS0_PACRK,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x5C++0x03 line.long 0x00 "AIPS0_PACRL,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x60++0x03 line.long 0x00 "AIPS0_PACRM,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x64++0x03 line.long 0x00 "AIPS0_PACRN,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x68++0x03 line.long 0x00 "AIPS0_PACRO,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x6C++0x03 line.long 0x00 "AIPS0_PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" width 0x0B tree.end tree "AIPS 1" base ad:0x40080000 width 13. group.long 0x00++0x03 line.long 0x00 "AIPS0_MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master 0 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master 0 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master 0 privilege level" "Forced,Not forced" bitfld.long 0x00 26. " MTR1 ,Master 1 trusted for read" "Not trusted,Trusted" newline bitfld.long 0x00 25. " MTW1 ,Master 1 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master 1 privilege level" "Forced,Not forced" bitfld.long 0x00 22. " MTR2 ,Master 2 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master 2 trusted for writes" "Not trusted,Trusted" newline bitfld.long 0x00 20. " MPL2 ,Master 2 privilege level" "Forced,Not forced" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") bitfld.long 0x00 18. " MTW3 ,Master 3 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MPL3 ,Master 3 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MTR3 ,Master 3 privilege level" "Forced,Not forced" endif newline group.long 0x20++0x03 line.long 0x00 "AIPS0_PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x24++0x03 line.long 0x00 "AIPS0_PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x28++0x03 line.long 0x00 "AIPS0_PACRC,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x2C++0x03 line.long 0x00 "AIPS0_PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x40++0x03 line.long 0x00 "AIPS0_PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x44++0x03 line.long 0x00 "AIPS0_PACRF,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x48++0x03 line.long 0x00 "AIPS0_PACRG,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x4C++0x03 line.long 0x00 "AIPS0_PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x50++0x03 line.long 0x00 "AIPS0_PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x54++0x03 line.long 0x00 "AIPS0_PACRJ,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x58++0x03 line.long 0x00 "AIPS0_PACRK,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x5C++0x03 line.long 0x00 "AIPS0_PACRL,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x60++0x03 line.long 0x00 "AIPS0_PACRM,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x64++0x03 line.long 0x00 "AIPS0_PACRN,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x68++0x03 line.long 0x00 "AIPS0_PACRO,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x6C++0x03 line.long 0x00 "AIPS0_PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" width 0x0B tree.end tree.end tree "MPU (System Memory Protection Unit)" base ad:0x4000D000 width 13. group.long 0x00++0x03 line.long 0x00 "CESR,Control/Error Status Register" eventfld.long 0x00 31. " SPERR[0] ,Slave port 0 error" "No error,Error" eventfld.long 0x00 30. " SPERR[1] ,Slave port 1 error" "No error,Error" newline eventfld.long 0x00 29. " SPERR[2] ,Slave port 2 error" "No error,Error" eventfld.long 0x00 28. " SPERR[3] ,Slave port 3 error" "No error,Error" newline sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") eventfld.long 0x00 27. " SPERR[4] ,Slave port 4 error" "No error,Error" newline endif sif cpuis("MK??F*")||cpuis("KK28FN2M0CAU15R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK20DN512*AB10R")&&!cpuis("MK21F*")&&!cpuis("MK22FX512*")&&!cpuis("MK24FN*")&&!cpuis("MK26FN*")&&!cpuis("MK10F*")&&!cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK65FN2M0CAC18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline sif !cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" newline endif elif cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" sif !cpuis("MK63FN1M0VLQ12R") eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" endif endif endif rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK70F*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,?..." elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12*")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,?..." elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18*")||cpuis("MK66FN2M0VLQ18*") rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,Three MPU slave ports,?..." else newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,?..." endif newline rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8,12,16,?..." bitfld.long 0x00 0. " VLD ,Valid (global enable/disable for the MPU)" "Disabled,Enabled" newline sif cpuis("MK70*") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x48++0x07 line.long 0x00 "EAR7,Error Address Register" line.long 0x04 "EDR7,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" else rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" endif newline group.long 0x400++0x0F line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD0_WORD1,Region Descriptor 0 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD0_WORD2,Region Descriptor 0 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD0_WORD3,Region Descriptor 0 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x410++0x0F line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD1_WORD1,Region Descriptor 1 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD1_WORD2,Region Descriptor 1 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD1_WORD3,Region Descriptor 1 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x420++0x0F line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD2_WORD1,Region Descriptor 2 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD2_WORD2,Region Descriptor 2 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD2_WORD3,Region Descriptor 2 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x430++0x0F line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD3_WORD1,Region Descriptor 3 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD3_WORD2,Region Descriptor 3 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD3_WORD3,Region Descriptor 3 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x440++0x0F line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD4_WORD1,Region Descriptor 4 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD4_WORD2,Region Descriptor 4 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD4_WORD3,Region Descriptor 4 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x450++0x0F line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD5_WORD1,Region Descriptor 5 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD5_WORD2,Region Descriptor 5 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD5_WORD3,Region Descriptor 5 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x460++0x0F line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD6_WORD1,Region Descriptor 6 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD6_WORD2,Region Descriptor 6 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD6_WORD3,Region Descriptor 6 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x470++0x0F line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD7_WORD1,Region Descriptor 7 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD7_WORD2,Region Descriptor 7 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD7_WORD3,Region Descriptor 7 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x480++0x0F line.long 0x00 "RGD8_WORD0,Region Descriptor 8 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD8_WORD1,Region Descriptor 8 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD8_WORD2,Region Descriptor 8 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD8_WORD3,Region Descriptor 8 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x490++0x0F line.long 0x00 "RGD9_WORD0,Region Descriptor 9 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD9_WORD1,Region Descriptor 9 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD9_WORD2,Region Descriptor 9 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD9_WORD3,Region Descriptor 9 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4A0++0x0F line.long 0x00 "RGD10_WORD0,Region Descriptor 10 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD10_WORD1,Region Descriptor 10 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD10_WORD2,Region Descriptor 10 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD10_WORD3,Region Descriptor 10 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4B0++0x0F line.long 0x00 "RGD11_WORD0,Region Descriptor 11 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD11_WORD1,Region Descriptor 11 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD11_WORD2,Region Descriptor 11 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD11_WORD3,Region Descriptor 11 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x800++0x03 line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x804++0x03 line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x808++0x03 line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x80C++0x03 line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x810++0x03 line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x814++0x03 line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x818++0x03 line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x81C++0x03 line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x820++0x03 line.long 0x00 "RGDAAC8,Region Descriptor Alternate Access Control 8" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x824++0x03 line.long 0x00 "RGDAAC9,Region Descriptor Alternate Access Control 9" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x828++0x03 line.long 0x00 "RGDAAC10,Region Descriptor Alternate Access Control 10" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x82C++0x03 line.long 0x00 "RGDAAC11,Region Descriptor Alternate Access Control 11" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif width 0x0B tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 9. if (((per.b(ad:0x40021000)+0x0)&0x80)==0x80) group.byte 0x0++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 0 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 0 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x0++0x00 line.byte 0x00 "CHCFG0,Channel 0 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 0 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 0 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 0 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1)&0x80)==0x80) group.byte 0x1++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 1 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 1 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 1 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1++0x00 line.byte 0x00 "CHCFG1,Channel 1 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 1 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 1 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 1 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x2)&0x80)==0x80) group.byte 0x2++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 2 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 2 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 2 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x2++0x00 line.byte 0x00 "CHCFG2,Channel 2 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 2 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 2 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 2 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x3)&0x80)==0x80) group.byte 0x3++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 3 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 3 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x3++0x00 line.byte 0x00 "CHCFG3,Channel 3 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 3 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 3 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 3 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x4)&0x80)==0x80) group.byte 0x4++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 4 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 4 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 4 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x4++0x00 line.byte 0x00 "CHCFG4,Channel 4 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 4 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 4 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 4 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x5)&0x80)==0x80) group.byte 0x5++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 5 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 5 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x5++0x00 line.byte 0x00 "CHCFG5,Channel 5 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 5 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 5 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 5 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x6)&0x80)==0x80) group.byte 0x6++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 6 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 6 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 6 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x6++0x00 line.byte 0x00 "CHCFG6,Channel 6 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 6 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 6 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 6 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x7)&0x80)==0x80) group.byte 0x7++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 7 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 7 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 7 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x7++0x00 line.byte 0x00 "CHCFG7,Channel 7 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 7 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 7 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 7 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x8)&0x80)==0x80) group.byte 0x8++0x00 line.byte 0x00 "CHCFG8,Channel 8 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 8 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 8 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 8 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x8++0x00 line.byte 0x00 "CHCFG8,Channel 8 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 8 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 8 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 8 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x9)&0x80)==0x80) group.byte 0x9++0x00 line.byte 0x00 "CHCFG9,Channel 9 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 9 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 9 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 9 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x9++0x00 line.byte 0x00 "CHCFG9,Channel 9 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 9 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 9 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 9 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xA)&0x80)==0x80) group.byte 0xA++0x00 line.byte 0x00 "CHCFG10,Channel 10 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 10 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 10 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 10 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xA++0x00 line.byte 0x00 "CHCFG10,Channel 10 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 10 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 10 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 10 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xB)&0x80)==0x80) group.byte 0xB++0x00 line.byte 0x00 "CHCFG11,Channel 11 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 11 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 11 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 11 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xB++0x00 line.byte 0x00 "CHCFG11,Channel 11 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 11 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 11 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 11 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xC)&0x80)==0x80) group.byte 0xC++0x00 line.byte 0x00 "CHCFG12,Channel 12 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 12 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 12 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 12 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xC++0x00 line.byte 0x00 "CHCFG12,Channel 12 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 12 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 12 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 12 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xD)&0x80)==0x80) group.byte 0xD++0x00 line.byte 0x00 "CHCFG13,Channel 13 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 13 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 13 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 13 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xD++0x00 line.byte 0x00 "CHCFG13,Channel 13 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 13 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 13 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 13 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xE)&0x80)==0x80) group.byte 0xE++0x00 line.byte 0x00 "CHCFG14,Channel 14 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 14 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 14 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 14 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xE++0x00 line.byte 0x00 "CHCFG14,Channel 14 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 14 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 14 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 14 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0xF)&0x80)==0x80) group.byte 0xF++0x00 line.byte 0x00 "CHCFG15,Channel 15 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 15 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 15 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 15 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0xF++0x00 line.byte 0x00 "CHCFG15,Channel 15 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 15 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 15 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 15 Source" "Disabled,,UART0_R,UART0_T,UART1_R,UART1_T,FlexPWM0_WR0,FlexPWM0_WR1,FlexPWM0_WR2,FlexPWM0_WR3,FlexPWM0_CP0,FlexPWM0_CP1,FlexPWM0_CP2,FlexPWM0_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,HSADC0A Scan complete,HSADC0B Scan complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x10)&0x80)==0x80) group.byte 0x10++0x00 line.byte 0x00 "CHCFG16,Channel 16 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 16 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 16 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 16 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x10++0x00 line.byte 0x00 "CHCFG16,Channel 16 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 16 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 16 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 16 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x11)&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "CHCFG17,Channel 17 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 17 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 17 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 17 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x11++0x00 line.byte 0x00 "CHCFG17,Channel 17 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 17 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 17 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 17 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x12)&0x80)==0x80) group.byte 0x12++0x00 line.byte 0x00 "CHCFG18,Channel 18 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 18 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 18 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 18 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x12++0x00 line.byte 0x00 "CHCFG18,Channel 18 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 18 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 18 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 18 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x13)&0x80)==0x80) group.byte 0x13++0x00 line.byte 0x00 "CHCFG19,Channel 19 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 19 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 19 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 19 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x13++0x00 line.byte 0x00 "CHCFG19,Channel 19 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 19 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 19 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 19 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x14)&0x80)==0x80) group.byte 0x14++0x00 line.byte 0x00 "CHCFG20,Channel 20 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 20 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 20 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 20 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x14++0x00 line.byte 0x00 "CHCFG20,Channel 20 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 20 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 20 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 20 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x15)&0x80)==0x80) group.byte 0x15++0x00 line.byte 0x00 "CHCFG21,Channel 21 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 21 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 21 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 21 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x15++0x00 line.byte 0x00 "CHCFG21,Channel 21 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 21 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 21 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 21 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x16)&0x80)==0x80) group.byte 0x16++0x00 line.byte 0x00 "CHCFG22,Channel 22 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 22 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 22 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 22 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x16++0x00 line.byte 0x00 "CHCFG22,Channel 22 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 22 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 22 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 22 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x17)&0x80)==0x80) group.byte 0x17++0x00 line.byte 0x00 "CHCFG23,Channel 23 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 23 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 23 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 23 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x17++0x00 line.byte 0x00 "CHCFG23,Channel 23 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 23 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 23 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 23 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x18)&0x80)==0x80) group.byte 0x18++0x00 line.byte 0x00 "CHCFG24,Channel 24 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 24 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 24 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 24 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x18++0x00 line.byte 0x00 "CHCFG24,Channel 24 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 24 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 24 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 24 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x19)&0x80)==0x80) group.byte 0x19++0x00 line.byte 0x00 "CHCFG25,Channel 25 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 25 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 25 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 25 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x19++0x00 line.byte 0x00 "CHCFG25,Channel 25 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 25 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 25 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 25 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1A)&0x80)==0x80) group.byte 0x1A++0x00 line.byte 0x00 "CHCFG26,Channel 26 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 26 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 26 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 26 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1A++0x00 line.byte 0x00 "CHCFG26,Channel 26 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 26 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 26 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 26 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1B)&0x80)==0x80) group.byte 0x1B++0x00 line.byte 0x00 "CHCFG27,Channel 27 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 27 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 27 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 27 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1B++0x00 line.byte 0x00 "CHCFG27,Channel 27 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 27 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 27 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 27 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1C)&0x80)==0x80) group.byte 0x1C++0x00 line.byte 0x00 "CHCFG28,Channel 28 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 28 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 28 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 28 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1C++0x00 line.byte 0x00 "CHCFG28,Channel 28 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 28 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 28 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 28 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1D)&0x80)==0x80) group.byte 0x1D++0x00 line.byte 0x00 "CHCFG29,Channel 29 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 29 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 29 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 29 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1D++0x00 line.byte 0x00 "CHCFG29,Channel 29 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 29 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 29 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 29 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1E)&0x80)==0x80) group.byte 0x1E++0x00 line.byte 0x00 "CHCFG30,Channel 30 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 30 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 30 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 30 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1E++0x00 line.byte 0x00 "CHCFG30,Channel 30 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 30 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 30 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 30 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif if (((per.b(ad:0x40021000)+0x1F)&0x80)==0x80) group.byte 0x1F++0x00 line.byte 0x00 "CHCFG31,Channel 31 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 31 Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA Channel 31 Trigger Enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 31 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A scan complete,HSADC1B scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else group.byte 0x1F++0x00 line.byte 0x00 "CHCFG31,Channel 31 Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel 31 Enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " TRIG ,DMA Channel 31 Trigger Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel 31 Source" "Disabled,,UART2_R,UART2_T,UART3_R,UART3_T,FlexPWM1_WR0,FlexPWM1_WR1,FlexPWM1_WR2,FlexPWM1_WR3,FlexPWM1_CP0,FlexPWM1_CP1,FlexPWM1_CP2,FlexPWM1_CP3,,15,SPI1 Receive,SPI1 transmit,,,,,I2C1,,,,,,,,,,FTM2 Ch0,FTM2 Ch1,SPI2 Receive,SPI2 Transmit,IEEE 1588 Timer 0,IEEE 1588 Timer 1,IEEE 1588 Timer 2,IEEE 1588 Timer 3,HSADC1A Scan complete,HSADC1B Scan complete,,,,ADC0,,,,,,,,,UART4_R,UART4_T,UART5_R,UART5_T,,,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif width 0xb tree.end tree "eDMA (Enhanced Direct Memory Access)" base ad:0x40008000 width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 4" group.long 0x80++0x03 line.long 0x00 "TCD4_SADDR,TCD Source Address" group.word (0x80+0x04)++0x03 line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD4_DADDR,TCD Destination Address" group.word (0x80+0x14)++0x01 line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x80+0x18)++0x03 line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x80+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 5" group.long 0xA0++0x03 line.long 0x00 "TCD5_SADDR,TCD Source Address" group.word (0xA0+0x04)++0x03 line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD5_DADDR,TCD Destination Address" group.word (0xA0+0x14)++0x01 line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xA0+0x18)++0x03 line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xA0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 6" group.long 0xC0++0x03 line.long 0x00 "TCD6_SADDR,TCD Source Address" group.word (0xC0+0x04)++0x03 line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD6_DADDR,TCD Destination Address" group.word (0xC0+0x14)++0x01 line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xC0+0x18)++0x03 line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xC0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 7" group.long 0xE0++0x03 line.long 0x00 "TCD7_SADDR,TCD Source Address" group.word (0xE0+0x04)++0x03 line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD7_DADDR,TCD Destination Address" group.word (0xE0+0x14)++0x01 line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xE0+0x18)++0x03 line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xE0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 8" group.long 0x100++0x03 line.long 0x00 "TCD8_SADDR,TCD Source Address" group.word (0x100+0x04)++0x03 line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x100+0x08))&0xC0000000)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x100+0x0C)++0x07 line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD8_DADDR,TCD Destination Address" group.word (0x100+0x14)++0x01 line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x100+0x16))&0x8000)==0x00) group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x100+0x18)++0x03 line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x100+0x1C)++0x01 line.word 0x00 "TCD8_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x100+0x1E))&0x8000)==0x00) group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 9" group.long 0x120++0x03 line.long 0x00 "TCD9_SADDR,TCD Source Address" group.word (0x120+0x04)++0x03 line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x120+0x08))&0xC0000000)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x120+0x0C)++0x07 line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD9_DADDR,TCD Destination Address" group.word (0x120+0x14)++0x01 line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x120+0x16))&0x8000)==0x00) group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x120+0x18)++0x03 line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x120+0x1C)++0x01 line.word 0x00 "TCD9_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x120+0x1E))&0x8000)==0x00) group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 10" group.long 0x140++0x03 line.long 0x00 "TCD10_SADDR,TCD Source Address" group.word (0x140+0x04)++0x03 line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x140+0x08))&0xC0000000)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x140+0x0C)++0x07 line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD10_DADDR,TCD Destination Address" group.word (0x140+0x14)++0x01 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x140+0x16))&0x8000)==0x00) group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x140+0x18)++0x03 line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x140+0x1E))&0x8000)==0x00) group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 11" group.long 0x160++0x03 line.long 0x00 "TCD11_SADDR,TCD Source Address" group.word (0x160+0x04)++0x03 line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x160+0x08))&0xC0000000)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x160+0x0C)++0x07 line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD11_DADDR,TCD Destination Address" group.word (0x160+0x14)++0x01 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x160+0x16))&0x8000)==0x00) group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x160+0x18)++0x03 line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x160+0x1E))&0x8000)==0x00) group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 12" group.long 0x180++0x03 line.long 0x00 "TCD12_SADDR,TCD Source Address" group.word (0x180+0x04)++0x03 line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x180+0x08))&0xC0000000)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x180+0x0C)++0x07 line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD12_DADDR,TCD Destination Address" group.word (0x180+0x14)++0x01 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x180+0x16))&0x8000)==0x00) group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x180+0x18)++0x03 line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x180+0x1E))&0x8000)==0x00) group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 13" group.long 0x1A0++0x03 line.long 0x00 "TCD13_SADDR,TCD Source Address" group.word (0x1A0+0x04)++0x03 line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1A0+0x08))&0xC0000000)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1A0+0x0C)++0x07 line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD13_DADDR,TCD Destination Address" group.word (0x1A0+0x14)++0x01 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1A0+0x16))&0x8000)==0x00) group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1A0+0x18)++0x03 line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00) group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 14" group.long 0x1C0++0x03 line.long 0x00 "TCD14_SADDR,TCD Source Address" group.word (0x1C0+0x04)++0x03 line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1C0+0x08))&0xC0000000)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1C0+0x0C)++0x07 line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD14_DADDR,TCD Destination Address" group.word (0x1C0+0x14)++0x01 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1C0+0x16))&0x8000)==0x00) group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1C0+0x18)++0x03 line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00) group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 15" group.long 0x1E0++0x03 line.long 0x00 "TCD15_SADDR,TCD Source Address" group.word (0x1E0+0x04)++0x03 line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1E0+0x08))&0xC0000000)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1E0+0x0C)++0x07 line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD15_DADDR,TCD Destination Address" group.word (0x1E0+0x14)++0x01 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1E0+0x16))&0x8000)==0x00) group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1E0+0x18)++0x03 line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00) group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 16" group.long 0x200++0x03 line.long 0x00 "TCD16_SADDR,TCD Source Address" group.word (0x200+0x04)++0x03 line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD16_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x200+0x08))&0xC0000000)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x200+0x0C)++0x07 line.long 0x00 "TCD16_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD16_DADDR,TCD Destination Address" group.word (0x200+0x14)++0x01 line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x200+0x16))&0x8000)==0x00) group.word (0x200+0x16)++0x01 line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x200+0x16)++0x01 line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x200+0x18)++0x03 line.long 0x00 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x200+0x1C)++0x01 line.word 0x00 "TCD16_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x200+0x1E))&0x8000)==0x00) group.word (0x200+0x1E)++0x01 line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x200+0x1E)++0x01 line.word 0x00 "TCD16_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 17" group.long 0x220++0x03 line.long 0x00 "TCD17_SADDR,TCD Source Address" group.word (0x220+0x04)++0x03 line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD17_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x220+0x08))&0xC0000000)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x220+0x0C)++0x07 line.long 0x00 "TCD17_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD17_DADDR,TCD Destination Address" group.word (0x220+0x14)++0x01 line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x220+0x16))&0x8000)==0x00) group.word (0x220+0x16)++0x01 line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x220+0x16)++0x01 line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x220+0x18)++0x03 line.long 0x00 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x220+0x1C)++0x01 line.word 0x00 "TCD17_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x220+0x1E))&0x8000)==0x00) group.word (0x220+0x1E)++0x01 line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x220+0x1E)++0x01 line.word 0x00 "TCD17_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 18" group.long 0x240++0x03 line.long 0x00 "TCD18_SADDR,TCD Source Address" group.word (0x240+0x04)++0x03 line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD18_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x240+0x08))&0xC0000000)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x240+0x0C)++0x07 line.long 0x00 "TCD18_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD18_DADDR,TCD Destination Address" group.word (0x240+0x14)++0x01 line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x240+0x16))&0x8000)==0x00) group.word (0x240+0x16)++0x01 line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x240+0x16)++0x01 line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x240+0x18)++0x03 line.long 0x00 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x240+0x1C)++0x01 line.word 0x00 "TCD18_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x240+0x1E))&0x8000)==0x00) group.word (0x240+0x1E)++0x01 line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x240+0x1E)++0x01 line.word 0x00 "TCD18_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 19" group.long 0x260++0x03 line.long 0x00 "TCD19_SADDR,TCD Source Address" group.word (0x260+0x04)++0x03 line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD19_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x260+0x08))&0xC0000000)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x260+0x0C)++0x07 line.long 0x00 "TCD19_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD19_DADDR,TCD Destination Address" group.word (0x260+0x14)++0x01 line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x260+0x16))&0x8000)==0x00) group.word (0x260+0x16)++0x01 line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x260+0x16)++0x01 line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x260+0x18)++0x03 line.long 0x00 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x260+0x1C)++0x01 line.word 0x00 "TCD19_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x260+0x1E))&0x8000)==0x00) group.word (0x260+0x1E)++0x01 line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x260+0x1E)++0x01 line.word 0x00 "TCD19_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 20" group.long 0x280++0x03 line.long 0x00 "TCD20_SADDR,TCD Source Address" group.word (0x280+0x04)++0x03 line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD20_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x280+0x08))&0xC0000000)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x280+0x0C)++0x07 line.long 0x00 "TCD20_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD20_DADDR,TCD Destination Address" group.word (0x280+0x14)++0x01 line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x280+0x16))&0x8000)==0x00) group.word (0x280+0x16)++0x01 line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x280+0x16)++0x01 line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x280+0x18)++0x03 line.long 0x00 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x280+0x1C)++0x01 line.word 0x00 "TCD20_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x280+0x1E))&0x8000)==0x00) group.word (0x280+0x1E)++0x01 line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x280+0x1E)++0x01 line.word 0x00 "TCD20_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 21" group.long 0x2A0++0x03 line.long 0x00 "TCD21_SADDR,TCD Source Address" group.word (0x2A0+0x04)++0x03 line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD21_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2A0+0x08))&0xC0000000)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2A0+0x0C)++0x07 line.long 0x00 "TCD21_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD21_DADDR,TCD Destination Address" group.word (0x2A0+0x14)++0x01 line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x2A0+0x16))&0x8000)==0x00) group.word (0x2A0+0x16)++0x01 line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2A0+0x16)++0x01 line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x2A0+0x18)++0x03 line.long 0x00 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x2A0+0x1C)++0x01 line.word 0x00 "TCD21_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x00) group.word (0x2A0+0x1E)++0x01 line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2A0+0x1E)++0x01 line.word 0x00 "TCD21_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 22" group.long 0x2C0++0x03 line.long 0x00 "TCD22_SADDR,TCD Source Address" group.word (0x2C0+0x04)++0x03 line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD22_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2C0+0x08))&0xC0000000)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2C0+0x0C)++0x07 line.long 0x00 "TCD22_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD22_DADDR,TCD Destination Address" group.word (0x2C0+0x14)++0x01 line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x2C0+0x16))&0x8000)==0x00) group.word (0x2C0+0x16)++0x01 line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2C0+0x16)++0x01 line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x2C0+0x18)++0x03 line.long 0x00 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x2C0+0x1C)++0x01 line.word 0x00 "TCD22_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x00) group.word (0x2C0+0x1E)++0x01 line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2C0+0x1E)++0x01 line.word 0x00 "TCD22_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 23" group.long 0x2E0++0x03 line.long 0x00 "TCD23_SADDR,TCD Source Address" group.word (0x2E0+0x04)++0x03 line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD23_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2E0+0x08))&0xC0000000)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2E0+0x0C)++0x07 line.long 0x00 "TCD23_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD23_DADDR,TCD Destination Address" group.word (0x2E0+0x14)++0x01 line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x2E0+0x16))&0x8000)==0x00) group.word (0x2E0+0x16)++0x01 line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2E0+0x16)++0x01 line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x2E0+0x18)++0x03 line.long 0x00 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x2E0+0x1C)++0x01 line.word 0x00 "TCD23_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x00) group.word (0x2E0+0x1E)++0x01 line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2E0+0x1E)++0x01 line.word 0x00 "TCD23_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 24" group.long 0x300++0x03 line.long 0x00 "TCD24_SADDR,TCD Source Address" group.word (0x300+0x04)++0x03 line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD24_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x300+0x08))&0xC0000000)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x300+0x0C)++0x07 line.long 0x00 "TCD24_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD24_DADDR,TCD Destination Address" group.word (0x300+0x14)++0x01 line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x300+0x16))&0x8000)==0x00) group.word (0x300+0x16)++0x01 line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x300+0x16)++0x01 line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x300+0x18)++0x03 line.long 0x00 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x300+0x1C)++0x01 line.word 0x00 "TCD24_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x300+0x1E))&0x8000)==0x00) group.word (0x300+0x1E)++0x01 line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x300+0x1E)++0x01 line.word 0x00 "TCD24_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 25" group.long 0x320++0x03 line.long 0x00 "TCD25_SADDR,TCD Source Address" group.word (0x320+0x04)++0x03 line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD25_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x320+0x08))&0xC0000000)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x320+0x0C)++0x07 line.long 0x00 "TCD25_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD25_DADDR,TCD Destination Address" group.word (0x320+0x14)++0x01 line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x320+0x16))&0x8000)==0x00) group.word (0x320+0x16)++0x01 line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x320+0x16)++0x01 line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x320+0x18)++0x03 line.long 0x00 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x320+0x1C)++0x01 line.word 0x00 "TCD25_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x320+0x1E))&0x8000)==0x00) group.word (0x320+0x1E)++0x01 line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x320+0x1E)++0x01 line.word 0x00 "TCD25_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 26" group.long 0x340++0x03 line.long 0x00 "TCD26_SADDR,TCD Source Address" group.word (0x340+0x04)++0x03 line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD26_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x340+0x08))&0xC0000000)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x340+0x0C)++0x07 line.long 0x00 "TCD26_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD26_DADDR,TCD Destination Address" group.word (0x340+0x14)++0x01 line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x340+0x16))&0x8000)==0x00) group.word (0x340+0x16)++0x01 line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x340+0x16)++0x01 line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x340+0x18)++0x03 line.long 0x00 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x340+0x1C)++0x01 line.word 0x00 "TCD26_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x340+0x1E))&0x8000)==0x00) group.word (0x340+0x1E)++0x01 line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x340+0x1E)++0x01 line.word 0x00 "TCD26_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 27" group.long 0x360++0x03 line.long 0x00 "TCD27_SADDR,TCD Source Address" group.word (0x360+0x04)++0x03 line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD27_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x360+0x08))&0xC0000000)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x360+0x0C)++0x07 line.long 0x00 "TCD27_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD27_DADDR,TCD Destination Address" group.word (0x360+0x14)++0x01 line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x360+0x16))&0x8000)==0x00) group.word (0x360+0x16)++0x01 line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x360+0x16)++0x01 line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x360+0x18)++0x03 line.long 0x00 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x360+0x1C)++0x01 line.word 0x00 "TCD27_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x360+0x1E))&0x8000)==0x00) group.word (0x360+0x1E)++0x01 line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x360+0x1E)++0x01 line.word 0x00 "TCD27_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 28" group.long 0x380++0x03 line.long 0x00 "TCD28_SADDR,TCD Source Address" group.word (0x380+0x04)++0x03 line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD28_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x380+0x08))&0xC0000000)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x380+0x0C)++0x07 line.long 0x00 "TCD28_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD28_DADDR,TCD Destination Address" group.word (0x380+0x14)++0x01 line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x380+0x16))&0x8000)==0x00) group.word (0x380+0x16)++0x01 line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x380+0x16)++0x01 line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x380+0x18)++0x03 line.long 0x00 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x380+0x1C)++0x01 line.word 0x00 "TCD28_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x380+0x1E))&0x8000)==0x00) group.word (0x380+0x1E)++0x01 line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x380+0x1E)++0x01 line.word 0x00 "TCD28_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 29" group.long 0x3A0++0x03 line.long 0x00 "TCD29_SADDR,TCD Source Address" group.word (0x3A0+0x04)++0x03 line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD29_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3A0+0x08))&0xC0000000)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3A0+0x0C)++0x07 line.long 0x00 "TCD29_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD29_DADDR,TCD Destination Address" group.word (0x3A0+0x14)++0x01 line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x3A0+0x16))&0x8000)==0x00) group.word (0x3A0+0x16)++0x01 line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3A0+0x16)++0x01 line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x3A0+0x18)++0x03 line.long 0x00 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x3A0+0x1C)++0x01 line.word 0x00 "TCD29_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x00) group.word (0x3A0+0x1E)++0x01 line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3A0+0x1E)++0x01 line.word 0x00 "TCD29_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 30" group.long 0x3C0++0x03 line.long 0x00 "TCD30_SADDR,TCD Source Address" group.word (0x3C0+0x04)++0x03 line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD30_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3C0+0x08))&0xC0000000)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3C0+0x0C)++0x07 line.long 0x00 "TCD30_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD30_DADDR,TCD Destination Address" group.word (0x3C0+0x14)++0x01 line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x3C0+0x16))&0x8000)==0x00) group.word (0x3C0+0x16)++0x01 line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3C0+0x16)++0x01 line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x3C0+0x18)++0x03 line.long 0x00 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x3C0+0x1C)++0x01 line.word 0x00 "TCD30_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x00) group.word (0x3C0+0x1E)++0x01 line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3C0+0x1E)++0x01 line.word 0x00 "TCD30_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 31" group.long 0x3E0++0x03 line.long 0x00 "TCD31_SADDR,TCD Source Address" group.word (0x3E0+0x04)++0x03 line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD31_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3E0+0x08))&0xC0000000)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3E0+0x0C)++0x07 line.long 0x00 "TCD31_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD31_DADDR,TCD Destination Address" group.word (0x3E0+0x14)++0x01 line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x3E0+0x16))&0x8000)==0x00) group.word (0x3E0+0x16)++0x01 line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3E0+0x16)++0x01 line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x3E0+0x18)++0x03 line.long 0x00 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x3E0+0x1C)++0x01 line.word 0x00 "TCD31_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x00) group.word (0x3E0+0x1E)++0x01 line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3E0+0x1E)++0x01 line.word 0x00 "TCD31_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Clock source select" "LPO_CLK[0],LPO_CLK[1],LPO_CLK[2],LPO_CLK[3]" endif sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,Allows the WDOG functional test mode to be disabled permanently" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested when the watchdog is in the byte test mode" "0,1,2,3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick,Byte" newline bitfld.word 0x00 10. " TESTWDOG ,Puts the watchdog in the functional test mode" "Disabled,Enabled" bitfld.word 0x00 7. " WAITEN ,Enables or disables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables or disables WDOG in stop mode" "Disabled,Enabled" newline bitfld.word 0x00 5. " DBGEN ,Enables or disables WDOG in debug mode" "Disabled,Enabled" bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" newline bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables or disables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F128VLH10P") eventfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" else bitfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" endif line.word 0x04 "TOVALH,Watchdog Time-Out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-Out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "AOI (Crossbar AND/OR/INVERT)" base ad:0x4005B000 width 10. group.word 0x00++0x0F line.word 0x00 "BFCRT010,Boolean Function Term 0 And 1 Configuration Register For EVENT0" bitfld.word 0x00 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x00 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x02 "BFCRT230,Boolean Function Term 2 And 3 Configuration Register For EVENT0" bitfld.word 0x02 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x02 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x04 "BFCRT011,Boolean Function Term 0 And 1 Configuration Register For EVENT1" bitfld.word 0x04 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x04 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x06 "BFCRT231,Boolean Function Term 2 And 3 Configuration Register For EVENT1" bitfld.word 0x06 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x06 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x08 "BFCRT012,Boolean Function Term 0 And 1 Configuration Register For EVENT2" bitfld.word 0x08 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x08 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0A "BFCRT232,Boolean Function Term 2 And 3 Configuration Register For EVENT2" bitfld.word 0x0A 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0A 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0C "BFCRT013,Boolean Function Term 0 And 1 Configuration Register For EVENT3" bitfld.word 0x0C 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0C 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0E "BFCRT233,Boolean Function Term 2 And 3 Configuration Register For EVENT3" bitfld.word 0x0E 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0E 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" width 0x0B tree.end tree "XBARA (Inter-Peripheral Crossbar Switch A)" base ad:0x40059000 width 7. group.word 0x0++0x01 line.word 0x00 "SEL0,Crossbar A Select Register 0" bitfld.word 0x00 8.--13. " SEL1 ,XBARA_OUT1 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL0 ,XBARA_OUT0 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x2++0x01 line.word 0x00 "SEL1,Crossbar A Select Register 1" bitfld.word 0x00 8.--13. " SEL3 ,XBARA_OUT3 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL2 ,XBARA_OUT2 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x4++0x01 line.word 0x00 "SEL2,Crossbar A Select Register 2" bitfld.word 0x00 8.--13. " SEL5 ,XBARA_OUT5 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL4 ,XBARA_OUT4 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x6++0x01 line.word 0x00 "SEL3,Crossbar A Select Register 3" bitfld.word 0x00 8.--13. " SEL7 ,XBARA_OUT7 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL6 ,XBARA_OUT6 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x8++0x01 line.word 0x00 "SEL4,Crossbar A Select Register 4" bitfld.word 0x00 8.--13. " SEL9 ,XBARA_OUT9 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL8 ,XBARA_OUT8 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0xA++0x01 line.word 0x00 "SEL5,Crossbar A Select Register 5" bitfld.word 0x00 8.--13. " SEL11 ,XBARA_OUT11 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL10 ,XBARA_OUT10 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0xC++0x01 line.word 0x00 "SEL6,Crossbar A Select Register 6" bitfld.word 0x00 8.--13. " SEL13 ,XBARA_OUT13 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL12 ,XBARA_OUT12 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0xE++0x01 line.word 0x00 "SEL7,Crossbar A Select Register 7" bitfld.word 0x00 8.--13. " SEL15 ,XBARA_OUT15 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL14 ,XBARA_OUT14 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x10++0x01 line.word 0x00 "SEL8,Crossbar A Select Register 8" bitfld.word 0x00 8.--13. " SEL17 ,XBARA_OUT17 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL16 ,XBARA_OUT16 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x12++0x01 line.word 0x00 "SEL9,Crossbar A Select Register 9" bitfld.word 0x00 8.--13. " SEL19 ,XBARA_OUT19 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL18 ,XBARA_OUT18 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x14++0x01 line.word 0x00 "SEL10,Crossbar A Select Register 10" bitfld.word 0x00 8.--13. " SEL21 ,XBARA_OUT21 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL20 ,XBARA_OUT20 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x16++0x01 line.word 0x00 "SEL11,Crossbar A Select Register 11" bitfld.word 0x00 8.--13. " SEL23 ,XBARA_OUT23 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL22 ,XBARA_OUT22 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x18++0x01 line.word 0x00 "SEL12,Crossbar A Select Register 12" bitfld.word 0x00 8.--13. " SEL25 ,XBARA_OUT25 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL24 ,XBARA_OUT24 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x1A++0x01 line.word 0x00 "SEL13,Crossbar A Select Register 13" bitfld.word 0x00 8.--13. " SEL27 ,XBARA_OUT27 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL26 ,XBARA_OUT26 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x1C++0x01 line.word 0x00 "SEL14,Crossbar A Select Register 14" bitfld.word 0x00 8.--13. " SEL29 ,XBARA_OUT29 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL28 ,XBARA_OUT28 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x1E++0x01 line.word 0x00 "SEL15,Crossbar A Select Register 15" bitfld.word 0x00 8.--13. " SEL31 ,XBARA_OUT31 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL30 ,XBARA_OUT30 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x20++0x01 line.word 0x00 "SEL16,Crossbar A Select Register 16" bitfld.word 0x00 8.--13. " SEL33 ,XBARA_OUT33 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL32 ,XBARA_OUT32 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x22++0x01 line.word 0x00 "SEL17,Crossbar A Select Register 17" bitfld.word 0x00 8.--13. " SEL35 ,XBARA_OUT35 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL34 ,XBARA_OUT34 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x24++0x01 line.word 0x00 "SEL18,Crossbar A Select Register 18" bitfld.word 0x00 8.--13. " SEL37 ,XBARA_OUT37 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL36 ,XBARA_OUT36 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x26++0x01 line.word 0x00 "SEL19,Crossbar A Select Register 19" bitfld.word 0x00 8.--13. " SEL39 ,XBARA_OUT39 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL38 ,XBARA_OUT38 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x28++0x01 line.word 0x00 "SEL20,Crossbar A Select Register 20" bitfld.word 0x00 8.--13. " SEL41 ,XBARA_OUT41 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL40 ,XBARA_OUT40 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x2A++0x01 line.word 0x00 "SEL21,Crossbar A Select Register 21" bitfld.word 0x00 8.--13. " SEL43 ,XBARA_OUT43 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL42 ,XBARA_OUT42 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x2C++0x01 line.word 0x00 "SEL22,Crossbar A Select Register 22" bitfld.word 0x00 8.--13. " SEL45 ,XBARA_OUT45 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL44 ,XBARA_OUT44 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x2E++0x01 line.word 0x00 "SEL23,Crossbar A Select Register 23" bitfld.word 0x00 8.--13. " SEL47 ,XBARA_OUT47 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL46 ,XBARA_OUT46 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x30++0x01 line.word 0x00 "SEL24,Crossbar A Select Register 24" bitfld.word 0x00 8.--13. " SEL49 ,XBARA_OUT49 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL48 ,XBARA_OUT48 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x32++0x01 line.word 0x00 "SEL25,Crossbar A Select Register 25" bitfld.word 0x00 8.--13. " SEL51 ,XBARA_OUT51 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL50 ,XBARA_OUT50 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x34++0x01 line.word 0x00 "SEL26,Crossbar A Select Register 26" bitfld.word 0x00 8.--13. " SEL53 ,XBARA_OUT53 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL52 ,XBARA_OUT52 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x36++0x01 line.word 0x00 "SEL27,Crossbar A Select Register 27" bitfld.word 0x00 8.--13. " SEL55 ,XBARA_OUT55 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL54 ,XBARA_OUT54 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x38++0x01 line.word 0x00 "SEL28,Crossbar A Select Register 28" bitfld.word 0x00 8.--13. " SEL57 ,XBARA_OUT57 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." bitfld.word 0x00 0.--5. " SEL56 ,XBARA_OUT56 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." group.word 0x3A++0x05 line.word 0x00 "SEL29,Crossbar A Select Register 29" bitfld.word 0x00 0.--5. " SEL58 ,XBARA_OUT58 Input Selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRG00,PWM0_OUT_TRG01,PWM0_OUT_TRG10,PWM0_OUT_TRG11,PWM0_OUT_TRG20,PWM0_OUT_TRG21,PWM0_OUT_TRG30,PWM0_OUT_TRG31,PDB0_CH1_OUT,PDB0_CH0_OUT,PDB1_CH1_OUT,PDB1_CH0_OUT,HSADC1A Scan complete,HSADC0A Scan complete,HSADC1B Scan complete,HSADC0B Scan complete,FTM1_allTRIG,FTM1_INIT,DMA ch0_done,DMA ch1_done,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,ADC0_COCO,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT ch2,PIT ch3,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,?..." textline " " line.word 0x02 "CTRL0,Crossbar A Control Register 0" eventfld.word 0x02 12. " STS1 ,Edge detection status for XBAR_OUT1" "Not detected,Detected" bitfld.word 0x02 10.--11. " EDGE1 ,Active edge for edge detection on XBAR_OUT1" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x02 9. " IEN1 ,Interrupt Enable for XBAR_OUT1" "Disabled,Enabled" bitfld.word 0x02 8. " DEN1 ,DMA Enable for XBAR_OUT1" "Disabled,Enabled" textline " " eventfld.word 0x02 4. " STS0 ,Edge detection status for XBAR_OUT0" "Not detected,Detected" bitfld.word 0x02 2.--3. " EDGE0 ,Active edge for edge detection on XBAR_OUT0" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x02 1. " IEN0 ,Interrupt Enable for XBAR_OUT0" "Disabled,Enabled" bitfld.word 0x02 0. " DEN0 ,DMA Enable for XBAR_OUT0" "Disabled,Enabled" line.word 0x04 "CTRL1,Crossbar A Control Register 1" eventfld.word 0x04 12. " STS3 ,Edge detection status for XBAR_OUT3" "Not detected,Detected" bitfld.word 0x04 10.--11. " EDGE3 ,Active edge for edge detection on XBAR_OUT3" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x04 9. " IEN3 ,Interrupt Enable for XBAR_OUT3" "Disabled,Enabled" bitfld.word 0x04 8. " DEN3 ,DMA Enable for XBAR_OUT3" "Disabled,Enabled" textline " " eventfld.word 0x04 4. " STS2 ,Edge detection status for XBAR_OUT2" "Not detected,Detected" bitfld.word 0x04 2.--3. " EDGE2 ,Active edge for edge detection on XBAR_OUT2" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x04 1. " IEN2 ,Interrupt Enable for XBAR_OUT2" "Disabled,Enabled" bitfld.word 0x04 0. " DEN2 ,DMA Enable for XBAR_OUT2" "Disabled,Enabled" width 0x0B tree.end tree "XBARB (Inter-Peripheral Crossbar Switch B)" base ad:0x4005A000 width 7. group.word 0x00++0x0F line.word 0x00 "SEL0,Crossbar B Select Register 0" bitfld.word 0x00 8.--13. " SEL1 ,XBARB_OUT1 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x00 0.--5. " SEL0 ,XBARB_OUT0 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x02 "SEL1,Crossbar B Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBARB_OUT3 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBARB_OUT2 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x04 "SEL2,Crossbar B Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBARB_OUT5 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBARB_OUT4 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x06 "SEL3,Crossbar B Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBARB_OUT7 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBARB_OUT6 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x08 "SEL4,Crossbar B Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBARB_OUT9 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBARB_OUT8 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x0A "SEL5,Crossbar B Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBARB_OUT11 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBARB_OUT10 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x0C "SEL6,Crossbar B Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBARB_OUT13 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBARB_OUT12 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." line.word 0x0E "SEL7,Crossbar B Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBARB_OUT15 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBARB_OUT14 Input Selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWM0_OUT_TRIG00/PWM0_OUT_TRIG01,PWM0_OUT_TRIG10/PWM0_OUT_TRIG11,PWM0_OUT_TRIG20/PWM0_OUT_TRIG21,PWM0_OUT_TRIG30/PWM0_OUT_TRIG31,PDB0_CH0_OUT,HSADC0A_Scan_complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_CH0_OUT,HSADC0B_Scan_complete,PWM1_OUT_TRIG00/PWM1_OUT_TRIG01,PWM1_OUT_TRIG10/PWM1_OUT_TRIG11,PWM1_OUT_TRIG20/PWM1_OUT_TRIG21,PWM1_OUT_TRIG30/PWM1_OUT_TRIG31,FTM2_allTRIG,FTM2_INIT,PDB0_CH1_OUT,PDB1_CH1_OUT,HSADC1A_Scan_complete,HSADC1B_Scan_complete,ADC0_COCO,?..." width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. sif (cpuis("MKV10Z*"))||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif elif cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12?")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)!=0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif else if (((per.b(ad:0x40064000+0x01))&0x30)==0x00||((per.b(ad:0x40064000+0x0C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" else bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" endif line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x03))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20-25 mHz,24 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "40-50 mHz,48 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60-75 mHz,72 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80-100 mHz,96 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" endif sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV10Z*") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN0 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN0 ,PLL stop enable" "Disabled,Enabled" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." newline endif newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV0 ,VCO 0 divider" "24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55" else group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV ,VCO divider" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif cpuis("MKV10Z*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" else bitfld.byte 0x00 7. " LOLS0 ,Loss of lock status" "Not locked,Locked" bitfld.byte 0x00 6. " LOCK0 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,Output PLL" bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" endif group.byte 0x08++0x00 sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" eventfld.byte 0x00 0. " LOCS0 ,OSC0 loss of clock status" "Not occurred,Occurred" else line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" rbitfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred" endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32khz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" newline hgroup.byte 0x11++0x00 hide.long 0x00 "C12,MCG Control 12 Register" hgroup.byte 0x12++0x00 hide.long 0x00 "S2,MCG Status 2 Register" hgroup.byte 0x13++0x00 hide.long 0x00 "T3,MCG Test 3 Register" elif (!cpuis("MKV10Z*"))&&(!cpuis("MKV5*"))&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif cpuis("MK65FN2M0CAF18")||cpuis("MK65FN2M0VMF18")||cpuis("MK65FX1M0CAF18")||cpuis("MK65FX1M0VMF18")||cpuis("MK66FN2M0VLQ18")||cpuis("MK66FN2M0VMD18")||cpuis("MK66FX1M0VLQ18")||cpuis("MK66FX1M0VMD18") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Disabled,Enabled" rbitfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" endif else sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" elif !cpuis("MKV10Z*")&&!cpuis("MKV11Z*") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif endif width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40065000 width 4. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKV5*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18*") width 9. newline group.byte 0x02++0x00 line.byte 0x00 "OSC_DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "FMC (Flash Memory Controller)" base ad:0x4001F000 width 8. group.long 0x00++0x07 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" textline " " bitfld.long 0x00 6.--7. " M3AP[1:0] ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP[1:0] ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP[1:0] ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP[1:0] ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" line.long 0x04 "PFB0CR,Flash Bank 0 Control Register" rbitfld.long 0x04 28.--31. " B0RWSC[3:0] ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 19. " S_B_INV ,Invalid fmcfer" "No effect,Invalidate" rbitfld.long 0x04 17.--18. " B0MW[1:0] ,Bank 0 memory width" "32 bits,64 bits,128 bits,256 bits" textline " " bitfld.long 0x04 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled" bitfld.long 0x04 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled" width 0x0B tree.end tree "FTFE (Flash Memory Module)" base ad:0x40020000 width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" newline eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif (cpuis("MKV5*")) newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready" elif (cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block" rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..." newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" else newline rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..." rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif rgroup.byte 0x02++0x00 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" newline bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" sif cpuis("MKV5*") rgroup.byte 0x03++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" sif !cpuis("MKV5*") group.byte 0x10++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x18++0x03 line.byte 0x00 "FPROTH3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTH2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTH1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTH0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV31F*")&&cpuis("MKV30F*") group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" line.byte 0x01 "FDPROT,Data Flash Protection Register" endif newline sif cpuis("MKV31F*")||cpuis("MKV30F*") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif width 0x0B tree.end tree "FLEXBUS (External Bus Interface)" base ad:0x4000C000 width 8. group.long 0x0++0x07 line.long 0x00 "CSAR0,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR0,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x0+0x08))&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0xC++0x07 line.long 0x00 "CSAR1,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR1,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0xC+0x08))&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x18++0x07 line.long 0x00 "CSAR2,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR2,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x18+0x08))&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x24++0x07 line.long 0x00 "CSAR3,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR3,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x24+0x08))&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x30++0x07 line.long 0x00 "CSAR4,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR4,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x30+0x08))&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x3C++0x07 line.long 0x00 "CSAR5,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR5,Chip Select Mask Register" bitfld.long 0x04 31. " BAM[31] ,Base address bit 31 mask" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,Base address bit 30 mask" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,Base address bit 29 mask" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,Base address bit 28 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [27] ,Base address bit 27 mask" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,Base address bit 26 mask" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,Base address bit 25 mask" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,Base address bit 24 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,Base address bit 23 mask" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,Base address bit 22 mask" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,Base address bit 21 mask" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,Base address bit 20 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [19] ,Base address bit 19 mask" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,Base address bit 18 mask" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,Base address bit 17 mask" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,Base address bit 16 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" newline if ((per.l(ad:0x4000C000+(0x3C+0x08))&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycle,1 cycles,2 cycles,3 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" newline bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Not asserted for reads,Asserted for read and write" newline bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif newline group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP1 ,FlexBus signal group 1 multiplex control" "FB_ALE,FB_CS1,FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP2 ,FlexBus signal group 2 multiplex control" "FB_CS4,FB_TSIZ0,FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP3 ,FlexBus signal group 3 multiplex control" "FB_CS5,FB_TSIZ1,FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP4 ,FlexBus signal group 4 multiplex control" "FB_TBST,FB_CS2,FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP5 ,FlexBus signal group 5 multiplex control" "FB_TA,FB_CS3,FB_BE_7_0,?..." width 0x0B tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x00) group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" else group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal half-word" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" endif width 0x0B tree.end tree "MMCAU (Memory-Mapped Cryptographic Acceleration Unit)" base ad:0xE0081000 width 6. group.long 0x00++0x03 line.long 0x00 "CASR,Status Register" rbitfld.long 0x00 28.--31. " VER ,CAU version" ",Initial CAU version,Second version(with SHA-256 algorithm),?..." bitfld.long 0x00 1. " DPE ,DES parity error" "No error,Error" bitfld.long 0x00 0. " IC ,Illegal command" "Not issued,Issued" group.long 0x01++0x03 line.long 0x00 "CAA,Accumulator" sif cpuis("MK24FN*") group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" else group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" group.long 0x8++0x03 line.long 0x00 "CA6,General Purpose Register" group.long 0x9++0x03 line.long 0x00 "CA7,General Purpose Register" group.long 0xA++0x03 line.long 0x00 "CA8,General Purpose Register" endif width 0x0B tree.end tree "TRNG (True Random Number Generator)" base ad:0x400A0000 width 12. if (((per.l(ad:0x400A0000))&0x10000)==0x00) group.long 0x00++0x03 line.long 0x00 "MCTL,TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running" eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" rbitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock" rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value" rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "/1,/2,/4,/8" rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..." else group.long 0x00++0x03 line.long 0x00 "MCTL,RNG TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,RNG ring oscillator (used for entropy generation) is not running" "Running,Not running" eventfld.long 0x00 12. " ERR ,Read: error status (read/write)" "No error/No effect,Error/Clear" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" bitfld.long 0x00 7. " FOR_SCLK ,Force system clock" "Ring oscillator,System clock" bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No effect,Clear" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "No effect,Generate entropy value" bitfld.long 0x00 2.--3. " OSC_DIV ,Ring oscillator divide" "/1,/2,/4,/8" bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode (data into: entropy shifter / statistical checker)" "Von Neumann both,Raw data both,Von Neumann/Raw data,?..." endif if (((per.l(ad:0x400A0000))&0x10000)==0x00) hgroup.long 0x04++0x03 hide.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register" hgroup.long 0x08++0x03 hide.long 0x00 "PKRRNG,TRNG Poker Range Register" rgroup.long 0x0C++0x03 line.long 0x00 "PKRSQ,TRNG Poker Square Calculation Result Register" hexmask.long.tbyte 0x00 0.--23. 1. " PKR_SQ ,Poker square calculation result" hgroup.long 0x10++0x03 hide.long 0x00 "SDCTL,TRNG Seed Control Register" rgroup.long 0x14++0x03 line.long 0x00 "TOTSAM,Total Samples Register" hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples" hgroup.long 0x18++0x03 hide.long 0x00 "FRQMIN,TRNG Frequency Count Minimum Limit Register" if (((per.l(ad:0x400A0000))&0x20)==0x20) rgroup.long 0x1C++0x03 line.long 0x00 "FRQCNT,TRNG Frequency Count Register" hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_CNT ,Frequency count" else hgroup.long 0x1C++0x03 hide.long 0x00 "FRQCNT,TRNG Frequency Count Register" endif rgroup.long 0x20++0x1B line.long 0x00 "SCMC,TRNG Statistical Check Monobit Count Register" hexmask.long.word 0x00 0.--15. 1. " MONO_CNT ,Monobit count" line.long 0x04 "SCR1C,TRNG Statistical Check Run Length 1 Count Register" hexmask.long.word 0x04 16.--30. 1. " R1_1_COUNT ,Runs of one (length 1 count)" hexmask.long.word 0x04 0.--14. 1. " R1_0_COUNT ,Runs of zero (length 1 count)" line.long 0x08 "SCR2C,TRNG Statistical Check Run Length 2 Count Register" hexmask.long.word 0x08 16.--29. 1. " R2_1_COUNT ,Runs of one (length 2 count)" hexmask.long.word 0x08 0.--13. 1. " R2_0_COUNT ,Runs of zero (length 2 count)" line.long 0x0C "SCR3C,TRNG Statistical Check Run Length 3 Count Register" hexmask.long.word 0x0C 16.--28. 1. " R3_1_COUNT ,Runs of ones (length 3 count)" hexmask.long.word 0x0C 0.--12. 1. " R3_0_COUNT ,Runs of zeroes (length 3 count)" line.long 0x10 "SCR4C,TRNG Statistical Check Run Length 4 Count Register" hexmask.long.word 0x10 16.--27. 1. " R4_1_COUNT ,Runs of one (length 4 count)" hexmask.long.word 0x10 0.--11. 1. " R4_0_COUNT ,Runs of zero (length 4 count)" line.long 0x14 "SCR5C,TRNG Statistical Check Run Length 5 Count Register" hexmask.long.word 0x14 16.--26. 1. " R5_1_COUNT ,Runs of one (length 5 count)" hexmask.long.word 0x14 0.--10. 1. " R5_0_COUNT ,Runs of zero (length 5 count)" line.long 0x18 "SCR6PC,TRNG Statistical Check Run Length 6+ Count Register" hexmask.long.word 0x18 16.--26. 1. " R6P_1_COUNT ,Runs of one (length 6+ count)" hexmask.long.word 0x18 0.--10. 1. " R6P_0_COUNT ,Runs of zero (length 6+ count)" else group.long 0x04++0x37 line.long 0x00 "SCMISC,TRNG Statistical Check Miscellaneous Register" bitfld.long 0x00 16.--19. " RTY_CNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " LRUN_MAX ,Long run max limit" line.long 0x04 "PKRRNG,TRNG Poker Range Register" hexmask.long.word 0x04 0.--15. 1. " PKR_RNG ,Poker range" line.long 0x08 "PKRMAX,TRNG Poker Maximum Limit Register" hexmask.long.tbyte 0x08 0.--23. 1. " PKR_MAX ,Poker maximum limit" line.long 0x0C "SDCTL,TRNG Seed Control Register" hexmask.long.word 0x0C 16.--31. 1. " ENT_DLY ,Entropy delay" hexmask.long.word 0x0C 0.--15. 1. " SAMP_SIZE ,Sample size" line.long 0x10 "SBLIM,TRNG Sparse Bit Limit Register" hexmask.long.word 0x10 0.--9. 1. " SB_LIM ,Sparse bit limit" line.long 0x14 "FRQMIN,TRNG Frequency Count Minimum Limit Register" hexmask.long.tbyte 0x14 0.--21. 1. " FRQ_MIN ,Frequency Count minimum limit" line.long 0x18 "FRQMAX,TRNG Frequency Count Maximum Limit Register" hexmask.long.tbyte 0x18 0.--21. 1. " FRQ_MAX ,Frequency Counter maximum limit" line.long 0x1C "SCML,TRNG Statistical Check Monobit Limit Register" hexmask.long.word 0x1C 16.--31. 1. " MONO_RNG ,Monobit range" hexmask.long.word 0x1C 0.--15. 1. " MONO_MAX ,Monobit maximum limit" line.long 0x20 "SCR1L,TRNG Statistical Check Run Length 1 Limit Register" hexmask.long.word 0x20 16.--30. 1. " RUN1_RNG ,Run length 1 range" hexmask.long.word 0x20 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit" line.long 0x24 "SCR2L,TRNG Statistical Check Run Length 2 Limit Register" hexmask.long.word 0x24 16.--29. 1. " RUN2_RNG ,Run length 2 range" hexmask.long.word 0x24 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit" line.long 0x28 "SCR3L,TRNG Statistical Check Run Length 3 Limit Register" hexmask.long.word 0x28 16.--28. 1. " RUN3_RNG ,Run length 3 range" hexmask.long.word 0x28 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit" line.long 0x2C "SCR4L,TRNG Statistical Check Run Length 4 Limit Register" hexmask.long.word 0x2C 16.--27. 1. " RUN4_RNG ,Run length 4 range" hexmask.long.word 0x2C 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit" line.long 0x30 "SCR5L,TRNG Statistical Check Run Length 5 Limit Register" hexmask.long.word 0x30 16.--26. 1. " RUN5_RNG ,Run length 5 range" hexmask.long.word 0x30 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit" line.long 0x34 "SCR6PL,TRNG Statistical Check Run Length 6+ Limit Register" hexmask.long.word 0x34 16.--26. 1. " RUN6P_RNG ,Run length 6+ range" hexmask.long.word 0x34 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit" endif if (((per.l(ad:0x400A0000))&0x10000)==0x10000) hgroup.long 0x3C++0x03 hide.long 0x00 "STATUS,TRNG Status Register" else rgroup.long 0x3C++0x03 line.long 0x00 "STATUS,TRNG Status Register" bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " TFMB ,Mono bit test fail" "Not failed,Failed" bitfld.long 0x00 14. " TFP ,Poker test fail" "Not failed,Failed" newline bitfld.long 0x00 13. " TFLR ,Long run test fail" "Not failed,Failed" bitfld.long 0x00 12. " TFSB ,Sparse bit test fail" "Not failed,Failed" bitfld.long 0x00 11. " TF6PBR1 ,6 Plus bit run (sampling 1s) test fail" "Not failed,Failed" newline bitfld.long 0x00 10. " TF6PBR0 ,6 Plus bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 9. " TF5BR1 ,5-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 8. " TF5BR0 ,5-bit run (sampling 0s) test fail" "Not failed,Failed" newline bitfld.long 0x00 7. " TF4BR1 ,4-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 6. " TF4BR0 ,4-bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 5. " TF3BR1 ,3-bit run (sampling 1s) test fail" "Not failed,Failed" newline bitfld.long 0x00 4. " TF3BR0 ,3-bit run (sampling 0s) test fail" "Not failed,Failed" bitfld.long 0x00 3. " TF2BR1 ,2-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 2. " TF2BR0 ,2-bit run (sampling 0s) test fail" "Not failed,Failed" newline bitfld.long 0x00 1. " TF1BR1 ,1-bit run (sampling 1s) test fail" "Not failed,Failed" bitfld.long 0x00 0. " TF1BR0 ,1-bit run (sampling 0s) test fail" "Not failed,Failed" endif sif (cpuis("IMX7ULP-CM4")||cpuis("IMX7ULP-CM4")) if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x40++0x03 line.long 0x00 "ENT0,TRNG Entropy Read Register 0" else hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x44++0x03 line.long 0x00 "ENT1,TRNG Entropy Read Register 1" else hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x48++0x03 line.long 0x00 "ENT2,TRNG Entropy Read Register 2" else hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x4C++0x03 line.long 0x00 "ENT3,TRNG Entropy Read Register 3" else hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x50++0x03 line.long 0x00 "ENT4,TRNG Entropy Read Register 4" else hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x54++0x03 line.long 0x00 "ENT5,TRNG Entropy Read Register 5" else hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x58++0x03 line.long 0x00 "ENT6,TRNG Entropy Read Register 6" else hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x5C++0x03 line.long 0x00 "ENT7,TRNG Entropy Read Register 7" else hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x60++0x03 line.long 0x00 "ENT8,TRNG Entropy Read Register 8" else hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x64++0x03 line.long 0x00 "ENT9,TRNG Entropy Read Register 9" else hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x68++0x03 line.long 0x00 "ENT10,TRNG Entropy Read Register 10" else hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x6C++0x03 line.long 0x00 "ENT11,TRNG Entropy Read Register 11" else hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x70++0x03 line.long 0x00 "ENT12,TRNG Entropy Read Register 12" else hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x74++0x03 line.long 0x00 "ENT13,TRNG Entropy Read Register 13" else hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) rgroup.long 0x78++0x03 line.long 0x00 "ENT14,TRNG Entropy Read Register 14" else hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" in else hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" endif else if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" in else hgroup.long 0x40++0x03 hide.long 0x00 "ENT0,TRNG Entropy Read Register 0" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" in else hgroup.long 0x44++0x03 hide.long 0x00 "ENT1,TRNG Entropy Read Register 1" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" in else hgroup.long 0x48++0x03 hide.long 0x00 "ENT2,TRNG Entropy Read Register 2" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" in else hgroup.long 0x4C++0x03 hide.long 0x00 "ENT3,TRNG Entropy Read Register 3" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" in else hgroup.long 0x50++0x03 hide.long 0x00 "ENT4,TRNG Entropy Read Register 4" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" in else hgroup.long 0x54++0x03 hide.long 0x00 "ENT5,TRNG Entropy Read Register 5" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" in else hgroup.long 0x58++0x03 hide.long 0x00 "ENT6,TRNG Entropy Read Register 6" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" in else hgroup.long 0x5C++0x03 hide.long 0x00 "ENT7,TRNG Entropy Read Register 7" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" in else hgroup.long 0x60++0x03 hide.long 0x00 "ENT8,TRNG Entropy Read Register 8" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" in else hgroup.long 0x64++0x03 hide.long 0x00 "ENT9,TRNG Entropy Read Register 9" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" in else hgroup.long 0x68++0x03 hide.long 0x00 "ENT10,TRNG Entropy Read Register 10" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" in else hgroup.long 0x6C++0x03 hide.long 0x00 "ENT11,TRNG Entropy Read Register 11" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" in else hgroup.long 0x70++0x03 hide.long 0x00 "ENT12,TRNG Entropy Read Register 12" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" in else hgroup.long 0x74++0x03 hide.long 0x00 "ENT13,TRNG Entropy Read Register 13" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" in else hgroup.long 0x78++0x03 hide.long 0x00 "ENT14,TRNG Entropy Read Register 14" endif if (((per.l(ad:0x400A0000))&0x10420)==0x420) hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" in else hgroup.long 0x7C++0x03 hide.long 0x00 "ENT15,TRNG Entropy Read Register 15" endif endif if (((per.l(ad:0x400A0000))&0x10000)==0x0) rgroup.long 0x80++0x03 line.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_1_CT ,Poker 1h count" hexmask.long.word 0x00 0.--15. 1. " PKR_0_CT ,Poker 0h count" rgroup.long 0x84++0x03 line.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_3_CT ,Poker 3h count" hexmask.long.word 0x00 0.--15. 1. " PKR_2_CT ,Poker 2h count" rgroup.long 0x88++0x03 line.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_5_CT ,Poker 5h count" hexmask.long.word 0x00 0.--15. 1. " PKR_4_CT ,Poker 4h count" rgroup.long 0x8C++0x03 line.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_7_CT ,Poker 7h count" hexmask.long.word 0x00 0.--15. 1. " PKR_6_CT ,Poker 6h count" rgroup.long 0x90++0x03 line.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_9_CT ,Poker 9h count" hexmask.long.word 0x00 0.--15. 1. " PKR_8_CT ,Poker 8h count" rgroup.long 0x94++0x03 line.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register" hexmask.long.word 0x00 16.--31. 1. " PKR_B_CT ,Poker Bh count" hexmask.long.word 0x00 0.--15. 1. " PKR_A_CT ,Poker Ah count" rgroup.long 0x98++0x03 line.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register" hexmask.long.word 0x00 16.--31. 1. " PKR_D_CT ,Poker Dh count" hexmask.long.word 0x00 0.--15. 1. " PKR_C_CT ,Poker Ch count" rgroup.long 0x9C++0x03 line.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register" hexmask.long.word 0x00 16.--31. 1. " PKR_F_CT ,Poker Fh count" hexmask.long.word 0x00 0.--15. 1. " PKR_E_CT ,Poker Eh count" else hgroup.long 0x80++0x03 hide.long 0x00 "PKRCNT10,TRNG Statistical Check Poker Count 1 And 0 Register" hgroup.long 0x84++0x03 hide.long 0x00 "PKRCNT32,TRNG Statistical Check Poker Count 3 And 2 Register" hgroup.long 0x88++0x03 hide.long 0x00 "PKRCNT54,TRNG Statistical Check Poker Count 5 And 4 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "PKRCNT76,TRNG Statistical Check Poker Count 7 And 6 Register" hgroup.long 0x90++0x03 hide.long 0x00 "PKRCNT98,TRNG Statistical Check Poker Count 9 And 8 Register" hgroup.long 0x94++0x03 hide.long 0x00 "PKRCNTBA,TRNG Statistical Check Poker Count B And A Register" hgroup.long 0x98++0x03 hide.long 0x00 "PKRCNTDC,TRNG Statistical Check Poker Count D And C Register" hgroup.long 0x9C++0x03 hide.long 0x00 "PKRCNTFE,TRNG Statistical Check Poker Count F And E Register" endif sif (cpuis("MK8?FN256V*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) group.long 0xB0++0x0F line.long 0x00 "SEC_CFG,TRNG Security Configuration Register" bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes" line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register" bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active" bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active" bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active" line.long 0x08 "INT_MASK,TRNG Mask Register" bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked" bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked" line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register" bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid" rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error" else group.long 0xA0++0x0F line.long 0x00 "SEC_CFG,TRNG Security Configuration Register" bitfld.long 0x00 1. " NO_PRGM ,TRNG registers cannot be programmed" "No,Yes" line.long 0x04 "INT_CTRL,TRNG Interrupt Control Register" bitfld.long 0x04 2. " FRQ_CT_FAIL ,Frequency count fail interrupt control status" "Cleared,Active" bitfld.long 0x04 1. " ENT_VAL ,Entropy valid interrupt control status" "Cleared,Active" bitfld.long 0x04 0. " HW_ERR ,HW error interrupt control status" "Cleared,Active" line.long 0x08 "INT_MASK,TRNG Mask Register" bitfld.long 0x08 2. " FRQ_CT_FAIL ,Frequency count fail interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " ENT_VAL ,Entropy valid interrupt mask" "Masked,Not masked" bitfld.long 0x08 0. " HW_ERR ,HW error interrupt mask" "Masked,Not masked" line.long 0x0C "INT_STATUS,TRNG Interrupt Status Register" sif (cpuis("K32W0?2S1M*")||cpuis("IMX7ULP-CA7")||cpuis("IMX7ULP-CM4")) rbitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" else bitfld.long 0x0C 2. " FRQ_CT_FAIL ,Frequency count fail interrupt status" "Not failed,Failed" endif newline rbitfld.long 0x0C 1. " ENT_VAL ,Entropy valid interrupt status" "Invalid,Valid" rbitfld.long 0x0C 0. " HW_ERR ,HW error interrupt status" "No error,Error" endif rgroup.long 0xF0++0x07 line.long 0x00 "VID1,Version ID (MS) Register" hexmask.long.word 0x00 16.--31. 1. " TRNG_IP_ID ,Shows IP ID" hexmask.long.byte 0x00 8.--15. 1. " TRNG_MAJ_REV ,Shows IP's major revision of the TRNG" hexmask.long.byte 0x00 0.--7. 1. " TRNG_MIN_REV ,Shows IP's minor revision of the TRNG" line.long 0x04 "VID2,Version ID (LS) Register" hexmask.long.byte 0x04 24.--31. 1. " TRNG_ERA ,Shows compile options for the TRNG" hexmask.long.byte 0x04 16.--23. 1. " TRNG_INTG_OPT ,Shows integration options for the TRNG" hexmask.long.byte 0x04 8.--15. 1. " TRNG_ECO_REV ,Shows IP's ECO revision of the TRNG" newline hexmask.long.byte 0x04 0.--7. 1. " TRNG_CONFIG_OPT ,Shows IP's Configuration options for the TRNG" width 0x0B tree.end tree "ADC (Analog-to-Digital Converter)" tree "ADC0" base ad:0x4003BA000 width 15. if (((per.l(ad:0x4003B000+0x0))&0x20)==0x0) group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "ADC0_SC1A,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000+0x4))&0x20)==0x0) group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1,DP2,,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,,,,SE9,SE10,,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,DP2,DP3,SE4a,SE5a,SE6a,SE7a,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,,,,,,,,12-bit DAC0 Output,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor (SE),Bandgap (SE),,VRESH,VRESL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "ADC0_SC1B,ADC status and control registers 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" newline sif (cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",DP1/DM1,DP2/DM2,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (diff),,-VREFH,,Disabled" elif (cpuis("MKV5?F512VLQ24")||cpuis("MKV5?F512VMD24")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (SE),Bandgap (SE),,VREFH,VREFL,Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (diff),Bandgap (diff),,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003B000))&0x20)==0x0) group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "SE 8-bit,SE 12-bit,SE 10-bit,SE 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "ADC0_CFG1,ADC configuration register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock Divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Diff 9-bit,Diff 13-bit,Diff 11-bit,Diff 16-bit" sif (cpuis("MKV5*")) newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "ADC0_CFG2,ADC Configuration register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long Sample time select" "24ADCK cycles,16ADCK cycles,10ADCK cycles,6ADCK cycles" rgroup.long 0x10++0x07 line.long 0x00 "ADC0_RA,ADC data result register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "ADC0_RB,ADC data result register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" group.long 0x18++0x37 line.long 0x00 "ADC0_CV1,Compare value registers" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare Value" line.long 0x04 "ADC0_CV2,Compare value registers" hexmask.long.word 0x04 0.--15. 1. " CV ,Compare Value" line.long 0x08 "ADC0_SC2,Status and control register 2" rbitfld.long 0x08 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x08 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x08 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x08 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x08 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x08 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x0C "ADC0_SC3,Status and control register 3" bitfld.long 0x0C 7. " CAL ,Calibration" "Not started,Started" sif (cpuis("MKV5*")) newline eventfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" else newline rbitfld.long 0x0C 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" endif newline bitfld.long 0x0C 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" bitfld.long 0x0C 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x0C 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x10 "ADC0_OFS,ADC offset correction register" hexmask.long.word 0x10 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x14 "ADC0_PG,ADC plus-side gain register" hexmask.long.word 0x14 0.--15. 1. " PG ,Plus-side gain" line.long 0x18 "ADC0_MG,ADC minus-side gain register" hexmask.long.word 0x18 0.--15. 1. " MG ,Minus-side Gain" line.long 0x1C "ADC0_CLPD,ADC plus-side general calibration value register" bitfld.long 0x1C 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x20 "ADC0_CLPS,ADC plus-side general calibration value register" bitfld.long 0x20 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "ADC0_CLP4,ADC plus-side general calibration value register" hexmask.long.word 0x24 0.--9. 1. " CLP4 ,Calibration value" line.long 0x28 "ADC0_CLP3,ADC plus-side general calibration value register" hexmask.long.word 0x28 0.--8. 1. " CLP3 ,Calibration value" line.long 0x2C "ADC0_CLP2,ADC plus-side general calibration value register" hexmask.long.byte 0x2C 0.--7. 1. " CLP2 ,Calibration value" line.long 0x30 "ADC0_CLP1,ADC plus-side general calibration value register" hexmask.long.byte 0x30 0.--6. 1. " CLP1 ,Calibration value" line.long 0x34 "ADC0_CLP0,ADC plus-side general calibration value register" bitfld.long 0x34 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x54++0x1B line.long 0x00 "ADC0_CLMD,ADC minus-side general calibration value register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ADC0_CLMS,ADC minus-side general calibration value register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ADC0_CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "ADC0_CLM3,CLM4,ADC minus-side general calibration value register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "ADC0_CLM2,ADC minus-side general calibration value register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "ADC0_CLM1,ADC minus-side general calibration value register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "ADC0_CLM0,ADC minus-side general calibration value register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree.end tree.open "HSADC (12-bit 5MSPS Analog-to-Digital Converter)" tree "HSADC0" base ad:0x4005C000 width 11. group.word 0x00++0x07 line.word 0x00 "CTRL1,HSADC Control Register 1" bitfld.word 0x00 15. " DMAENA ,DMA enable" "Disabled,Enabled" bitfld.word 0x00 14. " STOPA ,Stop" "Normal,Stopped" bitfld.word 0x00 13. " STARTA ,Start conversion" "No effect,Start" bitfld.word 0x00 12. " SYNCA ,Sync A enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " EOSIEA ,End of scan interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " ZCIE ,Zero crossing interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " LLMTIE ,Low limit interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " HLMTIE ,High limit interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CHNCFG_L[3] ,CHCNF (channel configure low) bits" "ANB2/3-single,ANB2/3-differential" bitfld.word 0x00 6. " [2] ,CHCNF (channel configure low) bits" "ANB0/1-single,ANB0/1-differential" bitfld.word 0x00 5. " [1] ,CHCNF (channel configure low) bits" "ANA2/3-single,ANA2/3-differential" bitfld.word 0x00 4. " [0] ,CHCNF (channel configure low) bits" "ANA0/1-single,ANA0/1-differential" textline " " bitfld.word 0x00 0.--2. " SMODE ,ADC scan mode control" "Once sequential,Once parallel,Loop sequential,Loop parallel,Triggered sequential,Triggered parallel,?..." line.word 0x02 "CTRL2,HSADC Control Register 2" bitfld.word 0x02 15. " DMAENB ,DMA enable" "Disabled,Enabled" bitfld.word 0x02 14. " STOPB ,Stop" "Normal,Stopped" bitfld.word 0x02 13. " STARTB ,Start conversion" "No effect,Start" bitfld.word 0x02 12. " SYNCB ,Syncb enable" "Disabled,Enabled" textline " " bitfld.word 0x02 11. " EOSIEB ,End of scan interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " CHNCFG_H[3] ,CHCNF (channel configure high) bits" "ANB6/7-single,ANB6/7-differential" bitfld.word 0x02 9. " [2] ,CHCNF (channel configure high) bits" "ANB4/5-single,ANB4/5-differential" bitfld.word 0x02 8. " [1] ,CHCNF (channel configure high) bits" "ANA6/7-single,ANA6/7-differential" bitfld.word 0x02 7. " [0] ,CHCNF (channel configure high) bits" "ANA4/5-single,ANA4/5-differential" textline " " bitfld.word 0x02 6. " SIMULT ,Simultaneous mode" "Independently,Simultaneously" bitfld.word 0x02 0.--5. " DIVA ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.word 0x04 "ZXCTRL1,HSADC Zero Crossing Control 1 Register" bitfld.word 0x04 14.--15. " ZCE7 ,Zero crossing enable 7" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 12.--13. " ZCE6 ,Zero crossing enable 6" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 10.--11. " ZCE5 ,Zero crossing enable 5" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 8.--9. " ZCE4 ,Zero crossing enable 4" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " bitfld.word 0x04 6.--7. " ZCE3 ,Zero crossing enable 3" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 4.--5. " ZCE2 ,Zero crossing enable 2" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 2.--3. " ZCE1 ,Zero crossing enable 1" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 0.--1. " ZCE0 ,Zero crossing enable 0" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" line.word 0x06 "ZXCTRL2,HSADC Zero Crossing Control 2 Register" bitfld.word 0x06 14.--15. " ZCE15 ,Zero crossing enable 15" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 12.--13. " ZCE14 ,Zero crossing enable 14" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 10.--11. " ZCE13 ,Zero crossing enable 13" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 8.--9. " ZCE12 ,Zero crossing enable 12" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " bitfld.word 0x06 6.--7. " ZCE11 ,Zero crossing enable 11" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 4.--5. " ZCE10 ,Zero crossing enable 10" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 2.--3. " ZCE9 ,Zero crossing enable 9" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 0.--1. " ZCE8 ,Zero crossing enable 8" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " group.word 0x08++0x07 line.word 0x00 "CLIST1,HSADC Channel List Register 1" bitfld.word 0x00 12.--15. " SAMPLE3 ,Sample field 3" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x00 8.--11. " SAMPLE2 ,Sample field 2" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x00 4.--7. " SAMPLE1 ,Sample field 1" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x00 0.--3. " SAMPLE0 ,Sample field 0" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x02 "CLIST2,HSADC Channel List Register 2" bitfld.word 0x02 12.--15. " SAMPLE7 ,Sample field 7" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x02 8.--11. " SAMPLE6 ,Sample field 6" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x02 4.--7. " SAMPLE5 ,Sample field 5" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x02 0.--3. " SAMPLE4 ,Sample field 4" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x04 "CLIST3,HSADC Channel List Register 3" bitfld.word 0x04 12.--15. " SAMPLE11 ,Sample field 11" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x04 8.--11. " SAMPLE10 ,Sample field 10" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x04 4.--7. " SAMPLE9 ,Sample field 9" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x04 0.--3. " SAMPLE8 ,Sample field 8" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x06 "CLIST4,HSADC Channel List Register 4" bitfld.word 0x06 12.--15. " SAMPLE15 ,Sample field 15" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x06 8.--11. " SAMPLE14 ,Sample field 14" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x06 4.--7. " SAMPLE13 ,Sample field 13" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x06 0.--3. " SAMPLE12 ,Sample field 12" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " group.word 0x10++0x03 line.word 0x00 "SDIS,HSADC Sample Disable Register" bitfld.word 0x00 15. " DS[15] ,Disable sample bit 15" "No,Yes" bitfld.word 0x00 14. " [14] ,Disable sample bit 14" "No,Yes" bitfld.word 0x00 13. " [13] ,Disable sample bit 13" "No,Yes" bitfld.word 0x00 12. " [12] ,Disable sample bit 12" "No,Yes" textline " " bitfld.word 0x0 11. " [11] ,Disable sample bit 11" "No,Yes" bitfld.word 0x00 10. " [10] ,Disable sample bit 10" "No,Yes" bitfld.word 0x00 9. " [9] ,Disable sample bit 9" "No,Yes" bitfld.word 0x00 8. " [8] ,Disable sample bit 8" "No,Yes" textline " " bitfld.word 0x00 7. " [7] ,Disable sample bit 7" "No,Yes" bitfld.word 0x00 6. " [6] ,Disable sample bit 6" "No,Yes" bitfld.word 0x00 5. " [5] ,Disable sample bit 5" "No,Yes" bitfld.word 0x00 4. " [4] ,Disable sample bit 4" "No,Yes" textline " " bitfld.word 0x00 3. " [3] ,Disable sample bit 3" "No,Yes" bitfld.word 0x00 2. " [2] ,Disable sample bit 2" "No,Yes" bitfld.word 0x00 1. " [1] ,Disable sample bit 1" "No,Yes" bitfld.word 0x00 0. " [0] ,Disable sample bit 0" "No,Yes" line.word 0x02 "STAT,HSADC Status Register" rbitfld.word 0x02 15. " CIPA ,Conversion in progress" "Idle,Active" rbitfld.word 0x02 14. " CIPB ,Conversion in progress" "Idle,Active" eventfld.word 0x02 12. " EOSIB ,End of scan interrupt" "Not completed,Completed" eventfld.word 0x02 11. " EOSIA ,End of scan interrupt" "Not completed,Completed" textline " " rbitfld.word 0x02 10. " ZCI ,Zero crossing interrupt" "Not requested,Requested" rbitfld.word 0x02 9. " LLMTI ,Low limit interrupt" "Not requested,Requested" rbitfld.word 0x02 8. " HLMTI ,High limit interrupt" "Not requested,Requested" eventfld.word 0x02 5. " EOCALIB ,End of calibration on ADCB interrupt" "No interrupt,Interrupt" textline " " eventfld.word 0x02 4. " EOCALIA ,End of calibration on ADCA interrupt" "No interrupt,Interrupt" rbitfld.word 0x02 3. " DUMMYB ,Dummy conversion running on HSADCB" "Not running,Running" rbitfld.word 0x02 2. " DUMMYA ,Dummy conversion running on HSADCA" "Not running,Running" rbitfld.word 0x02 1. " CALONB ,HSADCB calibration execution status" "Not running,Running" textline " " rbitfld.word 0x02 0. " CALONA ,HSADCA calibration execution status" "Not running,Running" rgroup.word 0x14++0x01 line.word 0x00 "RDY,HSADC Ready Register" bitfld.word 0x00 15. " RDY[15] ,Ready sample 15" "Not ready,Ready" bitfld.word 0x00 14. " [14] ,Ready sample 14" "Not ready,Ready" bitfld.word 0x00 13. " [13] ,Ready sample 13" "Not ready,Ready" textline " " bitfld.word 0x00 12. " [12] ,Ready sample 12" "Not ready,Ready" bitfld.word 0x00 11. " [11] ,Ready sample 11" "Not ready,Ready" bitfld.word 0x00 10. " [10] ,Ready sample 10" "Not ready,Ready" textline " " bitfld.word 0x00 9. " [9] ,Ready sample 9" "Not ready,Ready" bitfld.word 0x00 8. " [8] ,Ready sample 8" "Not ready,Ready" bitfld.word 0x00 7. " [7] ,Ready sample 7" "Not ready,Ready" textline " " bitfld.word 0x00 6. " [6] ,Ready sample 6" "Not ready,Ready" bitfld.word 0x00 5. " [5] ,Ready sample 5" "Not ready,Ready" bitfld.word 0x00 4. " [4] ,Ready sample 4" "Not ready,Ready" textline " " bitfld.word 0x00 3. " [3] ,Ready sample 3" "Not ready,Ready" bitfld.word 0x00 2. " [2] ,Ready sample 2" "Not ready,Ready" bitfld.word 0x00 1. " [1] ,Ready sample 1" "Not ready,Ready" textline " " bitfld.word 0x00 0. " [0] ,Ready sample 0" "Not ready,Ready" group.word 0x16++0x97 line.word 0x00 "LOLIMSTAT,HSADC Low Limit Status Register" eventfld.word 0x00 15. " LLS[15] ,Low limit status bits 15" "Not lower,Lower" eventfld.word 0x00 14. " [14] ,Low limit status bits 14" "Not lower,Lower" eventfld.word 0x00 13. " [13] ,Low limit status bits 13" "Not lower,Lower" eventfld.word 0x00 12. " [12] ,Low limit status bits 12" "Not lower,Lower" textline " " eventfld.word 0x00 11. " [11] ,Low limit status bits 11" "Not lower,Lower" eventfld.word 0x00 10. " [10] ,Low limit status bits 10" "Not lower,Lower" eventfld.word 0x00 9. " [9] ,Low limit status bits 9" "Not lower,Lower" eventfld.word 0x00 8. " [8] ,Low limit status bits 8" "Not lower,Lower" textline " " eventfld.word 0x00 7. " [7] ,Low limit status bits 7" "Not lower,Lower" eventfld.word 0x00 6. " [6] ,Low limit status bits 6" "Not lower,Lower" eventfld.word 0x00 5. " [5] ,Low limit status bits 5" "Not lower,Lower" eventfld.word 0x00 4. " [4] ,Low limit status bits 4" "Not lower,Lower" textline " " eventfld.word 0x00 3. " [3] ,Low limit status bits 3" "Not lower,Lower" eventfld.word 0x00 2. " [2] ,Low limit status bits 2" "Not lower,Lower" eventfld.word 0x00 1. " [1] ,Low limit status bits 1" "Not lower,Lower" eventfld.word 0x00 0. " [0] ,Low limit status bits 0" "Not lower,Lower" line.word 0x02 "HILIMSTAT,HSADC High Limit Status Register" eventfld.word 0x02 15. " HLS[15] ,High limit status bits 15" "Not higher,Higher" eventfld.word 0x02 14. " [14] ,High limit status bits 14" "Not higher,Higher" eventfld.word 0x02 13. " [13] ,High limit status bits 13" "Not higher,Higher" eventfld.word 0x02 12. " [12] ,High limit status bits 12" "Not higher,Higher" textline " " eventfld.word 0x02 11. " [11] ,High limit status bits 11" "Not higher,Higher" eventfld.word 0x02 10. " [10] ,High limit status bits 10" "Not higher,Higher" eventfld.word 0x02 9. " [9] ,High limit status bits 9" "Not higher,Higher" eventfld.word 0x02 8. " [8] ,High limit status bits 8" "Not higher,Higher" textline " " eventfld.word 0x02 7. " [7] ,High limit status bits 7" "Not higher,Higher" eventfld.word 0x02 6. " [6] ,High limit status bits 6" "Not higher,Higher" eventfld.word 0x02 5. " [5] ,High limit status bits 5" "Not higher,Higher" eventfld.word 0x02 4. " [4] ,High limit status bits 4" "Not higher,Higher" textline " " eventfld.word 0x02 3. " [3] ,High limit status bits 3" "Not higher,Higher" eventfld.word 0x02 2. " [2] ,High limit status bits 2" "Not higher,Higher" eventfld.word 0x02 1. " [1] ,High limit status bits 1" "Not higher,Higher" eventfld.word 0x02 0. " [0] ,High limit status bits 0" "Not higher,Higher" line.word 0x04 "ZXSTAT,HSADC Zero Crossing Status Register" eventfld.word 0x04 15. " ZCS[15] ,Zero crossing status 15" "Not crossed,Crossed" eventfld.word 0x04 14. " [14] ,Zero crossing status 14" "Not crossed,Crossed" eventfld.word 0x04 13. " [13] ,Zero crossing status 13" "Not crossed,Crossed" eventfld.word 0x04 12. " [12] ,Zero crossing status 12" "Not crossed,Crossed" textline " " eventfld.word 0x04 11. " [11] ,Zero crossing status 11" "Not crossed,Crossed" eventfld.word 0x04 10. " [10] ,Zero crossing status 10" "Not crossed,Crossed" eventfld.word 0x04 9. " [9] ,Zero crossing status 9" "Not crossed,Crossed" eventfld.word 0x04 8. " [8] ,Zero crossing status 8" "Not crossed,Crossed" textline " " eventfld.word 0x04 7. " [7] ,Zero crossing status 7" "Not crossed,Crossed" eventfld.word 0x04 6. " [6] ,Zero crossing status 6" "Not crossed,Crossed" eventfld.word 0x04 5. " [5] ,Zero crossing status 5" "Not crossed,Crossed" eventfld.word 0x04 4. " [4] ,Zero crossing status 4" "Not crossed,Crossed" textline " " eventfld.word 0x04 3. " [3] ,Zero crossing status 3" "Not crossed,Crossed" eventfld.word 0x04 2. " [2] ,Zero crossing status 2" "Not crossed,Crossed" eventfld.word 0x04 1. " [1] ,Zero crossing status 1" "Not crossed,Crossed" eventfld.word 0x04 0. " [0] ,Zero crossing status 0" "Not crossed,Crossed" group.word 0x1E++0x01 line.word 0x00 "RSLT0,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x20++0x01 line.word 0x00 "RSLT1,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x22++0x01 line.word 0x00 "RSLT2,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x24++0x01 line.word 0x00 "RSLT3,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x26++0x01 line.word 0x00 "RSLT4,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x28++0x01 line.word 0x00 "RSLT5,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2A++0x01 line.word 0x00 "RSLT6,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2C++0x01 line.word 0x00 "RSLT7,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2E++0x01 line.word 0x00 "RSLT8,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x30++0x01 line.word 0x00 "RSLT9,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x32++0x01 line.word 0x00 "RSLT10,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x34++0x01 line.word 0x00 "RSLT11,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x36++0x01 line.word 0x00 "RSLT12,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x38++0x01 line.word 0x00 "RSLT13,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3A++0x01 line.word 0x00 "RSLT14,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3C++0x01 line.word 0x00 "RSLT15,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3C++0x01 line.word 0x00 "LOLIM0,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x3E++0x01 line.word 0x00 "LOLIM1,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x40++0x01 line.word 0x00 "LOLIM2,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x42++0x01 line.word 0x00 "LOLIM3,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x44++0x01 line.word 0x00 "LOLIM4,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x46++0x01 line.word 0x00 "LOLIM5,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x48++0x01 line.word 0x00 "LOLIM6,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4A++0x01 line.word 0x00 "LOLIM7,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4C++0x01 line.word 0x00 "LOLIM8,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4E++0x01 line.word 0x00 "LOLIM9,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x50++0x01 line.word 0x00 "LOLIM10,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x52++0x01 line.word 0x00 "LOLIM11,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x54++0x01 line.word 0x00 "LOLIM12,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x56++0x01 line.word 0x00 "LOLIM13,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x58++0x01 line.word 0x00 "LOLIM14,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5A++0x01 line.word 0x00 "LOLIM15,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5C++0x01 line.word 0x00 "HILIM0,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x5E++0x01 line.word 0x00 "HILIM1,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x60++0x01 line.word 0x00 "HILIM2,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x62++0x01 line.word 0x00 "HILIM3,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x64++0x01 line.word 0x00 "HILIM4,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x66++0x01 line.word 0x00 "HILIM5,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x68++0x01 line.word 0x00 "HILIM6,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6A++0x01 line.word 0x00 "HILIM7,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6C++0x01 line.word 0x00 "HILIM8,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6E++0x01 line.word 0x00 "HILIM9,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x70++0x01 line.word 0x00 "HILIM10,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x72++0x01 line.word 0x00 "HILIM11,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x74++0x01 line.word 0x00 "HILIM12,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x76++0x01 line.word 0x00 "HILIM13,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x78++0x01 line.word 0x00 "HILIM14,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7A++0x01 line.word 0x00 "HILIM15,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7C++0x01 line.word 0x00 "OFFST0,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x7E++0x01 line.word 0x00 "OFFST1,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x80++0x01 line.word 0x00 "OFFST2,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x82++0x01 line.word 0x00 "OFFST3,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x84++0x01 line.word 0x00 "OFFST4,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x86++0x01 line.word 0x00 "OFFST5,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x88++0x01 line.word 0x00 "OFFST6,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8A++0x01 line.word 0x00 "OFFST7,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8C++0x01 line.word 0x00 "OFFST8,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8E++0x01 line.word 0x00 "OFFST9,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x90++0x01 line.word 0x00 "OFFST10,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x92++0x01 line.word 0x00 "OFFST11,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x94++0x01 line.word 0x00 "OFFST12,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x96++0x01 line.word 0x00 "OFFST13,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x98++0x01 line.word 0x00 "OFFST14,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x9A++0x01 line.word 0x00 "OFFST15,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x9C++0x01 line.word 0x00 "PWR,HSADC Power Control Register" bitfld.word 0x00 15. " ASB ,Auto standby" "Disabled,Enabled" rbitfld.word 0x00 11. " PSTSB ,ADC converter B power status" "Powered Up,Powered Down" rbitfld.word 0x00 10. " PSTSA ,ADC converter A power status" "Powered Up,Powered Down" bitfld.word 0x00 4.--9. " PUDELAY ,Power up delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 3. " APD ,Auto powerdown" "Not active,Active" bitfld.word 0x00 1. " PDB ,Manual power down for converter B" "Powered Up,Powered Down" bitfld.word 0x00 0. " PDA ,Manual power down for converter A" "Powered Up,Powered Down" group.word 0xA4++0x0F line.word 0x00 "SCTRL,HSADC Scan Control Register" bitfld.word 0x00 15. " SC[15] ,Scan control bit 15" "Immediate,Delayed" bitfld.word 0x00 14. " [14] ,Scan control bit 14" "Immediate,Delayed" bitfld.word 0x00 13. " [13] ,Scan control bit 13" "Immediate,Delayed" bitfld.word 0x00 12. " [12] ,Scan control bit 12" "Immediate,Delayed" textline " " bitfld.word 0x00 11. " [11] ,Scan control bit 11" "Immediate,Delayed" bitfld.word 0x00 10. " [10] ,Scan control bit 10" "Immediate,Delayed" bitfld.word 0x00 9. " [9] ,Scan control bit 9" "Immediate,Delayed" bitfld.word 0x00 8. " [8] ,Scan control bit 8" "Immediate,Delayed" textline " " bitfld.word 0x00 7. " [7] ,Scan control bit 7" "Immediate,Delayed" bitfld.word 0x00 6. " [6] ,Scan control bit 6" "Immediate,Delayed" bitfld.word 0x00 5. " [5] ,Scan control bit 5" "Immediate,Delayed" bitfld.word 0x00 4. " [4] ,Scan control bit 4" "Immediate,Delayed" textline " " bitfld.word 0x00 3. " [3] ,Scan control bit 3" "Immediate,Delayed" bitfld.word 0x00 2. " [2] ,Scan control bit 2" "Immediate,Delayed" bitfld.word 0x00 1. " [1] ,Scan control bit 1" "Immediate,Delayed" bitfld.word 0x00 0. " [0] ,Scan control bit 0" "Immediate,Delayed" line.word 0x02 "PWR2,HSADC Power Control Register 2" bitfld.word 0x02 8.--13. " DIVB ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.word 0x04 "CTRL3,HSADC Control Register 3" bitfld.word 0x04 8.--9. " ADCRES ,ADCA/B conversion resolution" "6-bit,8-bit,10-bit,12-bit" bitfld.word 0x04 6. " DMASRC ,DMA trigger source" "End of scan interrupt,RDY bits" line.word 0x06 "SCINTEN,HSADC Scan Halted Interrupt Enable Register" bitfld.word 0x06 15. " SCINTEN[15] ,Scan halted interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x06 14. " [14] ,Scan halted interrupt enable bit 14" "Disabled,Enabled" bitfld.word 0x06 13. " [13] ,Scan halted interrupt enable bit 13" "Disabled,Enabled" bitfld.word 0x06 12. " [12] ,Scan halted interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.word 0x06 11. " [11] ,Scan halted interrupt enable bit 11" "Disabled,Enabled" bitfld.word 0x06 10. " [10] ,Scan halted interrupt enable bit 10" "Disabled,Enabled" bitfld.word 0x06 9. " [9] ,Scan halted interrupt enable bit 9" "Disabled,Enabled" bitfld.word 0x06 8. " [8] ,Scan halted interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.word 0x06 7. " [7] ,Scan halted interrupt enable bit 7" "Disabled,Enabled" bitfld.word 0x06 6. " [6] ,Scan halted interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x06 5. " [5] ,Scan halted interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x06 4. " [4] ,Scan halted interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " [3] ,Scan halted interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x06 2. " [2] ,Scan halted interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x06 1. " [1] ,Scan halted interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x06 0. " [0] ,Scan halted interrupt enable bit 0" "Disabled,Enabled" line.word 0x08 "SAMPTIM,HSADC Sampling Time Configuration Register" hexmask.word.byte 0x08 8.--15. 1. " SAMPT_B ,Sampling time for ADCB" hexmask.word.byte 0x08 0.--7. 1. " SAMPT_A ,Sampling time for ADCA" line.word 0x0A "CALIB,HSADC Calibration Configuration Register" bitfld.word 0x0A 9. " EOCALIEB ,End of calibration on ADCB interrupt enable" "Disabled,Enabled" bitfld.word 0x0A 8. " EOCALIEA ,End of calibration on ADCA interrupt enable" "Disabled,Enabled" bitfld.word 0x0A 7. " CAL_REQB ,Calibration request for ADCB" "Not requested,Requested" bitfld.word 0x0A 6. " BYPB ,ADCB calibration bypass" "Not bypassed,Bypassed" textline " " bitfld.word 0x0A 5. " REQDIFB ,ADCB Calibration request for differential mode" "Not requested,Requested" bitfld.word 0x0A 4. " REQSINGB ,ADCB Calibration request for single ended mode" "Not requested,Requested" bitfld.word 0x0A 3. " CAL_REQA ,Calibration request for ADCA" "No effect,Requested" bitfld.word 0x0A 2. " BYPA ,ADCA calibration bypass" "Not bypassed,Bypassed" textline " " bitfld.word 0x0A 1. " REQDIFA ,ADCA Calibration request for differential mode" "Not requested,Requested" bitfld.word 0x0A 0. " REQSINGA ,ADCA Calibration request for single ended mode" "Not requested,Requested" line.word 0x0C "CALVAL_A,Calibration Values For ADCA Register" hexmask.word.byte 0x0C 8.--14. 1. " CALVDIF ,Differential mode calibration value for ADCA" hexmask.word.byte 0x0C 0.--6. 1. " CALVSING ,Single-ended mode calibration value for ADCA" line.word 0x0E "CALVAL_B,Calibration Values For ADCB Register" hexmask.word.byte 0x0E 8.--14. 1. " CALVDIF ,Differential mode calibration value for ADCA" hexmask.word.byte 0x0E 0.--6. 1. " CALVSING ,Single-ended mode calibration value for ADCA" group.word 0xBA++0x01 line.word 0x00 "MUX67_SEL,MUX6_7 Selection Controls Register" bitfld.word 0x00 12.--14. " CH7_SELB ,ADCB channel 7 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " CH6_SELB ,ADCB channel 6 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4.--6. " CH7_SELA ,ADCA channel 7 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " CH6_SELA ,ADCA channel 6 additional MUX selector" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "HSADC1" base ad:0x400DC000 width 11. group.word 0x00++0x07 line.word 0x00 "CTRL1,HSADC Control Register 1" bitfld.word 0x00 15. " DMAENA ,DMA enable" "Disabled,Enabled" bitfld.word 0x00 14. " STOPA ,Stop" "Normal,Stopped" bitfld.word 0x00 13. " STARTA ,Start conversion" "No effect,Start" bitfld.word 0x00 12. " SYNCA ,Sync A enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " EOSIEA ,End of scan interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " ZCIE ,Zero crossing interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " LLMTIE ,Low limit interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " HLMTIE ,High limit interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CHNCFG_L[3] ,CHCNF (channel configure low) bits" "ANB2/3-single,ANB2/3-differential" bitfld.word 0x00 6. " [2] ,CHCNF (channel configure low) bits" "ANB0/1-single,ANB0/1-differential" bitfld.word 0x00 5. " [1] ,CHCNF (channel configure low) bits" "ANA2/3-single,ANA2/3-differential" bitfld.word 0x00 4. " [0] ,CHCNF (channel configure low) bits" "ANA0/1-single,ANA0/1-differential" textline " " bitfld.word 0x00 0.--2. " SMODE ,ADC scan mode control" "Once sequential,Once parallel,Loop sequential,Loop parallel,Triggered sequential,Triggered parallel,?..." line.word 0x02 "CTRL2,HSADC Control Register 2" bitfld.word 0x02 15. " DMAENB ,DMA enable" "Disabled,Enabled" bitfld.word 0x02 14. " STOPB ,Stop" "Normal,Stopped" bitfld.word 0x02 13. " STARTB ,Start conversion" "No effect,Start" bitfld.word 0x02 12. " SYNCB ,Syncb enable" "Disabled,Enabled" textline " " bitfld.word 0x02 11. " EOSIEB ,End of scan interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 10. " CHNCFG_H[3] ,CHCNF (channel configure high) bits" "ANB6/7-single,ANB6/7-differential" bitfld.word 0x02 9. " [2] ,CHCNF (channel configure high) bits" "ANB4/5-single,ANB4/5-differential" bitfld.word 0x02 8. " [1] ,CHCNF (channel configure high) bits" "ANA6/7-single,ANA6/7-differential" bitfld.word 0x02 7. " [0] ,CHCNF (channel configure high) bits" "ANA4/5-single,ANA4/5-differential" textline " " bitfld.word 0x02 6. " SIMULT ,Simultaneous mode" "Independently,Simultaneously" bitfld.word 0x02 0.--5. " DIVA ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.word 0x04 "ZXCTRL1,HSADC Zero Crossing Control 1 Register" bitfld.word 0x04 14.--15. " ZCE7 ,Zero crossing enable 7" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 12.--13. " ZCE6 ,Zero crossing enable 6" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 10.--11. " ZCE5 ,Zero crossing enable 5" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 8.--9. " ZCE4 ,Zero crossing enable 4" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " bitfld.word 0x04 6.--7. " ZCE3 ,Zero crossing enable 3" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 4.--5. " ZCE2 ,Zero crossing enable 2" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 2.--3. " ZCE1 ,Zero crossing enable 1" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 0.--1. " ZCE0 ,Zero crossing enable 0" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" line.word 0x06 "ZXCTRL2,HSADC Zero Crossing Control 2 Register" bitfld.word 0x06 14.--15. " ZCE15 ,Zero crossing enable 15" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 12.--13. " ZCE14 ,Zero crossing enable 14" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 10.--11. " ZCE13 ,Zero crossing enable 13" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 8.--9. " ZCE12 ,Zero crossing enable 12" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " bitfld.word 0x06 6.--7. " ZCE11 ,Zero crossing enable 11" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 4.--5. " ZCE10 ,Zero crossing enable 10" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 2.--3. " ZCE9 ,Zero crossing enable 9" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 0.--1. " ZCE8 ,Zero crossing enable 8" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" textline " " group.word 0x08++0x07 line.word 0x00 "CLIST1,HSADC Channel List Register 1" bitfld.word 0x00 12.--15. " SAMPLE3 ,Sample field 3" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x00 8.--11. " SAMPLE2 ,Sample field 2" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x00 4.--7. " SAMPLE1 ,Sample field 1" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x00 0.--3. " SAMPLE0 ,Sample field 0" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x02 "CLIST2,HSADC Channel List Register 2" bitfld.word 0x02 12.--15. " SAMPLE7 ,Sample field 7" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x02 8.--11. " SAMPLE6 ,Sample field 6" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x02 4.--7. " SAMPLE5 ,Sample field 5" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x02 0.--3. " SAMPLE4 ,Sample field 4" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x04 "CLIST3,HSADC Channel List Register 3" bitfld.word 0x04 12.--15. " SAMPLE11 ,Sample field 11" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x04 8.--11. " SAMPLE10 ,Sample field 10" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x04 4.--7. " SAMPLE9 ,Sample field 9" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x04 0.--3. " SAMPLE8 ,Sample field 8" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" line.word 0x06 "CLIST4,HSADC Channel List Register 4" bitfld.word 0x06 12.--15. " SAMPLE15 ,Sample field 15" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x06 8.--11. " SAMPLE14 ,Sample field 14" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " bitfld.word 0x06 4.--7. " SAMPLE13 ,Sample field 13" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x06 0.--3. " SAMPLE12 ,Sample field 12" "Singleended:ANA0 Differential:ANA0+/ANA1-,Singleended:ANA1 Differential:ANA0+/ANA1-,Singleended:ANA2 Differential:ANA2+/ANA3-,Singleended:ANA3 Differential:ANA2+/ANA3-,Singleended:ANA4 Differential:ANA4+/ANA5-,Singleended:ANA5 Differential:ANA4+/ANA5-,Singleended:ANA6 Differential:ANA6+/ANA7-,Singleended:ANA7 Differential:ANA6+/ANA7-,Singleended:ANB0 Differential:ANB0+/ANB1-,Singleended:ANB1 Differential:ANB0+/ANB1-,Singleended:ANB2 Differential:ANB2+/ANB3-,Singleended:ANB3 Differential:ANB2+/ANB3-,Singleended:ANB4 Differential:ANB4+/ANB5-,Singleended:ANB5 Differential:ANB4+/ANB5-,Singleended:ANB6 Differential:ANB6+/ANB7-,Singleended:ANB7 Differential:ANB6+/ANB7-" textline " " group.word 0x10++0x03 line.word 0x00 "SDIS,HSADC Sample Disable Register" bitfld.word 0x00 15. " DS[15] ,Disable sample bit 15" "No,Yes" bitfld.word 0x00 14. " [14] ,Disable sample bit 14" "No,Yes" bitfld.word 0x00 13. " [13] ,Disable sample bit 13" "No,Yes" bitfld.word 0x00 12. " [12] ,Disable sample bit 12" "No,Yes" textline " " bitfld.word 0x0 11. " [11] ,Disable sample bit 11" "No,Yes" bitfld.word 0x00 10. " [10] ,Disable sample bit 10" "No,Yes" bitfld.word 0x00 9. " [9] ,Disable sample bit 9" "No,Yes" bitfld.word 0x00 8. " [8] ,Disable sample bit 8" "No,Yes" textline " " bitfld.word 0x00 7. " [7] ,Disable sample bit 7" "No,Yes" bitfld.word 0x00 6. " [6] ,Disable sample bit 6" "No,Yes" bitfld.word 0x00 5. " [5] ,Disable sample bit 5" "No,Yes" bitfld.word 0x00 4. " [4] ,Disable sample bit 4" "No,Yes" textline " " bitfld.word 0x00 3. " [3] ,Disable sample bit 3" "No,Yes" bitfld.word 0x00 2. " [2] ,Disable sample bit 2" "No,Yes" bitfld.word 0x00 1. " [1] ,Disable sample bit 1" "No,Yes" bitfld.word 0x00 0. " [0] ,Disable sample bit 0" "No,Yes" line.word 0x02 "STAT,HSADC Status Register" rbitfld.word 0x02 15. " CIPA ,Conversion in progress" "Idle,Active" rbitfld.word 0x02 14. " CIPB ,Conversion in progress" "Idle,Active" eventfld.word 0x02 12. " EOSIB ,End of scan interrupt" "Not completed,Completed" eventfld.word 0x02 11. " EOSIA ,End of scan interrupt" "Not completed,Completed" textline " " rbitfld.word 0x02 10. " ZCI ,Zero crossing interrupt" "Not requested,Requested" rbitfld.word 0x02 9. " LLMTI ,Low limit interrupt" "Not requested,Requested" rbitfld.word 0x02 8. " HLMTI ,High limit interrupt" "Not requested,Requested" eventfld.word 0x02 5. " EOCALIB ,End of calibration on ADCB interrupt" "No interrupt,Interrupt" textline " " eventfld.word 0x02 4. " EOCALIA ,End of calibration on ADCA interrupt" "No interrupt,Interrupt" rbitfld.word 0x02 3. " DUMMYB ,Dummy conversion running on HSADCB" "Not running,Running" rbitfld.word 0x02 2. " DUMMYA ,Dummy conversion running on HSADCA" "Not running,Running" rbitfld.word 0x02 1. " CALONB ,HSADCB calibration execution status" "Not running,Running" textline " " rbitfld.word 0x02 0. " CALONA ,HSADCA calibration execution status" "Not running,Running" rgroup.word 0x14++0x01 line.word 0x00 "RDY,HSADC Ready Register" bitfld.word 0x00 15. " RDY[15] ,Ready sample 15" "Not ready,Ready" bitfld.word 0x00 14. " [14] ,Ready sample 14" "Not ready,Ready" bitfld.word 0x00 13. " [13] ,Ready sample 13" "Not ready,Ready" textline " " bitfld.word 0x00 12. " [12] ,Ready sample 12" "Not ready,Ready" bitfld.word 0x00 11. " [11] ,Ready sample 11" "Not ready,Ready" bitfld.word 0x00 10. " [10] ,Ready sample 10" "Not ready,Ready" textline " " bitfld.word 0x00 9. " [9] ,Ready sample 9" "Not ready,Ready" bitfld.word 0x00 8. " [8] ,Ready sample 8" "Not ready,Ready" bitfld.word 0x00 7. " [7] ,Ready sample 7" "Not ready,Ready" textline " " bitfld.word 0x00 6. " [6] ,Ready sample 6" "Not ready,Ready" bitfld.word 0x00 5. " [5] ,Ready sample 5" "Not ready,Ready" bitfld.word 0x00 4. " [4] ,Ready sample 4" "Not ready,Ready" textline " " bitfld.word 0x00 3. " [3] ,Ready sample 3" "Not ready,Ready" bitfld.word 0x00 2. " [2] ,Ready sample 2" "Not ready,Ready" bitfld.word 0x00 1. " [1] ,Ready sample 1" "Not ready,Ready" textline " " bitfld.word 0x00 0. " [0] ,Ready sample 0" "Not ready,Ready" group.word 0x16++0x97 line.word 0x00 "LOLIMSTAT,HSADC Low Limit Status Register" eventfld.word 0x00 15. " LLS[15] ,Low limit status bits 15" "Not lower,Lower" eventfld.word 0x00 14. " [14] ,Low limit status bits 14" "Not lower,Lower" eventfld.word 0x00 13. " [13] ,Low limit status bits 13" "Not lower,Lower" eventfld.word 0x00 12. " [12] ,Low limit status bits 12" "Not lower,Lower" textline " " eventfld.word 0x00 11. " [11] ,Low limit status bits 11" "Not lower,Lower" eventfld.word 0x00 10. " [10] ,Low limit status bits 10" "Not lower,Lower" eventfld.word 0x00 9. " [9] ,Low limit status bits 9" "Not lower,Lower" eventfld.word 0x00 8. " [8] ,Low limit status bits 8" "Not lower,Lower" textline " " eventfld.word 0x00 7. " [7] ,Low limit status bits 7" "Not lower,Lower" eventfld.word 0x00 6. " [6] ,Low limit status bits 6" "Not lower,Lower" eventfld.word 0x00 5. " [5] ,Low limit status bits 5" "Not lower,Lower" eventfld.word 0x00 4. " [4] ,Low limit status bits 4" "Not lower,Lower" textline " " eventfld.word 0x00 3. " [3] ,Low limit status bits 3" "Not lower,Lower" eventfld.word 0x00 2. " [2] ,Low limit status bits 2" "Not lower,Lower" eventfld.word 0x00 1. " [1] ,Low limit status bits 1" "Not lower,Lower" eventfld.word 0x00 0. " [0] ,Low limit status bits 0" "Not lower,Lower" line.word 0x02 "HILIMSTAT,HSADC High Limit Status Register" eventfld.word 0x02 15. " HLS[15] ,High limit status bits 15" "Not higher,Higher" eventfld.word 0x02 14. " [14] ,High limit status bits 14" "Not higher,Higher" eventfld.word 0x02 13. " [13] ,High limit status bits 13" "Not higher,Higher" eventfld.word 0x02 12. " [12] ,High limit status bits 12" "Not higher,Higher" textline " " eventfld.word 0x02 11. " [11] ,High limit status bits 11" "Not higher,Higher" eventfld.word 0x02 10. " [10] ,High limit status bits 10" "Not higher,Higher" eventfld.word 0x02 9. " [9] ,High limit status bits 9" "Not higher,Higher" eventfld.word 0x02 8. " [8] ,High limit status bits 8" "Not higher,Higher" textline " " eventfld.word 0x02 7. " [7] ,High limit status bits 7" "Not higher,Higher" eventfld.word 0x02 6. " [6] ,High limit status bits 6" "Not higher,Higher" eventfld.word 0x02 5. " [5] ,High limit status bits 5" "Not higher,Higher" eventfld.word 0x02 4. " [4] ,High limit status bits 4" "Not higher,Higher" textline " " eventfld.word 0x02 3. " [3] ,High limit status bits 3" "Not higher,Higher" eventfld.word 0x02 2. " [2] ,High limit status bits 2" "Not higher,Higher" eventfld.word 0x02 1. " [1] ,High limit status bits 1" "Not higher,Higher" eventfld.word 0x02 0. " [0] ,High limit status bits 0" "Not higher,Higher" line.word 0x04 "ZXSTAT,HSADC Zero Crossing Status Register" eventfld.word 0x04 15. " ZCS[15] ,Zero crossing status 15" "Not crossed,Crossed" eventfld.word 0x04 14. " [14] ,Zero crossing status 14" "Not crossed,Crossed" eventfld.word 0x04 13. " [13] ,Zero crossing status 13" "Not crossed,Crossed" eventfld.word 0x04 12. " [12] ,Zero crossing status 12" "Not crossed,Crossed" textline " " eventfld.word 0x04 11. " [11] ,Zero crossing status 11" "Not crossed,Crossed" eventfld.word 0x04 10. " [10] ,Zero crossing status 10" "Not crossed,Crossed" eventfld.word 0x04 9. " [9] ,Zero crossing status 9" "Not crossed,Crossed" eventfld.word 0x04 8. " [8] ,Zero crossing status 8" "Not crossed,Crossed" textline " " eventfld.word 0x04 7. " [7] ,Zero crossing status 7" "Not crossed,Crossed" eventfld.word 0x04 6. " [6] ,Zero crossing status 6" "Not crossed,Crossed" eventfld.word 0x04 5. " [5] ,Zero crossing status 5" "Not crossed,Crossed" eventfld.word 0x04 4. " [4] ,Zero crossing status 4" "Not crossed,Crossed" textline " " eventfld.word 0x04 3. " [3] ,Zero crossing status 3" "Not crossed,Crossed" eventfld.word 0x04 2. " [2] ,Zero crossing status 2" "Not crossed,Crossed" eventfld.word 0x04 1. " [1] ,Zero crossing status 1" "Not crossed,Crossed" eventfld.word 0x04 0. " [0] ,Zero crossing status 0" "Not crossed,Crossed" group.word 0x1E++0x01 line.word 0x00 "RSLT0,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x20++0x01 line.word 0x00 "RSLT1,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x22++0x01 line.word 0x00 "RSLT2,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x24++0x01 line.word 0x00 "RSLT3,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x26++0x01 line.word 0x00 "RSLT4,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x28++0x01 line.word 0x00 "RSLT5,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2A++0x01 line.word 0x00 "RSLT6,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2C++0x01 line.word 0x00 "RSLT7,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2E++0x01 line.word 0x00 "RSLT8,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x30++0x01 line.word 0x00 "RSLT9,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x32++0x01 line.word 0x00 "RSLT10,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x34++0x01 line.word 0x00 "RSLT11,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x36++0x01 line.word 0x00 "RSLT12,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x38++0x01 line.word 0x00 "RSLT13,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3A++0x01 line.word 0x00 "RSLT14,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3C++0x01 line.word 0x00 "RSLT15,HSADC Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "+,-" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3C++0x01 line.word 0x00 "LOLIM0,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x3E++0x01 line.word 0x00 "LOLIM1,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x40++0x01 line.word 0x00 "LOLIM2,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x42++0x01 line.word 0x00 "LOLIM3,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x44++0x01 line.word 0x00 "LOLIM4,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x46++0x01 line.word 0x00 "LOLIM5,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x48++0x01 line.word 0x00 "LOLIM6,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4A++0x01 line.word 0x00 "LOLIM7,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4C++0x01 line.word 0x00 "LOLIM8,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4E++0x01 line.word 0x00 "LOLIM9,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x50++0x01 line.word 0x00 "LOLIM10,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x52++0x01 line.word 0x00 "LOLIM11,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x54++0x01 line.word 0x00 "LOLIM12,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x56++0x01 line.word 0x00 "LOLIM13,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x58++0x01 line.word 0x00 "LOLIM14,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5A++0x01 line.word 0x00 "LOLIM15,HSADC Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5C++0x01 line.word 0x00 "HILIM0,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x5E++0x01 line.word 0x00 "HILIM1,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x60++0x01 line.word 0x00 "HILIM2,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x62++0x01 line.word 0x00 "HILIM3,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x64++0x01 line.word 0x00 "HILIM4,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x66++0x01 line.word 0x00 "HILIM5,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x68++0x01 line.word 0x00 "HILIM6,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6A++0x01 line.word 0x00 "HILIM7,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6C++0x01 line.word 0x00 "HILIM8,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6E++0x01 line.word 0x00 "HILIM9,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x70++0x01 line.word 0x00 "HILIM10,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x72++0x01 line.word 0x00 "HILIM11,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x74++0x01 line.word 0x00 "HILIM12,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x76++0x01 line.word 0x00 "HILIM13,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x78++0x01 line.word 0x00 "HILIM14,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7A++0x01 line.word 0x00 "HILIM15,HSADC High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7C++0x01 line.word 0x00 "OFFST0,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x7E++0x01 line.word 0x00 "OFFST1,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x80++0x01 line.word 0x00 "OFFST2,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x82++0x01 line.word 0x00 "OFFST3,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x84++0x01 line.word 0x00 "OFFST4,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x86++0x01 line.word 0x00 "OFFST5,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x88++0x01 line.word 0x00 "OFFST6,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8A++0x01 line.word 0x00 "OFFST7,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8C++0x01 line.word 0x00 "OFFST8,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x8E++0x01 line.word 0x00 "OFFST9,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x90++0x01 line.word 0x00 "OFFST10,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x92++0x01 line.word 0x00 "OFFST11,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x94++0x01 line.word 0x00 "OFFST12,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x96++0x01 line.word 0x00 "OFFST13,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x98++0x01 line.word 0x00 "OFFST14,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x9A++0x01 line.word 0x00 "OFFST15,HSADC Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,HSADC offset bits" group.word 0x9C++0x01 line.word 0x00 "PWR,HSADC Power Control Register" bitfld.word 0x00 15. " ASB ,Auto standby" "Disabled,Enabled" rbitfld.word 0x00 11. " PSTSB ,ADC converter B power status" "Powered Up,Powered Down" rbitfld.word 0x00 10. " PSTSA ,ADC converter A power status" "Powered Up,Powered Down" bitfld.word 0x00 4.--9. " PUDELAY ,Power up delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x00 3. " APD ,Auto powerdown" "Not active,Active" bitfld.word 0x00 1. " PDB ,Manual power down for converter B" "Powered Up,Powered Down" bitfld.word 0x00 0. " PDA ,Manual power down for converter A" "Powered Up,Powered Down" group.word 0xA4++0x0F line.word 0x00 "SCTRL,HSADC Scan Control Register" bitfld.word 0x00 15. " SC[15] ,Scan control bit 15" "Immediate,Delayed" bitfld.word 0x00 14. " [14] ,Scan control bit 14" "Immediate,Delayed" bitfld.word 0x00 13. " [13] ,Scan control bit 13" "Immediate,Delayed" bitfld.word 0x00 12. " [12] ,Scan control bit 12" "Immediate,Delayed" textline " " bitfld.word 0x00 11. " [11] ,Scan control bit 11" "Immediate,Delayed" bitfld.word 0x00 10. " [10] ,Scan control bit 10" "Immediate,Delayed" bitfld.word 0x00 9. " [9] ,Scan control bit 9" "Immediate,Delayed" bitfld.word 0x00 8. " [8] ,Scan control bit 8" "Immediate,Delayed" textline " " bitfld.word 0x00 7. " [7] ,Scan control bit 7" "Immediate,Delayed" bitfld.word 0x00 6. " [6] ,Scan control bit 6" "Immediate,Delayed" bitfld.word 0x00 5. " [5] ,Scan control bit 5" "Immediate,Delayed" bitfld.word 0x00 4. " [4] ,Scan control bit 4" "Immediate,Delayed" textline " " bitfld.word 0x00 3. " [3] ,Scan control bit 3" "Immediate,Delayed" bitfld.word 0x00 2. " [2] ,Scan control bit 2" "Immediate,Delayed" bitfld.word 0x00 1. " [1] ,Scan control bit 1" "Immediate,Delayed" bitfld.word 0x00 0. " [0] ,Scan control bit 0" "Immediate,Delayed" line.word 0x02 "PWR2,HSADC Power Control Register 2" bitfld.word 0x02 8.--13. " DIVB ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.word 0x04 "CTRL3,HSADC Control Register 3" bitfld.word 0x04 8.--9. " ADCRES ,ADCA/B conversion resolution" "6-bit,8-bit,10-bit,12-bit" bitfld.word 0x04 6. " DMASRC ,DMA trigger source" "End of scan interrupt,RDY bits" line.word 0x06 "SCINTEN,HSADC Scan Halted Interrupt Enable Register" bitfld.word 0x06 15. " SCINTEN[15] ,Scan halted interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x06 14. " [14] ,Scan halted interrupt enable bit 14" "Disabled,Enabled" bitfld.word 0x06 13. " [13] ,Scan halted interrupt enable bit 13" "Disabled,Enabled" bitfld.word 0x06 12. " [12] ,Scan halted interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.word 0x06 11. " [11] ,Scan halted interrupt enable bit 11" "Disabled,Enabled" bitfld.word 0x06 10. " [10] ,Scan halted interrupt enable bit 10" "Disabled,Enabled" bitfld.word 0x06 9. " [9] ,Scan halted interrupt enable bit 9" "Disabled,Enabled" bitfld.word 0x06 8. " [8] ,Scan halted interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.word 0x06 7. " [7] ,Scan halted interrupt enable bit 7" "Disabled,Enabled" bitfld.word 0x06 6. " [6] ,Scan halted interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x06 5. " [5] ,Scan halted interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x06 4. " [4] ,Scan halted interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.word 0x06 3. " [3] ,Scan halted interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x06 2. " [2] ,Scan halted interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x06 1. " [1] ,Scan halted interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x06 0. " [0] ,Scan halted interrupt enable bit 0" "Disabled,Enabled" line.word 0x08 "SAMPTIM,HSADC Sampling Time Configuration Register" hexmask.word.byte 0x08 8.--15. 1. " SAMPT_B ,Sampling time for ADCB" hexmask.word.byte 0x08 0.--7. 1. " SAMPT_A ,Sampling time for ADCA" line.word 0x0A "CALIB,HSADC Calibration Configuration Register" bitfld.word 0x0A 9. " EOCALIEB ,End of calibration on ADCB interrupt enable" "Disabled,Enabled" bitfld.word 0x0A 8. " EOCALIEA ,End of calibration on ADCA interrupt enable" "Disabled,Enabled" bitfld.word 0x0A 7. " CAL_REQB ,Calibration request for ADCB" "Not requested,Requested" bitfld.word 0x0A 6. " BYPB ,ADCB calibration bypass" "Not bypassed,Bypassed" textline " " bitfld.word 0x0A 5. " REQDIFB ,ADCB Calibration request for differential mode" "Not requested,Requested" bitfld.word 0x0A 4. " REQSINGB ,ADCB Calibration request for single ended mode" "Not requested,Requested" bitfld.word 0x0A 3. " CAL_REQA ,Calibration request for ADCA" "No effect,Requested" bitfld.word 0x0A 2. " BYPA ,ADCA calibration bypass" "Not bypassed,Bypassed" textline " " bitfld.word 0x0A 1. " REQDIFA ,ADCA Calibration request for differential mode" "Not requested,Requested" bitfld.word 0x0A 0. " REQSINGA ,ADCA Calibration request for single ended mode" "Not requested,Requested" line.word 0x0C "CALVAL_A,Calibration Values For ADCA Register" hexmask.word.byte 0x0C 8.--14. 1. " CALVDIF ,Differential mode calibration value for ADCA" hexmask.word.byte 0x0C 0.--6. 1. " CALVSING ,Single-ended mode calibration value for ADCA" line.word 0x0E "CALVAL_B,Calibration Values For ADCB Register" hexmask.word.byte 0x0E 8.--14. 1. " CALVDIF ,Differential mode calibration value for ADCA" hexmask.word.byte 0x0E 0.--6. 1. " CALVSING ,Single-ended mode calibration value for ADCA" group.word 0xBA++0x01 line.word 0x00 "MUX67_SEL,MUX6_7 Selection Controls Register" bitfld.word 0x00 12.--14. " CH7_SELB ,ADCB channel 7 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. " CH6_SELB ,ADCB channel 6 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4.--6. " CH7_SELA ,ADCA channel 7 additional MUX selector" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--2. " CH6_SELA ,ADCA channel 6 additional MUX selector" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree.end tree.open "CMP (Comparator)" tree "CMP0" base ad:0x40073000 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP1" base ad:0x40073008 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP2" base ad:0x40073010 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,IN2,,IN4,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,IN2,,IN4,,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP3" base ad:0x40073018 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree.end tree "DAC (Digital-to-Analog Converter)" base ad:0x4003F000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC0_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC0_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.open "FTM (FlexTimer Module)" tree "Module 0" base ad:0x40038000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register" in newline else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM0_CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM0_MOD,FTM0 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM0_CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40038000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree "Module 1" base ad:0x40039000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register" in newline else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM1_CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM1_MOD,FTM1 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM1_CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40039000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree "Module 2" base ad:0x4003A000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM2_SC,FTM2 Status And Control Register" in newline else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM2_SC,FTM2 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM2_CNT,FTM2 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM2_MOD,FTM2 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM2_C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM2_C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM2_C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM2_CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM2_STATUS,FTM2 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM2_MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM2_SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM2_OUTINIT,FTM2 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM2_OUTMASK,FTM2 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM2_COMBINE,FTM2 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM2_DEADTIME,FTM2 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM2_EXTTRIG,FTM2 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM2_POL,FTM2 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM2_FMS,FTM2 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM2_FILTER,FTM2 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM2_FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM2_QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM2_CONF,FTM2 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x4003A000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM2_FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM2_SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM2_INVCTRL,FTM2 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM2_SWOCTRL,FTM2 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM2_PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree "Module 3" base ad:0x40036000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM3_SC,FTM3 Status And Control Register" in newline else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM3_CNT,FTM3 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM3_MOD,FTM3 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM3_CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM3_SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM3_OUTINIT,FTM3 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM3_OUTMASK,FTM3 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM3_EXTTRIG,FTM3 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM3_FMS,FTM3 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM3_FILTER,FTM3 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM3_CONF,FTM3 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40036000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM3_SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM3_INVCTRL,FTM3 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM3_SWOCTRL,FTM3 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM3_PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree.end tree "LPTMR (Low-Power Timer)" base ad:0x40040000 width 5. if (((per.l(ad:0x40040000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x40040000))&0x01)==0x00) if (((per.l(ad:0x40040000))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif else if (((per.l(ad:0x40040000))&0x02)==0x00) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif endif if (((per.l(ad:0x40040000))&0x01)==0x00)||(((per.l(ad:0x40040000))&0x81)==0x81) group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif else rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif sif cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree.open "PDB (Programmable Delay Block)" tree "PDB0" base ad:0x40036000 width 11. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,PDB reached MOD,Trigger detected,Trigger detected/PDB mod" bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 16. " SWTRIG,Software trigger" "No effect,Trigger" else bitfld.long 0x00 16. " SWTRIG,Software trigger" "Not triggered,Triggered" endif newline bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler factor" "/1*MULT,/2*MULT,/4*MULT,/8*MULT,/16*MULT,/32*MULT,/64*MULT,/128*MULT" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "PDB_EXTRG0,CMP0,CMP1,PDB_EXTRG1,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR,Software trigger" elif cpuis("MKV10Z*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV30F*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" elif (cpuis("MKV5*")) bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,XBARA_OUT38,,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV5*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV30F*")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" else group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 3. " POEN[3] ,PDB pulse out enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " POEN[2] ,PDB pulse out enable" "Disabled,Enabled" newline sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*") else bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" newline endif bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x03 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0x0B tree.end tree "PDB1" base ad:0x40031000 width 11. group.long 0x00++0x07 line.long 0x00 "SC,Status And Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately,PDB reached MOD,Trigger detected,Trigger detected/PDB mod" bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 16. " SWTRIG,Software trigger" "No effect,Trigger" else bitfld.long 0x00 16. " SWTRIG,Software trigger" "Not triggered,Triggered" endif newline bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler factor" "/1*MULT,/2*MULT,/4*MULT,/8*MULT,/16*MULT,/32*MULT,/64*MULT,/128*MULT" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VLH7") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "PDB_EXTRG0,CMP0,CMP1,PDB_EXTRG1,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR,Software trigger" elif cpuis("MKV10Z*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,DMA Ch0(Done),DMA Ch1(Done),DMA Ch2(Done),DMA Ch3(Done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV30F*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" ",CMP 0,CMP 1,CMP 2,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,,FTM3,XBAR_OUT 41,,LPTMR output,Software trigger" elif (cpuis("MKV5*")) bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" ",CMP 0,CMP 1,,PIT ch0 output,PIT ch1 output,PIT ch2 output,PIT ch3 output,FTM0,FTM1,FTM2,FTM3,XBARA_OUT41,,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x10++0x0F line.long 0x00 "CH0C1,Channel 0 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH0S,Channel 0 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH0DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" bitfld.long 0x00 23. " BB7 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB6 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB5 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB4 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB3 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB2 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB1 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB0 ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS7 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 14. " TOS6 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 13. " TOS5 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 12. " TOS4 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS3 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 10. " TOS2 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 9. " TOS1 ,PDB channel pre-trigger output select" "Disabled,Enabled" bitfld.long 0x00 8. " TOS0 ,PDB channel pre-trigger output select" "Disabled,Enabled" newline bitfld.long 0x00 7. " EN7 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN3 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 0x01 " CF ,PDB channel flags" newline bitfld.long 0x04 7. " ERR7 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 6. " ERR6 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 5. " ERR5 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 4. " ERR4 ,PDB channel sequence error flags" "No error,Error" newline bitfld.long 0x04 3. " ERR3 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 2. " ERR2 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 1. " ERR1 ,PDB channel sequence error flags" "No error,Error" bitfld.long 0x04 0. " ERR0 ,PDB channel sequence error flags" "No error,Error" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" else group.long 0x38++0x0F line.long 0x00 "CH1C1,Channel 1 Control Register 1" hexmask.long.byte 0x00 16.--23. 1. " BB ,PDB channel pre-trigger back-to-back operation enable" hexmask.long.byte 0x00 8.--15. 1. " TOS ,PDB channel pre-trigger output select" newline hexmask.long.byte 0x00 0.--7. 1. " EN ,PDB channel pre-trigger enable" line.long 0x04 "CH1S,Channel 1 Status Register" hexmask.long.byte 0x04 16.--23. 1. " CF ,PDB channel flags" hexmask.long.byte 0x04 0.--7. 1. " ERR ,PDB channel sequence error flags" line.long 0x08 "CH1DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" endif sif cpuis("MKV10Z*")||cpuis("MKV5*")||cpuis("MKV31F256VLL12")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV30F*")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" else group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 3. " POEN[3] ,PDB pulse out enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " POEN[2] ,PDB pulse out enable" "Disabled,Enabled" newline sif cpuis("MKV10Z*")||cpuis("MKV31F*")||cpuis("MKV30F*") else bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" newline endif bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x03 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0x0B tree.end tree.end tree "ENC (Quadrature Encoder/Decoder)" base ad:0x40055000 width 8. group.word 0x00++0x07 line.word 0x00 "CTRL,Control Register" eventfld.word 0x00 15. " HIRQ ,HOME signal transition interrupt request" "No interrupt,Interrupt" bitfld.word 0x00 14. " HIE ,HOME interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " HIP ,Enable HOME to initialize position counters UPOS and LPOS" "Disabled,Enabled" newline bitfld.word 0x00 12. " HNE ,Use negative edge of HOME input" "Positive,Negative" bitfld.word 0x00 11. " SWIP ,Software triggered initialization of position counters UPOS and LPOS" "No,Yes" bitfld.word 0x00 10. " REV ,Enable reverse direction counting" "Normal,Reverse" newline bitfld.word 0x00 9. " PH1 ,Enable signal phase count mode" "Disabled,Enabled" eventfld.word 0x00 8. " XIRQ ,INDEX pulse interrupt request" "Not occurred,Occurred" bitfld.word 0x00 7. " XIE ,INDEX pulse interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " XIP ,INDEX triggered initialization of position counters UPOS and LPOS" "No,Yes" bitfld.word 0x00 5. " XNE ,Use negative edge of index pulse" "Positive,Negative" eventfld.word 0x00 4. " DIRQ ,Watchdog timeout interrupt request" "Not occurred,Occurred" newline bitfld.word 0x00 3. " DIE ,Watchdog timeout interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" eventfld.word 0x00 1. " CMPIRQ ,Compare interrupt request" "Not occurred,Occurred" newline bitfld.word 0x00 0. " CMPIE ,Compare interrupt enable" "Disabled,Enabled" line.word 0x02 "FILT,Input Filter Register" bitfld.word 0x02 8.--10. " CNT ,Input filter sample count" "3,4,5,6,7,8,9,10" hexmask.word.byte 0x02 0.--7. 1. " PER ,Input filter sample period" line.word 0x04 "WTR,Watchdog Timeout Register" line.word 0x06 "POSD,Position Difference Counter" rgroup.word 0x08++0x01 line.word 0x00 "POSDH,Position Difference Hold Register" group.word 0x0A++0x01 line.word 0x00 "REV,Revolution Counter Register" rgroup.word 0x0C++0x01 line.word 0x00 "REVH,Revolution Hold Register" group.word 0x0E++0x03 line.word 0x00 "UPOS,Upper Position Counter Register" line.word 0x02 "LPOS,Lower Position Counter Register" rgroup.word 0x12++0x03 line.word 0x00 "UPOSH,Upper Position Hold Register" line.word 0x02 "LPOSH,Lower Position Hold Register" group.word 0x16++0x03 line.word 0x00 "UINIT,Upper Initialization Register" line.word 0x02 "LINIT,Lower Initialization Register" rgroup.word 0x1A++0x01 line.word 0x00 "IMR,Input Monitor Register" bitfld.word 0x00 7. " FPHA ,Filtered version of PHASEA input" "0,1" bitfld.word 0x00 6. " FPHB ,Filtered version of PHASEB input" "0,1" bitfld.word 0x00 5. " FIND ,Filtered version of INDEX input" "0,1" newline bitfld.word 0x00 4. " FHOM ,Filtered version of HOME input" "0,1" bitfld.word 0x00 3. " PHA ,Raw PHASEA input" "0,1" bitfld.word 0x00 2. " PHB ,Raw PHASEB input" "0,1" newline bitfld.word 0x00 1. " INDEX ,Raw INDEX input" "0,1" bitfld.word 0x00 0. " HOME ,Raw HOME input" "0,1" group.word 0x1C++0x0B line.word 0x00 "TST,Test Register" bitfld.word 0x00 15. " TEN ,Test mode enable" "Disabled,Enabled" bitfld.word 0x00 14. " TCE ,Test counter enable" "Disabled,Enabled" bitfld.word 0x00 13. " QDN ,Quadrature decoder negative signal" "Positive,Negative" newline bitfld.word 0x00 8.--12. " TEST_PERIOD ,These bits hold the period of quadrature phase in IPBus clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" hexmask.word.byte 0x00 0.--7. 1. " TEST_COUNT ,These bits hold the number of quadrature advances to generate" line.word 0x02 "CTRL2,Control 2 Register" sif (cpuis("MKV5*"))||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") eventfld.word 0x02 11. " SABIRQ , Indicates that the PHASEA and PHASEB inputs changed simultaneously" "Not occurred,Occurred" bitfld.word 0x02 10. " SABIE ,Simultaneous PHASEA and PHASEB change interrupt enable" "Disabled,Enabled" bitfld.word 0x02 9. " OUTCTL ,Output control" "On match,On read" newline bitfld.word 0x02 8. " REVMOD ,Revolution counter modulus enable" "INDEX pulse,Roll-over/under" eventfld.word 0x02 7. " ROIRQ ,Roll-over interrupt request" "Not occurred,Occurred" bitfld.word 0x02 6. " ROIE ,Roll-over interrupt enable" "Disabled,Enabled" newline eventfld.word 0x02 5. " RUIRQ ,Roll-under interrupt request" "Not occurred,Occurred" bitfld.word 0x02 4. " RUIE ,Roll-under interrupt enable" "Disabled,Enabled" rbitfld.word 0x02 3. " DIR ,Count direction flag" "Down,Up" newline bitfld.word 0x02 2. " MOD ,Enable modulo counting" "Disabled,Enabled" bitfld.word 0x02 1. " UPDPOS ,Update position registers" "Not cleared,Cleared" bitfld.word 0x02 0. " UPDHLD ,Update hold registers" "Disabled,Enabled" else bitfld.word 0x02 9. " OUTCTL ,Output control" "On match,On read" bitfld.word 0x02 8. " REVMOD ,Revolution counter modulus enable" "INDEX pulse,Roll-over/under" eventfld.word 0x02 7. " ROIRQ ,Roll-over interrupt request" "Not occurred,Occurred" newline bitfld.word 0x02 6. " ROIE ,Roll-over interrupt enable" "Disabled,Enabled" eventfld.word 0x02 5. " RUIRQ ,Roll-under interrupt request" "Not occurred,Occurred" bitfld.word 0x02 4. " RUIE ,Roll-under interrupt enable" "Disabled,Enabled" newline rbitfld.word 0x02 3. " DIR ,Count direction flag" "Down,Up" bitfld.word 0x02 2. " MOD ,Enable modulo counting" "Disabled,Enabled" bitfld.word 0x02 1. " UPDPOS ,Update position registers" "Not cleared,Cleared" newline bitfld.word 0x02 0. " UPDHLD ,Update hold registers" "No,Yes" endif line.word 0x04 "UMOD,Upper Modulus Register" line.word 0x06 "LMOD,Lower Modulus Register" line.word 0x08 "UCOMP,Upper Position Compare Register" line.word 0x0A "LCOMP,Lower Position Compare Register" width 0x0B tree.end tree.open "EFLEXPWM (Enhanced Flex Pulse Width Modulator)" tree "PWM0" base ad:0x40033000 width 14. rgroup.word 0x0++0x01 line.word 0x00 "SM0CNT,Counter Register" if (((per.l(ad:0x40033000+0x188))&(0x01<<0))==(0x01<<0)) rgroup.word (0x0+0x02)++0x01 line.word 0x00 "SM0INIT,Initial Count Register" else group.word (0x0+0x02)++0x01 line.word 0x00 "SM0INIT,Initial Count Register" endif group.word (0x0+0x04)++0x1 line.word 0x00 "SM0CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x40033000+0x188))&(0x01<<0))==(0x01<<0)) group.word (0x0+0x06)++0x01 line.word 0x00 "SM0CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x0+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x0+0x20)++0x01 line.word 0x00 "SM0FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x0+0x06)++0x01 line.word 0x00 "SM0CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x0+0x0A)++0x17 line.word 0x00 "SM0VAL0,Value Register 0" line.word 0x02 "SM0FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM0VAL1,Value Register 1" line.word 0x06 "SM0FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM0VAL2,Value Register 2" line.word 0x0A "SM0FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM0VAL3,Value Register 3" line.word 0x0E "SM0FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM0VAL4,Value Register 4" line.word 0x12 "SM0FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM0VAL5,Value Register 5" line.word 0x16 "SM0FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x0+0x22)++0x0B line.word 0x00 "SM0OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM0STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM0INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM0DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM0TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM0DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x0+0x30)++0x0F line.word 0x00 "SM0DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM0DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM0CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM0CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM0CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM0CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM0CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM0CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x0+0x40)++0x17 line.word 0x00 "SM0CVAL0,Capture Value 0 Register" line.word 0x02 "SM0CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM0CVAL1,Capture Value 1 Register" line.word 0x06 "SM0CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM0CVAL2,Capture Value 2 Register" line.word 0x0A "SM0CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM0CVAL3,Capture Value 3 Register" line.word 0x0E "SM0CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM0CVAL4,Capture Value 4 Register" line.word 0x12 "SM0CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM0CVAL5,Capture Value 5 Register" line.word 0x16 "SM0CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x60++0x01 line.word 0x00 "SM1CNT,Counter Register" if (((per.l(ad:0x40033000+0x188))&(0x01<<1))==(0x01<<1)) rgroup.word (0x60+0x02)++0x01 line.word 0x00 "SM1INIT,Initial Count Register" else group.word (0x60+0x02)++0x01 line.word 0x00 "SM1INIT,Initial Count Register" endif group.word (0x60+0x04)++0x1 line.word 0x00 "SM1CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x40033000+0x188))&(0x01<<1))==(0x01<<1)) group.word (0x60+0x06)++0x01 line.word 0x00 "SM1CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x60+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x60+0x20)++0x01 line.word 0x00 "SM1FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x60+0x06)++0x01 line.word 0x00 "SM1CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x60+0x0A)++0x17 line.word 0x00 "SM1VAL0,Value Register 0" line.word 0x02 "SM1FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM1VAL1,Value Register 1" line.word 0x06 "SM1FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM1VAL2,Value Register 2" line.word 0x0A "SM1FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM1VAL3,Value Register 3" line.word 0x0E "SM1FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM1VAL4,Value Register 4" line.word 0x12 "SM1FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM1VAL5,Value Register 5" line.word 0x16 "SM1FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x60+0x22)++0x0B line.word 0x00 "SM1OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM1STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM1INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM1DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM1TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM1DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x60+0x30)++0x0F line.word 0x00 "SM1DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM1DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM1CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM1CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM1CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM1CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM1CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM1CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x60+0x40)++0x17 line.word 0x00 "SM1CVAL0,Capture Value 0 Register" line.word 0x02 "SM1CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM1CVAL1,Capture Value 1 Register" line.word 0x06 "SM1CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM1CVAL2,Capture Value 2 Register" line.word 0x0A "SM1CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM1CVAL3,Capture Value 3 Register" line.word 0x0E "SM1CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM1CVAL4,Capture Value 4 Register" line.word 0x12 "SM1CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM1CVAL5,Capture Value 5 Register" line.word 0x16 "SM1CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xC0++0x01 line.word 0x00 "SM2CNT,Counter Register" if (((per.l(ad:0x40033000+0x188))&(0x01<<2))==(0x01<<2)) rgroup.word (0xC0+0x02)++0x01 line.word 0x00 "SM2INIT,Initial Count Register" else group.word (0xC0+0x02)++0x01 line.word 0x00 "SM2INIT,Initial Count Register" endif group.word (0xC0+0x04)++0x1 line.word 0x00 "SM2CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x40033000+0x188))&(0x01<<2))==(0x01<<2)) group.word (0xC0+0x06)++0x01 line.word 0x00 "SM2CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0xC0+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0xC0+0x20)++0x01 line.word 0x00 "SM2FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0xC0+0x06)++0x01 line.word 0x00 "SM2CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0xC0+0x0A)++0x17 line.word 0x00 "SM2VAL0,Value Register 0" line.word 0x02 "SM2FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM2VAL1,Value Register 1" line.word 0x06 "SM2FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM2VAL2,Value Register 2" line.word 0x0A "SM2FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM2VAL3,Value Register 3" line.word 0x0E "SM2FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM2VAL4,Value Register 4" line.word 0x12 "SM2FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM2VAL5,Value Register 5" line.word 0x16 "SM2FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0xC0+0x22)++0x0B line.word 0x00 "SM2OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM2STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM2INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM2DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM2TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM2DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0xC0+0x30)++0x0F line.word 0x00 "SM2DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM2DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM2CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM2CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM2CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM2CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM2CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM2CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0xC0+0x40)++0x17 line.word 0x00 "SM2CVAL0,Capture Value 0 Register" line.word 0x02 "SM2CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM2CVAL1,Capture Value 1 Register" line.word 0x06 "SM2CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM2CVAL2,Capture Value 2 Register" line.word 0x0A "SM2CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM2CVAL3,Capture Value 3 Register" line.word 0x0E "SM2CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM2CVAL4,Capture Value 4 Register" line.word 0x12 "SM2CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM2CVAL5,Capture Value 5 Register" line.word 0x16 "SM2CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x120++0x01 line.word 0x00 "SM3CNT,Counter Register" if (((per.l(ad:0x40033000+0x188))&(0x01<<3))==(0x01<<3)) rgroup.word (0x120+0x02)++0x01 line.word 0x00 "SM3INIT,Initial Count Register" else group.word (0x120+0x02)++0x01 line.word 0x00 "SM3INIT,Initial Count Register" endif group.word (0x120+0x04)++0x1 line.word 0x00 "SM3CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x40033000+0x188))&(0x01<<3))==(0x01<<3)) group.word (0x120+0x06)++0x01 line.word 0x00 "SM3CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x120+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x120+0x20)++0x01 line.word 0x00 "SM3FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x120+0x06)++0x01 line.word 0x00 "SM3CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x120+0x0A)++0x17 line.word 0x00 "SM3VAL0,Value Register 0" line.word 0x02 "SM3FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM3VAL1,Value Register 1" line.word 0x06 "SM3FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM3VAL2,Value Register 2" line.word 0x0A "SM3FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM3VAL3,Value Register 3" line.word 0x0E "SM3FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM3VAL4,Value Register 4" line.word 0x12 "SM3FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM3VAL5,Value Register 5" line.word 0x16 "SM3FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x120+0x22)++0x0B line.word 0x00 "SM3OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM3STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM3INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM3DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM3TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM3DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x120+0x30)++0x0F line.word 0x00 "SM3DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM3DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM3CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM3CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM3CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM3CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM3CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM3CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x120+0x40)++0x17 line.word 0x00 "SM3CVAL0,Capture Value 0 Register" line.word 0x02 "SM3CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM3CVAL1,Capture Value 1 Register" line.word 0x06 "SM3CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM3CVAL2,Capture Value 2 Register" line.word 0x0A "SM3CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM3CVAL3,Capture Value 3 Register" line.word 0x0E "SM3CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM3CVAL4,Capture Value 4 Register" line.word 0x12 "SM3CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM3CVAL5,Capture Value 5 Register" line.word 0x16 "SM3CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x180++0x15 line.word 0x00 "OUTEN,Output Enable Register" bitfld.word 0x00 11. " PWMA_EN[3] ,PWM_A output 3 enable" "Disabled,Enabled" bitfld.word 0x00 10. " [2] ,PWM_A output 2 enable" "Disabled,Enabled" bitfld.word 0x00 9. " [1] ,PWM_A output 1 enable" "Disabled,Enabled" bitfld.word 0x00 8. " [0] ,PWM_A output 0 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PWMB_EN[3] ,PWM_B output 3 enable" "Disabled,Enabled" bitfld.word 0x00 6. " [2] ,PWM_B output 2 enable" "Disabled,Enabled" bitfld.word 0x00 5. " [1] ,PWM_B output 1 enable" "Disabled,Enabled" bitfld.word 0x00 4. " [0] ,PWM_B output 0 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PWMX_EN[3] ,PWM_X output 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " [2] ,PWM_X output 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " [1] ,PWM_X output 1 enable" "Disabled,Enabled" bitfld.word 0x00 0. " [0] ,PWM_X output 0 enable" "Disabled,Enabled" line.word 0x02 "MASK,Mask Register" eventfld.word 0x02 15. " UPDATE_MASK[3] ,Update mask bit of PWM_X submodule 3 Immediately" "No effect,Update" eventfld.word 0x02 14. " [2] ,Update mask bit of PWM_X submodule 2 Immediately" "No effect,Update" eventfld.word 0x02 13. " [1] ,Update mask bit of PWM_X submodule 1 Immediately" "No effect,Update" eventfld.word 0x02 12. " [0] ,Update mask bit of PWM_X submodule 0 Immediately" "No effect,Update" textline " " bitfld.word 0x02 11. " MASKA[3] ,PWM_A mask 3" "Not masked,Masked" bitfld.word 0x02 10. " [2] ,PWM_A mask 2" "Not masked,Masked" bitfld.word 0x02 9. " [1] ,PWM_A mask 1" "Not masked,Masked" bitfld.word 0x02 8. " [0] ,PWM_A mask 0" "Not masked,Masked" textline " " bitfld.word 0x02 7. " MASKB[3] ,PWM_B mask 3" "Not masked,Masked" bitfld.word 0x02 6. " [2] ,PWM_B mask 2" "Not masked,Masked" bitfld.word 0x02 5. " [1] ,PWM_B mask 1" "Not masked,Masked" bitfld.word 0x02 4. " [0] ,PWM_B mask 0" "Not masked,Masked" textline " " bitfld.word 0x02 3. " MASKX[3] ,PWM_X mask 3" "Not masked,Masked" bitfld.word 0x02 2. " [2] ,PWM_X mask 2" "Not masked,Masked" bitfld.word 0x02 1. " [1] ,PWM_X mask 1" "Not masked,Masked" bitfld.word 0x02 0. " [0] ,PWM_X mask 0" "Not masked,Masked" line.word 0x04 "SWCOUT,Software Controlled Output Register" bitfld.word 0x04 7. " SM3OUT23 ,Submodule 3 software controlled output 23" "0,1" bitfld.word 0x04 6. " SM3OUT45 ,Submodule 3 software controlled output 45" "0,1" bitfld.word 0x04 5. " SM2OUT23 ,Submodule 2 software controlled output 23" "0,1" bitfld.word 0x04 4. " SM2OUT45 ,Submodule 2 software controlled output 45" "0,1" textline " " bitfld.word 0x04 3. " SM1OUT23 ,Submodule 1 software controlled output 23" "0,1" bitfld.word 0x04 2. " SM1OUT45 ,Submodule 1 software controlled output 45" "0,1" bitfld.word 0x04 1. " SM0OUT23 ,Submodule 0 software controlled output 23" "0,1" bitfld.word 0x04 0. " SM0OUT45 ,Submodule 0 software controlled output 45" "0,1" line.word 0x06 "DTSRCSEL,PWM Source Select Register" bitfld.word 0x06 14.--15. " SM3SEL23 ,Submodule 3 PWM23 control select" "SM3PWM23,Inverted SM3PWM23,SWCOUT[SM3OUT23],PWM_EXTA3" bitfld.word 0x06 12.--13. " SM3SEL45 ,Submodule 3 PWM45 control select" "SM3PWM45,Inverted SM3PWM45,SWCOUT[SM3OUT45],PWM_EXTB3" bitfld.word 0x06 10.--11. " SM2SEL23 ,Submodule 2 PWM23 control select" "SM2PWM23,Inverted SM2PWM23,SWCOUT[SM2OUT23],PWM_EXTA2" bitfld.word 0x06 8.--9. " SM2SEL45 ,Submodule 2 PWM45 control select" "SM2PWM45,Inverted SM2PWM45,SWCOUT[SM2OUT45],PWM_EXTB2" textline " " bitfld.word 0x06 6.--7. " SM1SEL23 ,Submodule 1 PWM23 control select" "SM1PWM23,Inverted SM1PWM23,SWCOUT[SM1OUT23],PWM_EXTA1" bitfld.word 0x06 4.--5. " SM1SEL45 ,Submodule 1 PWM45 control select" "SM1PWM45,Inverted SM1PWM45,SWCOUT[SM1OUT45],PWM_EXTB1" bitfld.word 0x06 2.--3. " SM0SEL23 ,Submodule 0 PWM23 control select" "SM0PWM23,Inverted SM0WM23,SWCOUT[SM0OUT23],PWM_EXTA0" bitfld.word 0x06 0.--1. " SM0SEL45 ,Submodule 0 PWM45 control select" "SM0PWM45,Inverted SM0PWM45,SWCOUT[SM0OUT45],PWM_EXTB0" line.word 0x08 "MCTRL0,Master Control 0 Register" bitfld.word 0x08 15. " IPOL[3] ,Current polarity of submodule 3" "PWM23,PWM45" bitfld.word 0x08 14. " [2] ,Current polarity of submodule 2" "PWM23,PWM45" bitfld.word 0x08 13. " [1] ,Current polarity of submodule 1" "PWM23,PWM45" bitfld.word 0x08 12. " [0] ,Current polarity of submodule 0" "PWM23,PWM45" textline " " bitfld.word 0x08 11. " RUN[3] , PWM generator of submodule 3" "Disabled,Enabled" bitfld.word 0x08 10. " [2] , PWM generator of submodule 2" "Disabled,Enabled" bitfld.word 0x08 9. " [1] , PWM generator of submodule 1" "Disabled,Enabled" bitfld.word 0x08 8. " [0] , PWM generator of submodule 0" "Disabled,Enabled" textline " " bitfld.word 0x08 7. " CLDOK[3] ,LDOK 3 clear" "No effect,Cleared" bitfld.word 0x08 6. " [2] ,LDOK 2 clear" "No effect,Cleared" bitfld.word 0x08 5. " [1] ,LDOK 1 clear" "No effect,Cleared" bitfld.word 0x08 4. " [0] ,LDOK 0 clear" "No effect,Cleared" textline " " bitfld.word 0x08 3. " LDOK[3] ,Load okay of submodule 3" "Not loaded,Loaded" bitfld.word 0x08 2. " [2] ,Load okay of submodule 2" "Not loaded,Loaded" bitfld.word 0x08 1. " [1] ,Load okay of submodule 1" "Not loaded,Loaded" bitfld.word 0x08 0. " [0] ,Load okay of submodule 0" "Not loaded,Loaded" line.word 0x0A "MCTRL2,Master Control 2 Register" bitfld.word 0x0A 0.--1. " MONPLL ,Monitor PLL state" "Not locked(Do not monitor),Not locked(Monitor),Locked(Do not monitor),Locked(Monitor)" line.word 0x0C "FCTRL0,Fault Control Register" bitfld.word 0x0C 15. " FLVL[3] ,Fault 3 level" "Logic 0,Logic 1" bitfld.word 0x0C 14. " [2] ,Fault 2 level" "Logic 0,Logic 1" bitfld.word 0x0C 13. " [1] ,Fault 1 level" "Logic 0,Logic 1" bitfld.word 0x0C 12. " [0] ,Fault 0 level" "Logic 0,Logic 1" textline " " bitfld.word 0x0C 11. " FAUTO[3] ,Automatic fault clearing 3" "Manual,Automatic" bitfld.word 0x0C 10. " [2] ,Automatic fault clearing 2" "Manual,Automatic" bitfld.word 0x0C 9. " [1] ,Automatic fault clearing 1" "Manual,Automatic" bitfld.word 0x0C 8. " [0] ,Automatic fault clearing 0" "Manual,Automatic" textline " " bitfld.word 0x0C 7. " FSAFE[3] ,Fault safety mode 3" "Normal,Safe" bitfld.word 0x0C 6. " [2] ,Fault safety mode 2" "Normal,Safe" bitfld.word 0x0C 5. " [1] ,Fault safety mode 1" "Normal,Safe" bitfld.word 0x0C 4. " [0] ,Fault safety mode 0" "Normal,Safe" textline " " bitfld.word 0x0C 3. " FIE[3] ,Fault interrupt enable 3" "Disabled,Enabled" bitfld.word 0x0C 2. " [2] ,Fault interrupt enable 2" "Disabled,Enabled" bitfld.word 0x0C 1. " [1] ,Fault interrupt enable 1" "Disabled,Enabled" bitfld.word 0x0C 0. " [0] ,Fault interrupt enable 0" "Disabled,Enabled" line.word 0x0E "FSTS0,Fault Status Register" bitfld.word 0x0E 15. " FHALF[3] ,Half cycle fault 3 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 14. " [2] ,Half cycle fault 2 Recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 13. " [1] ,Half cycle fault 1 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 12. " [0] ,Half cycle fault 0 recovery" "Not re-enabled,Re-enabled" textline " " rbitfld.word 0x0E 11. " FFPIN[3] ,Filtered fault pin 3" "Not occurred,Occurred" rbitfld.word 0x0E 10. " [2] ,Filtered fault pin 2" "Not occurred,Occurred" rbitfld.word 0x0E 9. " [1] ,Filtered fault pin 1" "Not occurred,Occurred" rbitfld.word 0x0E 8. " [0] ,Filtered fault pin 0" "Not occurred,Occurred" textline " " bitfld.word 0x0E 7. " FFULL[3] ,Full Cycle 3" "Not re-enabled,Re-enabled" bitfld.word 0x0E 6. " [2] ,Full cycle 2" "Not re-enabled,Re-enabled" bitfld.word 0x0E 5. " [1] ,Full cycle 1" "Not re-enabled,Re-enabled" bitfld.word 0x0E 4. " [0] ,Full cycle 0" "Not re-enabled,Re-enabled" textline " " eventfld.word 0x0E 3. " FFLAG[3] ,Fault Flag 3" "Not fault,Fault" eventfld.word 0x0E 2. " [2] ,Fault flag 2" "Not fault,Fault" eventfld.word 0x0E 1. " [1] ,Fault flag 1" "Not fault,Fault" eventfld.word 0x0E 0. " [0] ,Fault flag 0" "Not fault,Fault" line.word 0x10 "FFILT0,Fault Filter Register" bitfld.word 0x10 15. " GSTR ,Fault glitch stretch enable" "Disabled,Enabled" bitfld.word 0x10 8.--10. " FILT_CNT ,Fault filter count" "3,4,5,6,7,8,9,10" hexmask.word.byte 0x10 0.--7. 1. " FILT_PER ,Fault Filter period" line.word 0x12 "FTST,Fault Test Register" bitfld.word 0x12 0. " FTEST ,Fault test" "Not fault,Simulated fault" line.word 0x14 "FCTRL2,Fault control 2 register" bitfld.word 0x14 3. " NOCOMB[3] ,No Combinational Path From Fault Input To PWM Output" "No,Yes" bitfld.word 0x14 2. " [2] ,No combinational path from fault input To PWM output" "No,Yes" bitfld.word 0x14 1. " [1] ,No combinational path from fault input To PWM output" "No,Yes" bitfld.word 0x14 0. " [0] ,No combinational path from fault input to PWM output" "No,Yes" width 0x0B tree.end tree "PWM1" base ad:0x400B3000 width 14. rgroup.word 0x0++0x01 line.word 0x00 "SM0CNT,Counter Register" if (((per.l(ad:0x400B3000+0x188))&(0x01<<0))==(0x01<<0)) rgroup.word (0x0+0x02)++0x01 line.word 0x00 "SM0INIT,Initial Count Register" else group.word (0x0+0x02)++0x01 line.word 0x00 "SM0INIT,Initial Count Register" endif group.word (0x0+0x04)++0x1 line.word 0x00 "SM0CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x400B3000+0x188))&(0x01<<0))==(0x01<<0)) group.word (0x0+0x06)++0x01 line.word 0x00 "SM0CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x0+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x0+0x20)++0x01 line.word 0x00 "SM0FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x0+0x06)++0x01 line.word 0x00 "SM0CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x0+0x0A)++0x17 line.word 0x00 "SM0VAL0,Value Register 0" line.word 0x02 "SM0FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM0VAL1,Value Register 1" line.word 0x06 "SM0FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM0VAL2,Value Register 2" line.word 0x0A "SM0FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM0VAL3,Value Register 3" line.word 0x0E "SM0FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM0VAL4,Value Register 4" line.word 0x12 "SM0FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM0VAL5,Value Register 5" line.word 0x16 "SM0FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x0+0x22)++0x0B line.word 0x00 "SM0OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM0STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM0INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM0DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM0TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM0DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x0+0x30)++0x0F line.word 0x00 "SM0DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM0DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM0CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM0CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM0CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM0CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM0CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM0CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x0+0x40)++0x17 line.word 0x00 "SM0CVAL0,Capture Value 0 Register" line.word 0x02 "SM0CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM0CVAL1,Capture Value 1 Register" line.word 0x06 "SM0CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM0CVAL2,Capture Value 2 Register" line.word 0x0A "SM0CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM0CVAL3,Capture Value 3 Register" line.word 0x0E "SM0CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM0CVAL4,Capture Value 4 Register" line.word 0x12 "SM0CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM0CVAL5,Capture Value 5 Register" line.word 0x16 "SM0CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x60++0x01 line.word 0x00 "SM1CNT,Counter Register" if (((per.l(ad:0x400B3000+0x188))&(0x01<<1))==(0x01<<1)) rgroup.word (0x60+0x02)++0x01 line.word 0x00 "SM1INIT,Initial Count Register" else group.word (0x60+0x02)++0x01 line.word 0x00 "SM1INIT,Initial Count Register" endif group.word (0x60+0x04)++0x1 line.word 0x00 "SM1CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x400B3000+0x188))&(0x01<<1))==(0x01<<1)) group.word (0x60+0x06)++0x01 line.word 0x00 "SM1CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x60+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x60+0x20)++0x01 line.word 0x00 "SM1FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x60+0x06)++0x01 line.word 0x00 "SM1CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x60+0x0A)++0x17 line.word 0x00 "SM1VAL0,Value Register 0" line.word 0x02 "SM1FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM1VAL1,Value Register 1" line.word 0x06 "SM1FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM1VAL2,Value Register 2" line.word 0x0A "SM1FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM1VAL3,Value Register 3" line.word 0x0E "SM1FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM1VAL4,Value Register 4" line.word 0x12 "SM1FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM1VAL5,Value Register 5" line.word 0x16 "SM1FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x60+0x22)++0x0B line.word 0x00 "SM1OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM1STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM1INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM1DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM1TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM1DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x60+0x30)++0x0F line.word 0x00 "SM1DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM1DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM1CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM1CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM1CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM1CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM1CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM1CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x60+0x40)++0x17 line.word 0x00 "SM1CVAL0,Capture Value 0 Register" line.word 0x02 "SM1CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM1CVAL1,Capture Value 1 Register" line.word 0x06 "SM1CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM1CVAL2,Capture Value 2 Register" line.word 0x0A "SM1CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM1CVAL3,Capture Value 3 Register" line.word 0x0E "SM1CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM1CVAL4,Capture Value 4 Register" line.word 0x12 "SM1CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM1CVAL5,Capture Value 5 Register" line.word 0x16 "SM1CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xC0++0x01 line.word 0x00 "SM2CNT,Counter Register" if (((per.l(ad:0x400B3000+0x188))&(0x01<<2))==(0x01<<2)) rgroup.word (0xC0+0x02)++0x01 line.word 0x00 "SM2INIT,Initial Count Register" else group.word (0xC0+0x02)++0x01 line.word 0x00 "SM2INIT,Initial Count Register" endif group.word (0xC0+0x04)++0x1 line.word 0x00 "SM2CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x400B3000+0x188))&(0x01<<2))==(0x01<<2)) group.word (0xC0+0x06)++0x01 line.word 0x00 "SM2CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0xC0+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0xC0+0x20)++0x01 line.word 0x00 "SM2FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0xC0+0x06)++0x01 line.word 0x00 "SM2CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0xC0+0x0A)++0x17 line.word 0x00 "SM2VAL0,Value Register 0" line.word 0x02 "SM2FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM2VAL1,Value Register 1" line.word 0x06 "SM2FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM2VAL2,Value Register 2" line.word 0x0A "SM2FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM2VAL3,Value Register 3" line.word 0x0E "SM2FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM2VAL4,Value Register 4" line.word 0x12 "SM2FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM2VAL5,Value Register 5" line.word 0x16 "SM2FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0xC0+0x22)++0x0B line.word 0x00 "SM2OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM2STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM2INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM2DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM2TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM2DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0xC0+0x30)++0x0F line.word 0x00 "SM2DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM2DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM2CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM2CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM2CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM2CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM2CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM2CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0xC0+0x40)++0x17 line.word 0x00 "SM2CVAL0,Capture Value 0 Register" line.word 0x02 "SM2CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM2CVAL1,Capture Value 1 Register" line.word 0x06 "SM2CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM2CVAL2,Capture Value 2 Register" line.word 0x0A "SM2CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM2CVAL3,Capture Value 3 Register" line.word 0x0E "SM2CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM2CVAL4,Capture Value 4 Register" line.word 0x12 "SM2CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM2CVAL5,Capture Value 5 Register" line.word 0x16 "SM2CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x120++0x01 line.word 0x00 "SM3CNT,Counter Register" if (((per.l(ad:0x400B3000+0x188))&(0x01<<3))==(0x01<<3)) rgroup.word (0x120+0x02)++0x01 line.word 0x00 "SM3INIT,Initial Count Register" else group.word (0x120+0x02)++0x01 line.word 0x00 "SM3INIT,Initial Count Register" endif group.word (0x120+0x04)++0x1 line.word 0x00 "SM3CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "0,1" textline " " bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "0,1" bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "0,1" bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " FORCE ,Force Initialization" "No effect,Initialized" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." if (((per.l(ad:0x400B3000+0x188))&(0x01<<3))==(0x01<<3)) group.word (0x120+0x06)++0x01 line.word 0x00 "SM3CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half Cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" rbitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" rgroup.word (0x120+0x0A)++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "VAL5,Value Register 5" group.word (0x120+0x20)++0x01 line.word 0x00 "SM3FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status Bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" rbitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" rbitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " rbitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" else group.word (0x120+0x06)++0x01 line.word 0x00 "SM3CTRL,Control Register" bitfld.word 0x00 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x00 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x00 9. " DT[1] ,PWMX input after deadtime 1" "0,1" textline " " rbitfld.word 0x00 8. " [0] ,PWMX input after deadtime 0" "0,1" bitfld.word 0x00 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 2. " LDMOD ,Load mode select" "Next Reload,Immediately" bitfld.word 0x00 1. " DBLX ,PWMX double switching enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word (0x120+0x0A)++0x17 line.word 0x00 "SM3VAL0,Value Register 0" line.word 0x02 "SM3FRACVAL1,Fractional Value Register 1" bitfld.word 0x02 11.--15. " FRACVAL1 ,Fractional value 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "SM3VAL1,Value Register 1" line.word 0x06 "SM3FRACVAL2,Fractional Value Register 2" bitfld.word 0x06 11.--15. " FRACVAL2 ,Fractional value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x08 "SM3VAL2,Value Register 2" line.word 0x0A "SM3FRACVAL3,Fractional Value Register 3" bitfld.word 0x0A 11.--15. " FRACVAL3 ,Fractional value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "SM3VAL3,Value Register 3" line.word 0x0E "SM3FRACVAL4,Fractional Value Register 4" bitfld.word 0x0E 11.--15. " FRACVAL4 ,Fractional value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x10 "SM3VAL4,Value Register 4" line.word 0x12 "SM3FRACVAL5,Fractional Value Register 5" bitfld.word 0x12 11.--15. " FRACVAL5 ,Fractional value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x14 "SM3VAL5,Value Register 5" line.word 0x16 "SM3FRCTRL,Fractional Control Register" rbitfld.word 0x16 15. " TEST ,Test Status Bit" "0,1" bitfld.word 0x16 8. " FRAC_PU ,Fractional delay circuit power Up" "Powered down,Powered up" bitfld.word 0x16 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x16 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" textline " " bitfld.word 0x16 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" endif group.word (0x120+0x22)++0x0B line.word 0x00 "SM3OCTRL,Output Control Register" rbitfld.word 0x00 15. " PWMA_IN ,PWM_A Input" "0,1" rbitfld.word 0x00 14. " PWMB_IN ,PWM_B Input" "0,1" rbitfld.word 0x00 13. " PWMX_IN ,PWM_X Input" "0,1" bitfld.word 0x00 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" textline " " bitfld.word 0x00 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" bitfld.word 0x00 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" bitfld.word 0x00 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x00 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" textline " " bitfld.word 0x00 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x02 "SM3STS,Status Register" rbitfld.word 0x02 14. " RUF ,Registers Updated flag" "Not Updated,Updated" eventfld.word 0x02 13. " REF ,Reload error Flag" "No error,Error" eventfld.word 0x02 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x02 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" textline " " eventfld.word 0x02 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x02 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x02 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" eventfld.word 0x02 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" textline " " eventfld.word 0x02 6. " CFX0 ,Capture Flag X0" "Not occurred,Occurred" eventfld.word 0x02 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x02 4. " [4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x02 3. " [3] ,Compare flag VAL3" "Not occurred,Occurred" textline " " eventfld.word 0x02 2. " [2] ,Compare flag VAL2" "Not occurred,Occurred" eventfld.word 0x02 1. " [1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x02 0. " [0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x04 "SM3INTEN,Interrupt Enable Register" bitfld.word 0x04 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x04 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x04 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x04 5. " CMPIE[5] ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x04 4. " [4] ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x04 3. " [3] ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x04 2. " [2] ,Compare interrupt enable 2" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " [1] ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x04 0. " [0] ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x06 "SM3DMAEN,DMA Enable Register" bitfld.word 0x06 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x06 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x06 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x06 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x06 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x08 "SM3TCTRL,Output Trigger Control Register" bitfld.word 0x08 15. " PWAOT0 ,Output Trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x08 14. " PWBOT1 ,Output Trigger 1 Source Select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x08 12. " TRGFRQ ,Trigger frequency" "Every PWM period,Final PWM period" bitfld.word 0x08 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" bitfld.word 0x08 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x08 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x08 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x08 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0A "SM3DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0A 11. " DIS0X_3 ,PWM_X fault disable Mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" textline " " bitfld.word 0x0A 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0A 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0A 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0A 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" group.word (0x120+0x30)++0x0F line.word 0x00 "SM3DTCNT0,Deadtime Count Register 0" line.word 0x02 "SM3DTCNT1,Deadtime Count Register 1" line.word 0x04 "SM3CAPTCTRLA,Capture Control A Register" rbitfld.word 0x04 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" textline " " bitfld.word 0x04 6. " INP_SELA ,Input Select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x04 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTA ,One shot mode A" "Free run,One shot" textline " " bitfld.word 0x04 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x06 "SM3CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTA ,Edge Counter A" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x08 "SM3CAPTCTRLB,Capture Control B Register" rbitfld.word 0x08 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" textline " " bitfld.word 0x08 6. " INP_SELB ,Input Select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x08 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x08 1. " ONESHOTB ,One shot mode B" "Free run,One shot" textline " " bitfld.word 0x08 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x0A "SM3CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x0A 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x0A 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x0C "SM3CAPTCTRLX,Capture Control X Register" rbitfld.word 0x0C 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x0C 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x0C 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x0C 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" textline " " bitfld.word 0x0C 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x0C 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x0C 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" textline " " bitfld.word 0x0C 1. " ONESHOTX ,One Shot mode X" "Free run,One shot" bitfld.word 0x0C 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0E "SM3CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x0E 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x0E 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word (0x120+0x40)++0x17 line.word 0x00 "SM3CVAL0,Capture Value 0 Register" line.word 0x02 "SM3CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x04 "SM3CVAL1,Capture Value 1 Register" line.word 0x06 "SM3CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x06 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x08 "SM3CVAL2,Capture Value 2 Register" line.word 0x0A "SM3CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x0A 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0C "SM3CVAL3,Capture Value 3 Register" line.word 0x0E "SM3CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x0E 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x10 "SM3CVAL4,Capture Value 4 Register" line.word 0x12 "SM3CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x12 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x14 "SM3CVAL5,Capture Value 5 Register" line.word 0x16 "SM3CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x16 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x180++0x15 line.word 0x00 "OUTEN,Output Enable Register" bitfld.word 0x00 11. " PWMA_EN[3] ,PWM_A output 3 enable" "Disabled,Enabled" bitfld.word 0x00 10. " [2] ,PWM_A output 2 enable" "Disabled,Enabled" bitfld.word 0x00 9. " [1] ,PWM_A output 1 enable" "Disabled,Enabled" bitfld.word 0x00 8. " [0] ,PWM_A output 0 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PWMB_EN[3] ,PWM_B output 3 enable" "Disabled,Enabled" bitfld.word 0x00 6. " [2] ,PWM_B output 2 enable" "Disabled,Enabled" bitfld.word 0x00 5. " [1] ,PWM_B output 1 enable" "Disabled,Enabled" bitfld.word 0x00 4. " [0] ,PWM_B output 0 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PWMX_EN[3] ,PWM_X output 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " [2] ,PWM_X output 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " [1] ,PWM_X output 1 enable" "Disabled,Enabled" bitfld.word 0x00 0. " [0] ,PWM_X output 0 enable" "Disabled,Enabled" line.word 0x02 "MASK,Mask Register" eventfld.word 0x02 15. " UPDATE_MASK[3] ,Update mask bit of PWM_X submodule 3 Immediately" "No effect,Update" eventfld.word 0x02 14. " [2] ,Update mask bit of PWM_X submodule 2 Immediately" "No effect,Update" eventfld.word 0x02 13. " [1] ,Update mask bit of PWM_X submodule 1 Immediately" "No effect,Update" eventfld.word 0x02 12. " [0] ,Update mask bit of PWM_X submodule 0 Immediately" "No effect,Update" textline " " bitfld.word 0x02 11. " MASKA[3] ,PWM_A mask 3" "Not masked,Masked" bitfld.word 0x02 10. " [2] ,PWM_A mask 2" "Not masked,Masked" bitfld.word 0x02 9. " [1] ,PWM_A mask 1" "Not masked,Masked" bitfld.word 0x02 8. " [0] ,PWM_A mask 0" "Not masked,Masked" textline " " bitfld.word 0x02 7. " MASKB[3] ,PWM_B mask 3" "Not masked,Masked" bitfld.word 0x02 6. " [2] ,PWM_B mask 2" "Not masked,Masked" bitfld.word 0x02 5. " [1] ,PWM_B mask 1" "Not masked,Masked" bitfld.word 0x02 4. " [0] ,PWM_B mask 0" "Not masked,Masked" textline " " bitfld.word 0x02 3. " MASKX[3] ,PWM_X mask 3" "Not masked,Masked" bitfld.word 0x02 2. " [2] ,PWM_X mask 2" "Not masked,Masked" bitfld.word 0x02 1. " [1] ,PWM_X mask 1" "Not masked,Masked" bitfld.word 0x02 0. " [0] ,PWM_X mask 0" "Not masked,Masked" line.word 0x04 "SWCOUT,Software Controlled Output Register" bitfld.word 0x04 7. " SM3OUT23 ,Submodule 3 software controlled output 23" "0,1" bitfld.word 0x04 6. " SM3OUT45 ,Submodule 3 software controlled output 45" "0,1" bitfld.word 0x04 5. " SM2OUT23 ,Submodule 2 software controlled output 23" "0,1" bitfld.word 0x04 4. " SM2OUT45 ,Submodule 2 software controlled output 45" "0,1" textline " " bitfld.word 0x04 3. " SM1OUT23 ,Submodule 1 software controlled output 23" "0,1" bitfld.word 0x04 2. " SM1OUT45 ,Submodule 1 software controlled output 45" "0,1" bitfld.word 0x04 1. " SM0OUT23 ,Submodule 0 software controlled output 23" "0,1" bitfld.word 0x04 0. " SM0OUT45 ,Submodule 0 software controlled output 45" "0,1" line.word 0x06 "DTSRCSEL,PWM Source Select Register" bitfld.word 0x06 14.--15. " SM3SEL23 ,Submodule 3 PWM23 control select" "SM3PWM23,Inverted SM3PWM23,SWCOUT[SM3OUT23],PWM_EXTA3" bitfld.word 0x06 12.--13. " SM3SEL45 ,Submodule 3 PWM45 control select" "SM3PWM45,Inverted SM3PWM45,SWCOUT[SM3OUT45],PWM_EXTB3" bitfld.word 0x06 10.--11. " SM2SEL23 ,Submodule 2 PWM23 control select" "SM2PWM23,Inverted SM2PWM23,SWCOUT[SM2OUT23],PWM_EXTA2" bitfld.word 0x06 8.--9. " SM2SEL45 ,Submodule 2 PWM45 control select" "SM2PWM45,Inverted SM2PWM45,SWCOUT[SM2OUT45],PWM_EXTB2" textline " " bitfld.word 0x06 6.--7. " SM1SEL23 ,Submodule 1 PWM23 control select" "SM1PWM23,Inverted SM1PWM23,SWCOUT[SM1OUT23],PWM_EXTA1" bitfld.word 0x06 4.--5. " SM1SEL45 ,Submodule 1 PWM45 control select" "SM1PWM45,Inverted SM1PWM45,SWCOUT[SM1OUT45],PWM_EXTB1" bitfld.word 0x06 2.--3. " SM0SEL23 ,Submodule 0 PWM23 control select" "SM0PWM23,Inverted SM0WM23,SWCOUT[SM0OUT23],PWM_EXTA0" bitfld.word 0x06 0.--1. " SM0SEL45 ,Submodule 0 PWM45 control select" "SM0PWM45,Inverted SM0PWM45,SWCOUT[SM0OUT45],PWM_EXTB0" line.word 0x08 "MCTRL0,Master Control 0 Register" bitfld.word 0x08 15. " IPOL[3] ,Current polarity of submodule 3" "PWM23,PWM45" bitfld.word 0x08 14. " [2] ,Current polarity of submodule 2" "PWM23,PWM45" bitfld.word 0x08 13. " [1] ,Current polarity of submodule 1" "PWM23,PWM45" bitfld.word 0x08 12. " [0] ,Current polarity of submodule 0" "PWM23,PWM45" textline " " bitfld.word 0x08 11. " RUN[3] , PWM generator of submodule 3" "Disabled,Enabled" bitfld.word 0x08 10. " [2] , PWM generator of submodule 2" "Disabled,Enabled" bitfld.word 0x08 9. " [1] , PWM generator of submodule 1" "Disabled,Enabled" bitfld.word 0x08 8. " [0] , PWM generator of submodule 0" "Disabled,Enabled" textline " " bitfld.word 0x08 7. " CLDOK[3] ,LDOK 3 clear" "No effect,Cleared" bitfld.word 0x08 6. " [2] ,LDOK 2 clear" "No effect,Cleared" bitfld.word 0x08 5. " [1] ,LDOK 1 clear" "No effect,Cleared" bitfld.word 0x08 4. " [0] ,LDOK 0 clear" "No effect,Cleared" textline " " bitfld.word 0x08 3. " LDOK[3] ,Load okay of submodule 3" "Not loaded,Loaded" bitfld.word 0x08 2. " [2] ,Load okay of submodule 2" "Not loaded,Loaded" bitfld.word 0x08 1. " [1] ,Load okay of submodule 1" "Not loaded,Loaded" bitfld.word 0x08 0. " [0] ,Load okay of submodule 0" "Not loaded,Loaded" line.word 0x0A "MCTRL2,Master Control 2 Register" bitfld.word 0x0A 0.--1. " MONPLL ,Monitor PLL state" "Not locked(Do not monitor),Not locked(Monitor),Locked(Do not monitor),Locked(Monitor)" line.word 0x0C "FCTRL0,Fault Control Register" bitfld.word 0x0C 15. " FLVL[3] ,Fault 3 level" "Logic 0,Logic 1" bitfld.word 0x0C 14. " [2] ,Fault 2 level" "Logic 0,Logic 1" bitfld.word 0x0C 13. " [1] ,Fault 1 level" "Logic 0,Logic 1" bitfld.word 0x0C 12. " [0] ,Fault 0 level" "Logic 0,Logic 1" textline " " bitfld.word 0x0C 11. " FAUTO[3] ,Automatic fault clearing 3" "Manual,Automatic" bitfld.word 0x0C 10. " [2] ,Automatic fault clearing 2" "Manual,Automatic" bitfld.word 0x0C 9. " [1] ,Automatic fault clearing 1" "Manual,Automatic" bitfld.word 0x0C 8. " [0] ,Automatic fault clearing 0" "Manual,Automatic" textline " " bitfld.word 0x0C 7. " FSAFE[3] ,Fault safety mode 3" "Normal,Safe" bitfld.word 0x0C 6. " [2] ,Fault safety mode 2" "Normal,Safe" bitfld.word 0x0C 5. " [1] ,Fault safety mode 1" "Normal,Safe" bitfld.word 0x0C 4. " [0] ,Fault safety mode 0" "Normal,Safe" textline " " bitfld.word 0x0C 3. " FIE[3] ,Fault interrupt enable 3" "Disabled,Enabled" bitfld.word 0x0C 2. " [2] ,Fault interrupt enable 2" "Disabled,Enabled" bitfld.word 0x0C 1. " [1] ,Fault interrupt enable 1" "Disabled,Enabled" bitfld.word 0x0C 0. " [0] ,Fault interrupt enable 0" "Disabled,Enabled" line.word 0x0E "FSTS0,Fault Status Register" bitfld.word 0x0E 15. " FHALF[3] ,Half cycle fault 3 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 14. " [2] ,Half cycle fault 2 Recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 13. " [1] ,Half cycle fault 1 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 12. " [0] ,Half cycle fault 0 recovery" "Not re-enabled,Re-enabled" textline " " rbitfld.word 0x0E 11. " FFPIN[3] ,Filtered fault pin 3" "Not occurred,Occurred" rbitfld.word 0x0E 10. " [2] ,Filtered fault pin 2" "Not occurred,Occurred" rbitfld.word 0x0E 9. " [1] ,Filtered fault pin 1" "Not occurred,Occurred" rbitfld.word 0x0E 8. " [0] ,Filtered fault pin 0" "Not occurred,Occurred" textline " " bitfld.word 0x0E 7. " FFULL[3] ,Full Cycle 3" "Not re-enabled,Re-enabled" bitfld.word 0x0E 6. " [2] ,Full cycle 2" "Not re-enabled,Re-enabled" bitfld.word 0x0E 5. " [1] ,Full cycle 1" "Not re-enabled,Re-enabled" bitfld.word 0x0E 4. " [0] ,Full cycle 0" "Not re-enabled,Re-enabled" textline " " eventfld.word 0x0E 3. " FFLAG[3] ,Fault Flag 3" "Not fault,Fault" eventfld.word 0x0E 2. " [2] ,Fault flag 2" "Not fault,Fault" eventfld.word 0x0E 1. " [1] ,Fault flag 1" "Not fault,Fault" eventfld.word 0x0E 0. " [0] ,Fault flag 0" "Not fault,Fault" line.word 0x10 "FFILT0,Fault Filter Register" bitfld.word 0x10 15. " GSTR ,Fault glitch stretch enable" "Disabled,Enabled" bitfld.word 0x10 8.--10. " FILT_CNT ,Fault filter count" "3,4,5,6,7,8,9,10" hexmask.word.byte 0x10 0.--7. 1. " FILT_PER ,Fault Filter period" line.word 0x12 "FTST,Fault Test Register" bitfld.word 0x12 0. " FTEST ,Fault test" "Not fault,Simulated fault" line.word 0x14 "FCTRL2,Fault control 2 register" bitfld.word 0x14 3. " NOCOMB[3] ,No Combinational Path From Fault Input To PWM Output" "No,Yes" bitfld.word 0x14 2. " [2] ,No combinational path from fault input To PWM output" "No,Yes" bitfld.word 0x14 1. " [1] ,No combinational path from fault input To PWM output" "No,Yes" bitfld.word 0x14 0. " [0] ,No combinational path from fault input to PWM output" "No,Yes" width 0x0B tree.end tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x40037000 width 9. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" sif cpuis("MKV5*") rgroup.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" endif group.long 0x100++0x03 "PIT0 Registers" line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CVAL0,PIT0 Current Timer Value Register" group.long (0x100+0x08)++0x07 line.long 0x00 "TCTRL0,PIT0 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG0,PIT0 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x110++0x03 "PIT1 Registers" line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register" rgroup.long (0x110+0x04)++0x03 line.long 0x00 "CVAL1,PIT1 Current Timer Value Register" group.long (0x110+0x08)++0x07 line.long 0x00 "TCTRL1,PIT1 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG1,PIT1 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x120++0x03 "PIT2 Registers" line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register" rgroup.long (0x120+0x04)++0x03 line.long 0x00 "CVAL2,PIT2 Current Timer Value Register" group.long (0x120+0x08)++0x07 line.long 0x00 "TCTRL2,PIT2 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG2,PIT2 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x130++0x03 "PIT3 Registers" line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register" rgroup.long (0x130+0x04)++0x03 line.long 0x00 "CVAL3,PIT3 Current Timer Value Register" group.long (0x130+0x08)++0x07 line.long 0x00 "TCTRL3,PIT3 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG3,PIT3 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" width 0x0B tree.end tree.open "SPI (Serial Peripheral Interface)" tree "SPI0" base ad:0x4002C000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002C000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpu()=="MKV30F128VFM10"||cpu()=="MKV30F64VFM10"||cpuis("MKW2?D*")) bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "SPI1" base ad:0x4002D000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" textline " " bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000)&&(((per.l(ad:0x4002D000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x4002D000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " sif (cpu()=="MKV31F128VLH10"||cpu()=="MKV31F256VLH12"||cpu()=="MKV31F512VLH12") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" textline " " bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" elif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" endif textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x4002D000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "SPI2" base ad:0x400AC000 width 13. sif (cpuis("MKV5*")) if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) if ((per.l(ad:0x400AC000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,peripheral chip select strobe enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x400AC000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." rbitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,Configuration" "SPI,?..." textline " " bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" textline " " sif (cpuis("MKW*")) sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif elif (cpuis("MKV*")) bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" textline " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" endif textline " " bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" textline " " bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "-,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "-,Clear" textline " " bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif sif (cpuis("MKV5*")) if ((per.l(ad:0x400AC000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif (cpuis("MKV*")||cpuis("MKW*")) if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000)&&(((per.l(ad:0x400AC000+0x34))&0x70000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" elif ((per.l(ad:0x400AC000)&0x80000000)==0x80000000)&&(((per.l(ad:0x400AC000+0x34))&0x70000000)==0x10000000) hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase [capture/change]" "Leading/following,Following/leading" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" elif ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) hgroup.long 0x0C++0x07 hide.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" hide.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKV5*")) bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif else if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" textline " " bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" bitfld.long 0x00 24. " LSBFE ,LBS first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "1,3,5,7" textline " " bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "2,3,5,7" textline " " bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (Slave Mode)" bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" textline " " sif (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif textline " " eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" textline " " eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV5*") if ((per.l(ad:0x400AC000+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill dma/interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain dma/interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not ended,Ended" textline " " bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "-,Cleared" textline " " bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" textline " " hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register" sif (cpuis("MKV10Z*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")||cpuis("MKV5*")) if ((per.l(ad:0x400AC000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif textline " " sif (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW2?D*")) group.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" group.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" group.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" group.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" else hgroup.long 0x7C++0x03 hide.long 0x00 "RXFR0,Receive FIFO Register 0" textfld " " in hgroup.long 0x80++0x03 hide.long 0x00 "RXFR1,Receive FIFO Register 1" textfld " " in hgroup.long 0x84++0x03 hide.long 0x00 "RXFR2,Receive FIFO Register 2" textfld " " in hgroup.long 0x88++0x03 hide.long 0x00 "RXFR3,Receive FIFO Register 3" textfld " " in endif textline " " sif (cpuis("MKV10Z*")) group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" textline " " rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.end tree "ENET (10/100-Mbps Ethernet MAC)" base ad:0x400C0004 width 10. tree "Configuration Registers" group.long 0x04++0x7 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling Receive Error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling Transmit Error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful Stop Complete" "Not completed,Completed" eventfld.long 0x00 27. " TXF ,Transmit Frame Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive Frame Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive Buffer Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet Bus Error" "No error,Error" eventfld.long 0x00 21. " LC ,Late Collision (In half-duplex mode)" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision Retry Limit (In half-duplex mode)" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO Underrun" "No underrun,Underrun" textline " " eventfld.long 0x00 18. " PLR ,Payload Receive Error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node Wake-up Request" "Not requested,Requested" eventfld.long 0x00 16. " TS_AVAIL ,Transmit Timestamp Available" "Not available,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp Timer" "Not reached,Reached" sif (!cpuis("MKV5*")) textline " " eventfld.long 0x00 14. " RXFLUSH_2 ,RX DMA Ring 2 flush indication" "Not flushed,Flushed" eventfld.long 0x00 13. " RXFLUSH_1 ,RX DMA Ring 1 flush indication" "Not flushed,Flushed" eventfld.long 0x00 12. " RXFLUSH_0 ,RX DMA Ring 0 flush indication" "Not flushed,Flushed" eventfld.long 0x00 7. " TXF2 ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " TXB2 ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " RXF2 ,Receive frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " RXB2 ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " TXF1 ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " TXB1 ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " RXF1 ,Receive frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " RXB1 ,Receive buffer interrupt" "No interrupt,Interrupt" endif line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,Babbling Receive Error Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,Babbling Transmit Error Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,Graceful Stop Complete Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,Transmit Frame Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x04 26. " TXB ,Transmit Buffer Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,Receive Frame Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,Receive Buffer Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x04 22. " EBERR ,Ethernet Bus Error Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,Late Collision Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,Collision Retry Limit Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,Transmit FIFO Underrun Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x04 18. " PLR ,Payload Receive Error Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,Node Wake-up Request Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,Transmit Timestamp Available Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,Timestamp Timer Interrupt Mask" "Masked,Not masked" sif (!cpuis("MKV5*")) textline " " bitfld.long 0x04 14. " RXFLUSH_2 ,Corresponds to interrupt source EIR2" "Masked,Not masked" bitfld.long 0x04 13. " RXFLUSH_1 ,Corresponds to interrupt source EIR1" "Masked,Not masked" bitfld.long 0x04 12. " RXFLUSH_0 ,Corresponds to interrupt source EIR0" "Masked,Not masked" bitfld.long 0x04 7. " TXF2 ,Transmit frame interrupt" "Masked,Not masked" textline " " bitfld.long 0x04 6. " TXB2 ,Transmit buffer interrupt" "Masked,Not masked" bitfld.long 0x04 5. " RXF2 ,Receive frame interrupt" "Masked,Not masked" bitfld.long 0x04 4. " RXB2 ,Receive buffer interrupt" "Masked,Not masked" bitfld.long 0x04 3. " TXF1 ,Transmit frame interrupt" "Masked,Not masked" textline " " bitfld.long 0x04 2. " TXB1 ,Transmit buffer interrupt" "Masked,Not masked" bitfld.long 0x04 1. " RXF1 ,Receive frame interrupt" "Masked,Not masked" bitfld.long 0x04 0. " RXB1 ,Receive buffer interrupt" "Masked,Not masked" endif group.long 0x10++0x7 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive Descriptor Active" "Inactive,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit Descriptor Active" "Inactive,Active" group.long 0x24++0x3 line.long 0x00 "ECR,Ethernet Control Register" sif (!cpuis("MKV5*")) bitfld.long 0x00 11. " SVLANDBL ,S-VLAN double tag" "Disabled,Enabled" bitfld.long 0x00 10. " VLANUSE2ND ,VLAN use second tag" "Disabled,Enabled" bitfld.long 0x00 9. " SVLANEN ,S-VLAN enable" "Disabled,Enabled" bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Disabled,Enabled" textline " " else bitfld.long 0x00 8. " DBSWP ,Descriptor Byte Swapping Enable" "Disabled,Enabled" bitfld.long 0x00 7. " STOPEN ,STOPEN Signal Control" "Not stopped,Stopped" textline " " endif bitfld.long 0x00 6. " DBGEN ,Debug Enable" "Debug,Freeze" bitfld.long 0x00 4. " EN1588 ,EN1588 Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SLEEP ,Sleep Mode Enable" "Normal operated,Sleep mode" bitfld.long 0x00 2. " MAGICEN ,Magic Packet Detection Enable (In Sleep mode)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ETHEREN ,Ethernet Enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC Reset" "No reset,Reset" group.long 0x40++0x7 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "00,01,10,11" bitfld.long 0x00 28.--29. " OP ,Operation code" "Write(not MII),Write(MII),Read(MII),Read(not MII)" hexmask.long.byte 0x00 23.--27. 0x80 " PA ,PHY address" hexmask.long.byte 0x00 18.--22. 0x04 " RA ,Register address" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "00,01,10,11" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1,2,3,,,,,8" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,MII speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x64++0x3 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "Busy,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Cleared" group.long 0x84++0x3 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "No,Yes" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,RMII 10-Base T" "100 Mbps,10 Mbps" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII,RMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII/RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" if ((per.l(ad:0x400C0004+0x24)&0x02)==0x00) group.long 0xC4++0x3 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Yes,No" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "No,Yes" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" else group.long 0xC4++0x3 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Yes,No" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "No,Yes" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" rbitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif group.long 0xE4++0xB line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Upper 2 bytes of the 48-bit address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" sif (!cpuis("MKV5*")) group.long 0xF0++0x03 line.long 0x00 "TXIC0,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF4++0x03 line.long 0x00 "TXIC1,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0xF8++0x03 line.long 0x00 "TXIC2,Transmit Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x100++0x03 line.long 0x00 "RXIC0,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x104++0x03 line.long 0x00 "RXIC1,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" group.long 0x108++0x03 line.long 0x00 "RXIC2,Receive Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt Coalescing Enable" "Disabled,Enabled" bitfld.long 0x00 30. " ICCS ,Interrupt Coalescing Timer Clock Source Select" "MII/GMII TX clocks,ENET system clock" hexmask.long.byte 0x00 20.--27. 1. " ICFT ,Interrupt coalescing frame count threshold" hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" endif group.long 0x118++0xF line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0C "GALR,Descriptor Group Lower Address Register" group.long 0x144++0x3 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64-bytes,64-bytes,128-bytes,192-bytes,256-bytes,320-bytes,384-bytes,448-bytes,512-bytes,576-bytes,640-bytes,704-bytes,768-bytes,832-bytes,896-bytes,960-bytes,1024-bytes,1088-bytes,1152-bytes,1216-bytes,1280-bytes,1344-bytes,1408-bytes,1472-bytes,1536-bytes,1600-bytes,1664-bytes,1728-bytes,1792-bytes,1856-bytes,1920-bytes,1984-bytes,?..." sif (!cpuis("MKV5*")) group.long 0x160++0x0B line.long 0x00 "RDSR1,Receive Descriptor Ring 1 Start Register" hexmask.long 0x00 3.--31. 1. " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x04 "TDSR1,Transmit Buffer Descriptor Ring 1 Start Register" hexmask.long 0x04 3.--31. 1. " X_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 1" line.long 0x08 "MRBR1,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x16C++0x0B line.long 0x00 "RDSR2,Receive Descriptor Ring 2 Start Register" hexmask.long 0x00 3.--31. 1. " R_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 2" line.long 0x04 "TDSR2,Transmit Buffer Descriptor Ring 2 Start Register" hexmask.long 0x04 3.--31. 1. " X_DES_START ,Pointer to the beginning of the receive buffer descriptor queue 2" line.long 0x08 "MRBR2,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" endif group.long 0x180++0xB line.long 0x00 "RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold Register" bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO Section Empty Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--7. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold Register" hexmask.long.byte 0x08 0.--7. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0C "RAFL,Receive FIFO Almost Full Threshold Register" hexmask.long.byte 0x0C 0.--7. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold Register" hexmask.long.byte 0x10 0.--7. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold Register" hexmask.long.byte 0x14 0.--7. 1. " TX_ALMOST_EMPTY ,Value of the transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-Packet Gap Register" bitfld.long 0x1C 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" line.long 0x20 "FTRL,Frame Truncation Length Register" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x7 line.long 0x00 "TACC,Transmit Accelerator Function Configuration Register" bitfld.long 0x00 4. " PROCHK ,Insertion of protocol checksum enable" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Insertion of IP header checksum enable" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16 enable" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration Register" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16 enable" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Discard of frames with MAC layer errors enable" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Discard of frames with wrong protocol checksum enable" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Discard of frames with wrong IPv4 header checksum enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PADREM ,Padding removal for short IP frames enable" "Disabled,Enabled" sif (!cpuis("MKV5*")) group.long 0x1C8++0x03 line.long 0x00 "RCMR1,Receive Classification Match Register for Class 1" bitfld.long 0x00 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1CC++0x03 line.long 0x00 "RCMR2,Receive Classification Match Register for Class 2" bitfld.long 0x00 16. " MATCHEN ,Match Enable" "Disabled,Enabled" bitfld.long 0x00 12.--14. " CMP3 ,Compare 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " CMP2 ,Compare 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " CMP1 ,Compare 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " CMP0 ,Compare 0" "0,1,2,3,4,5,6,7" group.long 0x1D8++0x03 line.long 0x00 "DMA1CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Calculate no IPG" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1DC++0x03 line.long 0x00 "DMA2CFG,DMA Class Based Configuration" bitfld.long 0x00 17. " CALC_NOIPG ,Calculate no IPG" "Disabled,Enabled" bitfld.long 0x00 16. " DMA_CLASS_EN ,DMA class enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDLE_SLOPE ,Idle slope" group.long 0x1E0++0x07 line.long 0x00 "RDAR1,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive Descriptor Active" "Not set,Set" line.long 0x04 "TDAR1,Receive Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit Descriptor Active" "Not set,Set" group.long 0x1E8++0x07 line.long 0x00 "RDAR2,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive Descriptor Active" "Not set,Set" line.long 0x04 "TDAR2,Receive Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit Descriptor Active" "Not set,Set" group.long 0x1F0++0x03 line.long 0x00 "ENET_QOS,QOS Scheme" bitfld.long 0x00 5. " RX_FLUSH2 ,RX Flush Ring 2" "Disabled,Enabled" bitfld.long 0x00 4. " RX_FLUSH1 ,RX Flush Ring 1" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLUSH0 ,RX Flush Ring 0" "Disabled,Enabled" bitfld.long 0x00 0.--2. " TX_SCHEME ,TX scheme configuration" "Credit-based,Round-robin,?..." endif tree.end width 20. tree "Statistic Event Counters" rgroup.long 0x204++0x43 line.long 0x00 "RMON_T_PACKETS,RMON Tx Packet Count Register" hexmask.long.word 0x00 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x04 "RMON_T_BC_PKT,RMON Tx Broadcast Packets Register" hexmask.long.word 0x04 0.--15. 1. " TXPKTS ,Broadcast packets" line.long 0x08 "RMON_T_MC_PKT,RMON Tx Multicast Packets Register" hexmask.long.word 0x08 0.--15. 1. " TXPKTS ,Multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,RMON Tx Packets CRC/Align Error Register" hexmask.long.word 0x0C 0.--15. 1. " TXPKTS ,Packets with CRC/align error" line.long 0x10 "RMON_T_UNDERSIZE,RMON Tx Packets 64 bytes Good CRC Register" hexmask.long.word 0x10 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x14 "RMON_T_OVERSIZE,Good CRC Register" hexmask.long.word 0x14 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x18 "RMON_T_FRAG,Bad CRC Register" hexmask.long.word 0x18 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x1C "RMON_T_JAB,Bad CRC Register" hexmask.long.word 0x1C 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x20 "RMON_T_COL,RMON Tx Collision Count Register" hexmask.long.word 0x20 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x24 "RMON_T_P64,RMON Tx 64 Byte Packets Register" hexmask.long.word 0x24 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x28 "RMON_T_P65TO127,RMON Tx 65 to 127 Byte Packets Register" hexmask.long.word 0x28 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x2C "RMON_T_P128TO255,RMON Tx 128 to 255 Byte Packets Register" hexmask.long.word 0x2C 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x30 "RMON_T_P256TO511,RMON Tx 256 to 511 Byte Packets Register" hexmask.long.word 0x30 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x34 "RMON_T_P512TO1023,RMON Tx 512 to 1023 Byte Packets Register" hexmask.long.word 0x34 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x38 "RMON_T_P1024TO2047,RMON Tx 1024 to 2047 Byte Packets Register" hexmask.long.word 0x38 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x3C "RMON_T_P_GTE2048,RMON Tx Packets 2048 Bytes Register" hexmask.long.word 0x3C 0.--15. 1. " TXPKTS ,Packet Count" line.long 0x40 "RMON_T_OCTETS,RMON Tx Octets Register" rgroup.long 0x24C++0x1F line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Packet Count" line.long 0x04 "IEEE_T_1COL,Frames Transmitted with Single Collision Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Packet Count" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Packet Count" line.long 0x0C "IEEE_T_DEF,Frames Transmitted after Deferral Delay Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Packet Count" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted with Late Collision Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Packet Count" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Packet Count" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Packet Count" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Packet Count" rgroup.long 0x270++0x07 line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Packet Count" line.long 0x04 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted Error Register" rgroup.long 0x284++0x1F line.long 0x00 "RMON_R_PACKETS,RMON Rx Packet Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Packet Count" line.long 0x04 "RMON_R_BC_PKT,RMON Rx Broadcast Packets Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Packet Count" line.long 0x08 "RMON_R_MC_PKT,RMON Rx Multicast Packets Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Packet Count" line.long 0x0C "RMON_R_CRC_ALIGN,RMON Rx Packets CRC/Align Error Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Packet Count" line.long 0x10 "RMON_R_UNDERSIZE,Good CRC Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Packet Count" line.long 0x14 "RMON_R_OVERSIZE,Good CRC Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Packet Count" line.long 0x18 "RMON_R_FRAG,Bad CRC Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Packet Count" line.long 0x1C "RMON_R_JAB,Bad CRC Register" hexmask.long.word 0x1C 0.--15. 1. " COUNT ,Packet Count" rgroup.long 0x2A8++0x3B line.long 0x00 "RMON_R_P64,RMON Rx 64 Byte Packets Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Packet Count" line.long 0x04 "RMON_R_P65TO127,RMON Rx 65 to 127 Byte Packets Register" hexmask.long.word 0x04 0.--15. 1. " COUNT ,Packet Count" line.long 0x08 "RMON_R_P128TO255,RMON Rx 128 to 255 Byte Packets Register" hexmask.long.word 0x08 0.--15. 1. " COUNT ,Packet Count" line.long 0x0C "RMON_R_P256TO511,RMON Rx 256 to 511 Byte Packets Register" hexmask.long.word 0x0C 0.--15. 1. " COUNT ,Packet Count" line.long 0x10 "RMON_R_P512TO1023,RMON Rx 512 to 1023 Byte Packets Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Packet Count" line.long 0x14 "RMON_R_P1024TO2047,RMON Rx 1024 to 2047 Byte Backets Register" hexmask.long.word 0x14 0.--15. 1. " COUNT ,Packet Count" line.long 0x18 "RMON_R_P_GTE2048,RMON Rx Packets 2048 Bytes Register" hexmask.long.word 0x18 0.--15. 1. " COUNT ,Packet Count" line.long 0x1C "RMON_R_OCTETS,RMON Rx Octets Register" line.long 0x20 "IEEE_R_DROP,Count of Frames Not Counted Correctly Register" hexmask.long.word 0x20 0.--15. 1. " COUNT ,Frame count" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Register" hexmask.long.word 0x24 0.--15. 1. " COUNT ,Frame count" line.long 0x28 "IEEE_R_CRC,Frames Received with CRC Error Register" hexmask.long.word 0x28 0.--15. 1. " COUNT ,Frame count" line.long 0x2C "IEEE_R_ALIGN,Frames Received with Alignment Error Register" hexmask.long.word 0x2C 0.--15. 1. " COUNT ,Frame count" line.long 0x30 "IEEE_R_MACERR,Receive Fifo Overflow Count Register" hexmask.long.word 0x30 0.--15. 1. " COUNT ,Count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Register" hexmask.long.word 0x34 0.--15. 1. " COUNT ,Pause frame count" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count for Frames Rcvd Error Register" tree.end width 8. tree "1588 Timer" group.long 0x400++0x17 line.long 0x00 "ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "Not captured,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" sif (cpuis("MKV5*")) bitfld.long 0x00 7. " PINPER ,Event signal output assertion on period event" "Disabled,Enabled" else bitfld.long 0x00 7. " PINPER ,Enables MAC output assertion on period event" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" line.long 0x04 "ATVR,Timer Value Register" line.long 0x08 "ATOFF,Timer Offset Register" line.long 0x0C "ATPER,Timer Period Register" line.long 0x10 "ATCOR,Timer Correction Register" hexmask.long 0x10 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x14 "ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x14 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " INC ,Clock period of the timestamping clock (ts_clk) in ns" if ((per.l(ad:0x400C0004+0x4)&0x10000)==0x10000) rgroup.long 0x418++0x3 line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame Register" else hgroup.long 0x418++0x3 hide.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame Register" endif tree.end width 7. tree "Capture/Compare Block" group.long 0x604++0x23 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "Cleared,Set" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "Cleared,Set" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "Cleared,Set" eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "Cleared,Set" line.long 0x4 "TCSR0,Timer Control Status Register 0" eventfld.long 0x4 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x4 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKV5*")) bitfld.long 0x4 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture - rising edge,Input Capture - falling edge,Input Capture - both edge,Output Compare - software only,Output Compare - toggle output,Output Compare - clear output,Output Compare - set output,,Output Compare - set on compare/clear on overflow,?..." else bitfld.long 0x4 2.--5. " TMODE ,Timer mode" "Disabled,,,,Output Compare - software only,?..." endif textline " " bitfld.long 0x4 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long (0x4+0x4) "TCCR0,Timer Compare Capture Register 0" line.long 0xC "TCSR1,Timer Control Status Register 1" eventfld.long 0xC 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0xC 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKV5*")) bitfld.long 0xC 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture - rising edge,Input Capture - falling edge,Input Capture - both edge,Output Compare - software only,Output Compare - toggle output,Output Compare - clear output,Output Compare - set output,,Output Compare - set on compare/clear on overflow,?..." else bitfld.long 0xC 2.--5. " TMODE ,Timer mode" "Disabled,,,,Output Compare - software only,?..." endif textline " " bitfld.long 0xC 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long (0xC+0x4) "TCCR1,Timer Compare Capture Register 1" line.long 0x14 "TCSR2,Timer Control Status Register 2" eventfld.long 0x14 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x14 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKV5*")) bitfld.long 0x14 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture - rising edge,Input Capture - falling edge,Input Capture - both edge,Output Compare - software only,Output Compare - toggle output,Output Compare - clear output,Output Compare - set output,,Output Compare - set on compare/clear on overflow,?..." else bitfld.long 0x14 2.--5. " TMODE ,Timer mode" "Disabled,,,,Output Compare - software only,?..." endif textline " " bitfld.long 0x14 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long (0x14+0x4) "TCCR2,Timer Compare Capture Register 2" line.long 0x1C "TCSR3,Timer Control Status Register 3" eventfld.long 0x1C 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x1C 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKV5*")) bitfld.long 0x1C 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture - rising edge,Input Capture - falling edge,Input Capture - both edge,Output Compare - software only,Output Compare - toggle output,Output Compare - clear output,Output Compare - set output,,Output Compare - set on compare/clear on overflow,?..." else bitfld.long 0x1C 2.--5. " TMODE ,Timer mode" "Disabled,,,,Output Compare - software only,?..." endif textline " " bitfld.long 0x1C 0. " TDRE ,Timer DMA Request Enable" "Disabled,Enabled" line.long (0x1C+0x4) "TCCR3,Timer Compare Capture Register 3" tree.end width 0x0B tree.end tree.open "I2C (Inter-Integrated Circuit)" tree "I2C0" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" newline in newline if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" width 0x0B tree.end tree "I2C1" base ad:0x40067000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" newline in newline if ((per.b(ad:0x40067000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" width 0x0B tree.end tree.end tree.open "UART (Universal Asynchronous Receiver Transmitter)" tree "UART0" base ad:0x4006A000 width 19. tree "UART 0 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART0_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART0_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART0_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART0_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART0_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART0_MA1,UART Match Address Registers 1" line.byte 0x01 "UART0_MA2,UART Match Address Registers 2" line.byte 0x02 "UART0_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART0_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART0_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART0_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART0_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 0 FIFO Registers" if ((per.b(ad:0x4006A000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006A000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006A000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x4006A000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006A000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 0 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART0_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006A000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART0_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART0_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART0_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x4006A000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART0_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART0_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x4006A000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART0_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART0_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART0_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART0_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x4006A000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART0_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART0_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree "UART1" base ad:0x4006B000 width 19. tree "UART 1 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART1_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART1_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART1_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART1_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART1_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART1_MA1,UART Match Address Registers 1" line.byte 0x01 "UART1_MA2,UART Match Address Registers 2" line.byte 0x02 "UART1_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART1_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART1_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART1_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART1_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 1 FIFO Registers" if ((per.b(ad:0x4006B000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006B000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006B000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x4006B000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006B000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 1 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006B000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x4006B000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x4006B000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x4006B000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART1_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART1_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART1_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART1_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x4006B000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree "UART2" base ad:0x4006C000 width 19. tree "UART 2 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART2_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART2_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART2_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART2_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART2_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART2_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART2_MA1,UART Match Address Registers 1" line.byte 0x01 "UART2_MA2,UART Match Address Registers 2" line.byte 0x02 "UART2_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART2_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART2_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART2_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART2_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 2 FIFO Registers" if ((per.b(ad:0x4006C000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006C000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006C000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART2_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART2_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x4006C000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006C000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 2 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART2_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART2_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART2_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006C000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART2_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART2_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART2_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART2_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART2_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART2_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART2_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART2_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x4006C000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART2_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x4006C000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART2_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART2_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART2_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART2_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x4006C000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART2_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART2_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART2_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART2_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x4006C000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART2_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART2_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART2_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree "UART3" base ad:0x4006D000 width 19. tree "UART 3 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART3_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART3_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART3_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART3_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART3_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART3_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART3_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART3_MA1,UART Match Address Registers 1" line.byte 0x01 "UART3_MA2,UART Match Address Registers 2" line.byte 0x02 "UART3_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART3_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART3_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART3_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART3_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 3 FIFO Registers" if ((per.b(ad:0x4006D000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006D000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x4006D000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART3_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART3_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x4006D000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART3_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006D000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART3_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 3 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART3_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART3_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART3_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006D000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x4006D000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x4006D000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x4006D000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x4006D000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART3_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART3_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART3_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART3_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x4006D000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree "UART4" base ad:0x400EA000 width 19. tree "UART 4 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART4_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART4_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART4_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART4_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART4_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART4_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART4_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART4_MA1,UART Match Address Registers 1" line.byte 0x01 "UART4_MA2,UART Match Address Registers 2" line.byte 0x02 "UART4_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART4_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART4_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART4_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART4_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 4 FIFO Registers" if ((per.b(ad:0x400EA000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x400EA000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x400EA000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART4_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART4_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x400EA000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART4_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART4_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART4_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x400EA000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART4_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART4_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART4_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 4 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART4_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART4_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART4_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x400EA000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART4_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART4_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART4_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART4_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART4_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART4_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART4_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART4_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x400EA000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART4_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x400EA000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART4_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART4_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x400EA000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART4_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART4_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART4_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART4_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x400EA000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART4_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART4_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART4_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART4_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x400EA000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART4_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART4_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART4_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART4_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree "UART5" base ad:0x400EB000 width 19. tree "UART 5 Standard Features Registers" group.byte 0x00++0x03 line.byte 0x00 "UART5_BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART5_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART5_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART5_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART5_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at lenght of)" "Disabled,11/12 bit times" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART5_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART5_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART5_MA1,UART Match Address Registers 1" line.byte 0x01 "UART5_MA2,UART Match Address Registers 2" line.byte 0x02 "UART5_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART5_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "UART5_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART5_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" line.byte 0x01 "UART5_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" tree.end tree "UART 5 FIFO Registers" if ((per.b(ad:0x400EB000+0x03)&0xC)==0x0) group.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x400EB000+0x03)&0xC)==0x4) group.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" rbitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." elif ((per.b(ad:0x400EB000+0x03)&0xC)==0x8) group.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " rbitfld.byte 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." textline " " bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART5_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART5_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "Not occurred,Occurred" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "Not occurred,Occurred" textline " " eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "Not occurred,Occurred" if ((per.b(ad:0x400EB000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "UART5_TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "UART5_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART5_TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x400EB000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "UART5_RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "UART5_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART5_RCFIFO,UART FIFO Receive Count" tree.end tree "UART 5 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART5_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" textline " " bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enable" "Disabled,Enabled" line.byte 0x01 "UART5_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART5_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 3. " ADT ,ATR duration timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x400EB000+0x18)&0x1)==0x0) group.byte 0x1B++0x03 line.byte 0x00 "UART5_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART5_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART5_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART5_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x03 line.byte 0x00 "UART5_WP7816,UART 7816 Wait Parameter Register" line.byte 0x01 "UART5_WN7816,UART 7816 Wait N Register" line.byte 0x02 "UART5_WF7816,UART 7816 Wait FD Register" line.byte 0x03 "UART5_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x03 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x03 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if ((per.b(ad:0x400EB000+0x18)&0x2)==0x0) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART5_TL7816,UART 7816 Transmit Length Register" else if ((per.b(ad:0x400EB000+0x03)&0x8)==0x8) rgroup.byte 0x1F++0x00 line.byte 0x00 "UART5_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART5_TL7816,UART 7816 Transmit Length Register" endif endif if ((per.b(ad:0x400EB000+0x18)&0x1)==0x00) group.byte 0x3A++0x01 line.byte 0x00 "UART5_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART5_AP7816B_T0,UART 7816 ATR Duration Timer Register B" else rgroup.byte 0x3A++0x01 line.byte 0x00 "UART5_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART5_AP7816B_T0,UART 7816 ATR Duration Timer Register B" endif if ((per.b(ad:0x400EB000+0x18)&0x2)==0x0) group.byte 0x3C++0x01 line.byte 0x00 "UART5_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART5_WP7816B_T0,UART 7816 Wait Parameter Register B" else group.byte 0x3C++0x01 line.byte 0x00 "UART5_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART5_WP7816B_T1,UART 7816 Wait Parameter Register B" endif if ((per.b(ad:0x400EB000+0x18)&0x1)==0x00) group.byte 0x3E++0x01 line.byte 0x00 "UART5_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART5_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.byte 0x3E++0x01 line.byte 0x00 "UART5_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x00 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BGI , Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "UART5_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x01 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end width 0x0B tree.end tree.end tree.open "FlexCAN" tree "CAN0" base ad:0x40024000 width 15. group.long 0x00++0x0B line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" textline " " sif (cpuis("MKV5*")) rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" bitfld.long 0x00 22. " SLFWAK ,Self wake up" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" textline " " bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" else rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" textline " " bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" endif endif textline " " bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" textline " " bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Disabled,Enabled" bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" textline " " bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" line.long 0x08 "CAN0_TIMER,CAN0 Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" textline " " line.long 0x04 "CAN0_RX14MASK,CAN0 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN0_RX15MASK,CAN0 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RX_ERR_CNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TX_ERR_CNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_CNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_CNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" line.long 0x04 "CAN0_RX14MASK,CAN0 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN0_RX15MASK,CAN0 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif hgroup.long 0x20++0x3 hide.long 0x00 "CAN0_ESR1,CAN0 Error and Status 1 Register" in sif (!cpuis("MKV5*")) group.long 0x24++0x03 line.long 0x00 "CAN0_IMASK2,Interrupt Masks 2 register" bitfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [62] ,Buffer MB62 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [61] ,Buffer MB61 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [60] ,Buffer MB60 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [59] ,Buffer MB59 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [58] ,Buffer MB58 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [57] ,Buffer MB57 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [56] ,Buffer MB56 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [55] ,Buffer MB55 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [54] ,Buffer MB54 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [53] ,Buffer MB53 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [52] ,Buffer MB52 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [51] ,Buffer MB51 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [50] ,Buffer MB50 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [49] ,Buffer MB49 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [48] ,Buffer MB48 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [47] ,Buffer MB47 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [46] ,Buffer MB46 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [45] ,Buffer MB45 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [44] ,Buffer MB44 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [43] ,Buffer MB43 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [42] ,Buffer MB42 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [41] ,Buffer MB41 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [40] ,Buffer MB40 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [39] ,Buffer MB39 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [38] ,Buffer MB38 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [37] ,Buffer MB37 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [36] ,Buffer MB36 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [35] ,Buffer MB35 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [34] ,Buffer MB34 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [33] ,Buffer MB33 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [32] ,Buffer MB32 interrupt mask" "Masked,Not masked" endif group.long 0x28++0x03 line.long 0x00 "CAN0_IMASK1,CAN0 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Buffer MB29 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Buffer MB28 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Buffer MB26 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Buffer MB24 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Buffer MB23 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Buffer MB20 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Buffer MB17 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Buffer MB16 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Buffer MB14 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Buffer MB12 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Buffer MB11 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Buffer MB8 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Buffer MB5 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Buffer MB4 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Buffer MB2 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Buffer MB0 interrupt mask" "Masked,Not masked" sif (!cpuis("MKV5*")) group.long 0x28++0x03 line.long 0x00 "CAN0_IFLAG2,CAN0 Interrupt Flags 2 register" eventfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [62] ,Buffer MB62 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [61] ,Buffer MB61 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [60] ,Buffer MB60 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [59] ,Buffer MB59 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [58] ,Buffer MB58 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [57] ,Buffer MB57 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [56] ,Buffer MB56 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [55] ,Buffer MB55 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [54] ,Buffer MB54 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [53] ,Buffer MB53 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [52] ,Buffer MB52 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [51] ,Buffer MB51 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [50] ,Buffer MB50 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [49] ,Buffer MB49 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [48] ,Buffer MB48 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [47] ,Buffer MB47 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [46] ,Buffer MB46 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [45] ,Buffer MB45 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [44] ,Buffer MB44 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [43] ,Buffer MB43 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [42] ,Buffer MB42 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [41] ,Buffer MB41 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [40] ,Buffer MB40 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [39] ,Buffer MB39 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " [38] ,Buffer MB38 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " [37] ,Buffer MB37 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " [36] ,Buffer MB36 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [35] ,Buffer MB35 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [34] ,Buffer MB34 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [33] ,Buffer MB33 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [32] ,Buffer MB32 interrupt" "No interrupt,Interrupt" endif group.long 0x30++0x03 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt/Rx FIFO overflow" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt/Rx FIFO warning" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt/frames available in Rx FIFO" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt/clear FIFO bit" "No interrupt,Interrupt" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x34++0x3 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif else group.long 0x34++0x3 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif endif rgroup.long 0x38++0x3 line.long 0x00 "CAN0_ESR2,CAN0 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No Mailbox,Mailbox" rgroup.long 0x44++0x3 line.long 0x00 "CAN0_CRCR,CAN0 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x48++0x3 line.long 0x00 "CAN0_RXFGMASK,CAN0 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" else group.long 0x48++0x3 line.long 0x00 "CAN0_RXFGMASK,CAN0 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" endif hgroup.long 0x4C++0x3 hide.long 0x00 "CAN0_RXFIR,CAN0 Rx FIFO Information Register" in if ((per.l(ad:0x40024000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" sif (cpuis("MKV5*")) hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" else hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" endif bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" endif if (((per.l(ad:0x40024000)&0x40000000)==0x40000000)) group.long 0x880++0x3 line.long 0x00 "CAN0_RXIMR0,CAN0 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x884++0x3 line.long 0x00 "CAN0_RXIMR1,CAN0 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x888++0x3 line.long 0x00 "CAN0_RXIMR2,CAN0 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x88C++0x3 line.long 0x00 "CAN0_RXIMR3,CAN0 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x890++0x3 line.long 0x00 "CAN0_RXIMR4,CAN0 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x894++0x3 line.long 0x00 "CAN0_RXIMR5,CAN0 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x898++0x3 line.long 0x00 "CAN0_RXIMR6,CAN0 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x89C++0x3 line.long 0x00 "CAN0_RXIMR7,CAN0 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A0++0x3 line.long 0x00 "CAN0_RXIMR8,CAN0 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A4++0x3 line.long 0x00 "CAN0_RXIMR9,CAN0 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A8++0x3 line.long 0x00 "CAN0_RXIMR10,CAN0 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8AC++0x3 line.long 0x00 "CAN0_RXIMR11,CAN0 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B0++0x3 line.long 0x00 "CAN0_RXIMR12,CAN0 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B4++0x3 line.long 0x00 "CAN0_RXIMR13,CAN0 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B8++0x3 line.long 0x00 "CAN0_RXIMR14,CAN0 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8BC++0x3 line.long 0x00 "CAN0_RXIMR15,CAN0 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " else rgroup.long 0x880++0x3 line.long 0x00 "CAN0_RXIMR0,CAN0 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x884++0x3 line.long 0x00 "CAN0_RXIMR1,CAN0 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x888++0x3 line.long 0x00 "CAN0_RXIMR2,CAN0 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x88C++0x3 line.long 0x00 "CAN0_RXIMR3,CAN0 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x890++0x3 line.long 0x00 "CAN0_RXIMR4,CAN0 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x894++0x3 line.long 0x00 "CAN0_RXIMR5,CAN0 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x898++0x3 line.long 0x00 "CAN0_RXIMR6,CAN0 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x89C++0x3 line.long 0x00 "CAN0_RXIMR7,CAN0 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A0++0x3 line.long 0x00 "CAN0_RXIMR8,CAN0 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A4++0x3 line.long 0x00 "CAN0_RXIMR9,CAN0 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A8++0x3 line.long 0x00 "CAN0_RXIMR10,CAN0 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8AC++0x3 line.long 0x00 "CAN0_RXIMR11,CAN0 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B0++0x3 line.long 0x00 "CAN0_RXIMR12,CAN0 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B4++0x3 line.long 0x00 "CAN0_RXIMR13,CAN0 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B8++0x3 line.long 0x00 "CAN0_RXIMR14,CAN0 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8BC++0x3 line.long 0x00 "CAN0_RXIMR15,CAN0 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " endif sif (!cpuis("MKV5*")) if (((per.l(ad:0x40024000+0x34)&0x20000000)==0x00)) group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" rbitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " rbitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" rbitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " rbitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" rbitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" else group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" bitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" bitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" bitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" bitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " bitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" bitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" endif group.long 0xAE4++0x0B line.long 0x00 "CAN_ERRIAR,Error Injection Address Register" hexmask.long.word 0x00 0.--13. 1. " INJADDR ,Error injection address" line.long 0x04 "CAN_ERRIDPR,Error Injection Data Pattern Register" line.long 0x08 "CAN_ERRIPPR,Error Injection Parity Pattern Register" bitfld.long 0x08 24.--28. " PFLIP3 ,Parity flip pattern for byte 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " PFLIP2 ,Parity flip pattern for byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " PFLIP1 ,Parity flip pattern for byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " PFLIP0 ,Parity flip pattern for byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xAF0++0x0B line.long 0x00 "CAN_RERRAR,Error Report Address Register" bitfld.long 0x00 24. " NCE ,Non-correctable error" "Correctable,Non-correctable" bitfld.long 0x00 16.--18. " SAID ,Source of memory access error" "Move-out,Move-in,TX arbitration,RX matching,Move-out host access,?..." hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,Address where the error was detected" line.long 0x04 "CAN_RERRDR,Error Report Data Register" line.long 0x08 "CAN_RERRSYNR,Error Report Syndrome Register" bitfld.long 0x08 31. " BE3 ,Byte enabled for byte 3" "Not read,Read" bitfld.long 0x08 24.--28. " SYND3 ,Error syndrome for byte 3" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 23. " BE2 ,Byte enabled for byte 2" "Not read,Read" bitfld.long 0x08 16.--20. " SYND2 ,Error syndrome for byte 2" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" textline " " bitfld.long 0x08 15. " BE1 ,Byte enabled for byte 1" "Not read,Read" bitfld.long 0x08 8.--12. " SYND1 ,Error syndrome for byte 1" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 7. " BE0 ,Byte enabled for byte 0" "Not read,Read" bitfld.long 0x08 0.--4. " SYND0 ,Error syndrome for byte 0" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" group.long 0xAFC++0x03 line.long 0x00 "CAN_ERRSR,Error Status Register" eventfld.long 0x00 19. " HANCEIF ,Host access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 18. " FANCEIF ,FlexCAN access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 16. " CEIF ,Correctable error interrupt flag" "No error,Error" eventfld.long 0x00 3. " HANCEIOF ,Host access with non-correctable error interrupt overrun flag" "No overrun,Overrun" textline " " eventfld.long 0x00 2. " FANCEIOF ,FlexCAN access with non-correctable error interrupt overrun flag" "No overrun,Overrun" eventfld.long 0x00 0. " CEIOF ,Correctable error interrupt overrun flag" "No overrun,Overrun" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") if (((per.l(ad:0x40024000)&0x40000000)==0x40000000)) group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" rbitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compenstaion value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x40024000)&0x40000000)==0x40000000)) group.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else rgroup.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif group.long 0xC08++0x03 line.long 0x00 "CAN_FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCTC ,Extended transmitted CTC value" endif endif width 0x0B tree.end tree "CAN1" base ad:0x40025000 width 15. group.long 0x00++0x0B line.long 0x00 "CAN1_MCR,CAN1 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" textline " " sif (cpuis("MKV5*")) rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" bitfld.long 0x00 22. " SLFWAK ,Self wake up" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" textline " " bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" else rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" textline " " bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" endif endif textline " " bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN1_CTRL1,CAN1 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" textline " " bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Disabled,Enabled" bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" textline " " bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" line.long 0x08 "CAN1_TIMER,CAN1 Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40025000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN1_RXMGMASK,CAN1 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" textline " " line.long 0x04 "CAN1_RX14MASK,CAN1 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN1_RX15MASK,CAN1 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN1_ECR,CAN1 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RX_ERR_CNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TX_ERR_CNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_CNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_CNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN1_RXMGMASK,CAN1 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" line.long 0x04 "CAN1_RX14MASK,CAN1 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN1_RX15MASK,CAN1 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN1_ECR,CAN1 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif hgroup.long 0x20++0x3 hide.long 0x00 "CAN1_ESR1,CAN1 Error and Status 1 Register" in sif (!cpuis("MKV5*")) group.long 0x24++0x03 line.long 0x00 "CAN1_IMASK2,Interrupt Masks 2 register" bitfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [62] ,Buffer MB62 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [61] ,Buffer MB61 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [60] ,Buffer MB60 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [59] ,Buffer MB59 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [58] ,Buffer MB58 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [57] ,Buffer MB57 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [56] ,Buffer MB56 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [55] ,Buffer MB55 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [54] ,Buffer MB54 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [53] ,Buffer MB53 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [52] ,Buffer MB52 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [51] ,Buffer MB51 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [50] ,Buffer MB50 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [49] ,Buffer MB49 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [48] ,Buffer MB48 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [47] ,Buffer MB47 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [46] ,Buffer MB46 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [45] ,Buffer MB45 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [44] ,Buffer MB44 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [43] ,Buffer MB43 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [42] ,Buffer MB42 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [41] ,Buffer MB41 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [40] ,Buffer MB40 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [39] ,Buffer MB39 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [38] ,Buffer MB38 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [37] ,Buffer MB37 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [36] ,Buffer MB36 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [35] ,Buffer MB35 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [34] ,Buffer MB34 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [33] ,Buffer MB33 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [32] ,Buffer MB32 interrupt mask" "Masked,Not masked" endif group.long 0x28++0x03 line.long 0x00 "CAN1_IMASK1,CAN1 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Buffer MB29 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Buffer MB28 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Buffer MB26 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Buffer MB24 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Buffer MB23 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Buffer MB20 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Buffer MB17 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Buffer MB16 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Buffer MB14 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Buffer MB12 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Buffer MB11 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Buffer MB8 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Buffer MB5 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Buffer MB4 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Buffer MB2 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Buffer MB0 interrupt mask" "Masked,Not masked" sif (!cpuis("MKV5*")) group.long 0x28++0x03 line.long 0x00 "CAN1_IFLAG2,CAN1 Interrupt Flags 2 register" eventfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [62] ,Buffer MB62 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [61] ,Buffer MB61 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [60] ,Buffer MB60 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [59] ,Buffer MB59 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [58] ,Buffer MB58 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [57] ,Buffer MB57 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [56] ,Buffer MB56 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [55] ,Buffer MB55 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [54] ,Buffer MB54 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [53] ,Buffer MB53 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [52] ,Buffer MB52 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [51] ,Buffer MB51 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [50] ,Buffer MB50 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [49] ,Buffer MB49 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [48] ,Buffer MB48 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [47] ,Buffer MB47 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [46] ,Buffer MB46 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [45] ,Buffer MB45 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [44] ,Buffer MB44 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [43] ,Buffer MB43 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [42] ,Buffer MB42 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [41] ,Buffer MB41 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [40] ,Buffer MB40 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [39] ,Buffer MB39 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " [38] ,Buffer MB38 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " [37] ,Buffer MB37 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " [36] ,Buffer MB36 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [35] ,Buffer MB35 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [34] ,Buffer MB34 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [33] ,Buffer MB33 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [32] ,Buffer MB32 interrupt" "No interrupt,Interrupt" endif group.long 0x30++0x03 line.long 0x00 "CAN1_IFLAG1,CAN1 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt/Rx FIFO overflow" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt/Rx FIFO warning" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt/frames available in Rx FIFO" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt/clear FIFO bit" "No interrupt,Interrupt" if ((per.l(ad:0x40025000)&0x40000000)==0x00) rgroup.long 0x34++0x3 line.long 0x00 "CAN1_CTRL2,CAN1 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif else group.long 0x34++0x3 line.long 0x00 "CAN1_CTRL2,CAN1 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif endif rgroup.long 0x38++0x3 line.long 0x00 "CAN1_ESR2,CAN1 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No Mailbox,Mailbox" rgroup.long 0x44++0x3 line.long 0x00 "CAN1_CRCR,CAN1 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x40025000)&0x40000000)==0x00) rgroup.long 0x48++0x3 line.long 0x00 "CAN1_RXFGMASK,CAN1 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" else group.long 0x48++0x3 line.long 0x00 "CAN1_RXFGMASK,CAN1 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" endif hgroup.long 0x4C++0x3 hide.long 0x00 "CAN1_RXFIR,CAN1 Rx FIFO Information Register" in if ((per.l(ad:0x40025000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN1_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" sif (cpuis("MKV5*")) hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" else hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" endif bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN1_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" endif if (((per.l(ad:0x40025000)&0x40000000)==0x40000000)) group.long 0x880++0x3 line.long 0x00 "CAN1_RXIMR0,CAN1 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x884++0x3 line.long 0x00 "CAN1_RXIMR1,CAN1 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x888++0x3 line.long 0x00 "CAN1_RXIMR2,CAN1 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x88C++0x3 line.long 0x00 "CAN1_RXIMR3,CAN1 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x890++0x3 line.long 0x00 "CAN1_RXIMR4,CAN1 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x894++0x3 line.long 0x00 "CAN1_RXIMR5,CAN1 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x898++0x3 line.long 0x00 "CAN1_RXIMR6,CAN1 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x89C++0x3 line.long 0x00 "CAN1_RXIMR7,CAN1 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A0++0x3 line.long 0x00 "CAN1_RXIMR8,CAN1 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A4++0x3 line.long 0x00 "CAN1_RXIMR9,CAN1 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A8++0x3 line.long 0x00 "CAN1_RXIMR10,CAN1 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8AC++0x3 line.long 0x00 "CAN1_RXIMR11,CAN1 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B0++0x3 line.long 0x00 "CAN1_RXIMR12,CAN1 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B4++0x3 line.long 0x00 "CAN1_RXIMR13,CAN1 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B8++0x3 line.long 0x00 "CAN1_RXIMR14,CAN1 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8BC++0x3 line.long 0x00 "CAN1_RXIMR15,CAN1 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " else rgroup.long 0x880++0x3 line.long 0x00 "CAN1_RXIMR0,CAN1 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x884++0x3 line.long 0x00 "CAN1_RXIMR1,CAN1 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x888++0x3 line.long 0x00 "CAN1_RXIMR2,CAN1 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x88C++0x3 line.long 0x00 "CAN1_RXIMR3,CAN1 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x890++0x3 line.long 0x00 "CAN1_RXIMR4,CAN1 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x894++0x3 line.long 0x00 "CAN1_RXIMR5,CAN1 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x898++0x3 line.long 0x00 "CAN1_RXIMR6,CAN1 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x89C++0x3 line.long 0x00 "CAN1_RXIMR7,CAN1 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A0++0x3 line.long 0x00 "CAN1_RXIMR8,CAN1 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A4++0x3 line.long 0x00 "CAN1_RXIMR9,CAN1 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A8++0x3 line.long 0x00 "CAN1_RXIMR10,CAN1 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8AC++0x3 line.long 0x00 "CAN1_RXIMR11,CAN1 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B0++0x3 line.long 0x00 "CAN1_RXIMR12,CAN1 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B4++0x3 line.long 0x00 "CAN1_RXIMR13,CAN1 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B8++0x3 line.long 0x00 "CAN1_RXIMR14,CAN1 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8BC++0x3 line.long 0x00 "CAN1_RXIMR15,CAN1 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " endif sif (!cpuis("MKV5*")) if (((per.l(ad:0x40025000+0x34)&0x20000000)==0x00)) group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" rbitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " rbitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" rbitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " rbitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" rbitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" else group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" bitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" bitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" bitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" bitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " bitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" bitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" endif group.long 0xAE4++0x0B line.long 0x00 "CAN_ERRIAR,Error Injection Address Register" hexmask.long.word 0x00 0.--13. 1. " INJADDR ,Error injection address" line.long 0x04 "CAN_ERRIDPR,Error Injection Data Pattern Register" line.long 0x08 "CAN_ERRIPPR,Error Injection Parity Pattern Register" bitfld.long 0x08 24.--28. " PFLIP3 ,Parity flip pattern for byte 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " PFLIP2 ,Parity flip pattern for byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " PFLIP1 ,Parity flip pattern for byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " PFLIP0 ,Parity flip pattern for byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xAF0++0x0B line.long 0x00 "CAN_RERRAR,Error Report Address Register" bitfld.long 0x00 24. " NCE ,Non-correctable error" "Correctable,Non-correctable" bitfld.long 0x00 16.--18. " SAID ,Source of memory access error" "Move-out,Move-in,TX arbitration,RX matching,Move-out host access,?..." hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,Address where the error was detected" line.long 0x04 "CAN_RERRDR,Error Report Data Register" line.long 0x08 "CAN_RERRSYNR,Error Report Syndrome Register" bitfld.long 0x08 31. " BE3 ,Byte enabled for byte 3" "Not read,Read" bitfld.long 0x08 24.--28. " SYND3 ,Error syndrome for byte 3" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 23. " BE2 ,Byte enabled for byte 2" "Not read,Read" bitfld.long 0x08 16.--20. " SYND2 ,Error syndrome for byte 2" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" textline " " bitfld.long 0x08 15. " BE1 ,Byte enabled for byte 1" "Not read,Read" bitfld.long 0x08 8.--12. " SYND1 ,Error syndrome for byte 1" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 7. " BE0 ,Byte enabled for byte 0" "Not read,Read" bitfld.long 0x08 0.--4. " SYND0 ,Error syndrome for byte 0" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" group.long 0xAFC++0x03 line.long 0x00 "CAN_ERRSR,Error Status Register" eventfld.long 0x00 19. " HANCEIF ,Host access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 18. " FANCEIF ,FlexCAN access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 16. " CEIF ,Correctable error interrupt flag" "No error,Error" eventfld.long 0x00 3. " HANCEIOF ,Host access with non-correctable error interrupt overrun flag" "No overrun,Overrun" textline " " eventfld.long 0x00 2. " FANCEIOF ,FlexCAN access with non-correctable error interrupt overrun flag" "No overrun,Overrun" eventfld.long 0x00 0. " CEIOF ,Correctable error interrupt overrun flag" "No overrun,Overrun" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") if (((per.l(ad:0x40025000)&0x40000000)==0x40000000)) group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" rbitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compenstaion value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x40025000)&0x40000000)==0x40000000)) group.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else rgroup.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif group.long 0xC08++0x03 line.long 0x00 "CAN_FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCTC ,Extended transmitted CTC value" endif endif width 0x0B tree.end sif cpuis("MKV56*")||cpuis("MKV58*") tree "CAN2" base ad:0x400A4000 width 15. group.long 0x00++0x0B line.long 0x00 "CAN2_MCR,CAN2 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" textline " " sif (cpuis("MKV5*")) rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" bitfld.long 0x00 22. " SLFWAK ,Self wake up" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" textline " " bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered Rx,Filtered Rx" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" else rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "No,Yes" bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not Freeze,Freeze" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" textline " " bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx masking and queue enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") bitfld.long 0x00 11. " FDEN ,CAN FD operation enable" "Disabled,Enabled" endif endif textline " " bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN2_CTRL1,CAN2 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" textline " " bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Disabled,Enabled" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Disabled,Enabled" bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 10. " RWRNMSK ,Rx warning interrupt mask" "Disabled,Enabled" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" textline " " bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" line.long 0x08 "CAN2_TIMER,CAN2 Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x400A4000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN2_RXMGMASK,CAN2 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" textline " " line.long 0x04 "CAN2_RX14MASK,CAN2 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN2_RX15MASK,CAN2 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN2_ECR,CAN2 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RX_ERR_CNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TX_ERR_CNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RX_ERR_CNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TX_ERR_CNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN2_RXMGMASK,CAN2 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,Rx mailboxes global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx mailboxes global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx mailboxes global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx mailboxes global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx mailboxes global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx mailboxes global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx mailboxes global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx mailboxes global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx mailboxes global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx mailboxes global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx mailboxes global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx mailboxes global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx mailboxes global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx mailboxes global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx mailboxes global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx mailboxes global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx mailboxes global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx mailboxes global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx mailboxes global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx mailboxes global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx mailboxes global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx mailboxes global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx mailboxes global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx mailboxes global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx mailboxes global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx mailboxes global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx mailboxes global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx mailboxes global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx mailboxes global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx mailboxes global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx mailboxes global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx mailboxes global mask bit 0" "Masked,Not masked" line.long 0x04 "CAN2_RX14MASK,CAN2 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,Rx buffer 14 mask bit 31" "Masked,Not masked" bitfld.long 0x04 30. " [30] ,Rx buffer 14 mask bit 30" "Masked,Not masked" bitfld.long 0x04 29. " [29] ,Rx buffer 14 mask bit 29" "Masked,Not masked" bitfld.long 0x04 28. " [28] ,Rx buffer 14 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " [27] ,Rx buffer 14 mask bit 27" "Masked,Not masked" bitfld.long 0x04 26. " [26] ,Rx buffer 14 mask bit 26" "Masked,Not masked" bitfld.long 0x04 25. " [25] ,Rx buffer 14 mask bit 25" "Masked,Not masked" bitfld.long 0x04 24. " [24] ,Rx buffer 14 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " [23] ,Rx buffer 14 mask bit 23" "Masked,Not masked" bitfld.long 0x04 22. " [22] ,Rx buffer 14 mask bit 22" "Masked,Not masked" bitfld.long 0x04 21. " [21] ,Rx buffer 14 mask bit 21" "Masked,Not masked" bitfld.long 0x04 20. " [20] ,Rx buffer 14 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " [19] ,Rx buffer 14 mask bit 19" "Masked,Not masked" bitfld.long 0x04 18. " [18] ,Rx buffer 14 mask bit 18" "Masked,Not masked" bitfld.long 0x04 17. " [17] ,Rx buffer 14 mask bit 17" "Masked,Not masked" bitfld.long 0x04 16. " [16] ,Rx buffer 14 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " [15] ,Rx buffer 14 mask bit 15" "Masked,Not masked" bitfld.long 0x04 14. " [14] ,Rx buffer 14 mask bit 14" "Masked,Not masked" bitfld.long 0x04 13. " [13] ,Rx buffer 14 mask bit 13" "Masked,Not masked" bitfld.long 0x04 12. " [12] ,Rx buffer 14 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " [11] ,Rx buffer 14 mask bit 11" "Masked,Not masked" bitfld.long 0x04 10. " [10] ,Rx buffer 14 mask bit 10" "Masked,Not masked" bitfld.long 0x04 9. " [9] ,Rx buffer 14 mask bit 9" "Masked,Not masked" bitfld.long 0x04 8. " [8] ,Rx buffer 14 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " [7] ,Rx buffer 14 mask bit 7" "Masked,Not masked" bitfld.long 0x04 6. " [6] ,Rx buffer 14 mask bit 6" "Masked,Not masked" bitfld.long 0x04 5. " [5] ,Rx buffer 14 mask bit 5" "Masked,Not masked" bitfld.long 0x04 4. " [4] ,Rx buffer 14 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " [3] ,Rx buffer 14 mask bit 3" "Masked,Not masked" bitfld.long 0x04 2. " [2] ,Rx buffer 14 mask bit 2" "Masked,Not masked" bitfld.long 0x04 1. " [1] ,Rx buffer 14 mask bit 1" "Masked,Not masked" bitfld.long 0x04 0. " [0] ,Rx buffer 14 mask bit 0" "Masked,Not masked" line.long 0x08 "CAN2_RX15MASK,CAN2 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,Rx buffer 15 mask bit 31" "Masked,Not masked" bitfld.long 0x08 30. " [30] ,Rx buffer 15 mask bit 30" "Masked,Not masked" bitfld.long 0x08 29. " [29] ,Rx buffer 15 mask bit 29" "Masked,Not masked" bitfld.long 0x08 28. " [28] ,Rx buffer 15 mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " [27] ,Rx buffer 15 mask bit 27" "Masked,Not masked" bitfld.long 0x08 26. " [26] ,Rx buffer 15 mask bit 26" "Masked,Not masked" bitfld.long 0x08 25. " [25] ,Rx buffer 15 mask bit 25" "Masked,Not masked" bitfld.long 0x08 24. " [24] ,Rx buffer 15 mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " [23] ,Rx buffer 15 mask bit 23" "Masked,Not masked" bitfld.long 0x08 22. " [22] ,Rx buffer 15 mask bit 22" "Masked,Not masked" bitfld.long 0x08 21. " [21] ,Rx buffer 15 mask bit 21" "Masked,Not masked" bitfld.long 0x08 20. " [20] ,Rx buffer 15 mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " [19] ,Rx buffer 15 mask bit 19" "Masked,Not masked" bitfld.long 0x08 18. " [18] ,Rx buffer 15 mask bit 18" "Masked,Not masked" bitfld.long 0x08 17. " [17] ,Rx buffer 15 mask bit 17" "Masked,Not masked" bitfld.long 0x08 16. " [16] ,Rx buffer 15 mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " [15] ,Rx buffer 15 mask bit 15" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Rx buffer 15 mask bit 14" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Rx buffer 15 mask bit 13" "Masked,Not masked" bitfld.long 0x08 12. " [12] ,Rx buffer 15 mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " [11] ,Rx buffer 15 mask bit 11" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Rx buffer 15 mask bit 10" "Masked,Not masked" bitfld.long 0x08 9. " [9] ,Rx buffer 15 mask bit 9" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Rx buffer 15 mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " [7] ,Rx buffer 15 mask bit 7" "Masked,Not masked" bitfld.long 0x08 6. " [6] ,Rx buffer 15 mask bit 6" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Rx buffer 15 mask bit 5" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Rx buffer 15 mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Rx buffer 15 mask bit 3" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Rx buffer 15 mask bit 2" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Rx buffer 15 mask bit 1" "Masked,Not masked" bitfld.long 0x08 0. " [0] ,Rx buffer 15 mask bit 0" "Masked,Not masked" line.long 0x0C "CAN2_ECR,CAN2 Error Counter Register" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4")&&!cpuis("MKV5*") hexmask.long.byte 0x0C 24.--31. 1. " RXERRCNT_FAST ,Receive error counter for fast bits" hexmask.long.byte 0x0C 16.--23. 1. " TXERRCNT_FAST ,Transmit error counter for fast bits" textline " " endif hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif hgroup.long 0x20++0x3 hide.long 0x00 "CAN2_ESR1,CAN2 Error and Status 1 Register" in sif (!cpuis("MKV5*")) group.long 0x24++0x03 line.long 0x00 "CAN2_IMASK2,Interrupt Masks 2 register" bitfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [62] ,Buffer MB62 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [61] ,Buffer MB61 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [60] ,Buffer MB60 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [59] ,Buffer MB59 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [58] ,Buffer MB58 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [57] ,Buffer MB57 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [56] ,Buffer MB56 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [55] ,Buffer MB55 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [54] ,Buffer MB54 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [53] ,Buffer MB53 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [52] ,Buffer MB52 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [51] ,Buffer MB51 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [50] ,Buffer MB50 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [49] ,Buffer MB49 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [48] ,Buffer MB48 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [47] ,Buffer MB47 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [46] ,Buffer MB46 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [45] ,Buffer MB45 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [44] ,Buffer MB44 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [43] ,Buffer MB43 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [42] ,Buffer MB42 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [41] ,Buffer MB41 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [40] ,Buffer MB40 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [39] ,Buffer MB39 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [38] ,Buffer MB38 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [37] ,Buffer MB37 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [36] ,Buffer MB36 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [35] ,Buffer MB35 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [34] ,Buffer MB34 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [33] ,Buffer MB33 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [32] ,Buffer MB32 interrupt mask" "Masked,Not masked" endif group.long 0x28++0x03 line.long 0x00 "CAN2_IMASK1,CAN2 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Buffer MB29 interrupt mask" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Buffer MB28 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Buffer MB26 interrupt mask" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Buffer MB24 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Buffer MB23 interrupt mask" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Buffer MB20 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Buffer MB17 interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Buffer MB16 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Buffer MB14 interrupt mask" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Buffer MB12 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Buffer MB11 interrupt mask" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Buffer MB8 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Buffer MB5 interrupt mask" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Buffer MB4 interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Buffer MB2 interrupt mask" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Buffer MB0 interrupt mask" "Masked,Not masked" sif (!cpuis("MKV5*")) group.long 0x28++0x03 line.long 0x00 "CAN2_IFLAG2,CAN2 Interrupt Flags 2 register" eventfld.long 0x00 31. " BUF[63] ,Buffer MB63 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [62] ,Buffer MB62 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [61] ,Buffer MB61 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [60] ,Buffer MB60 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [59] ,Buffer MB59 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [58] ,Buffer MB58 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [57] ,Buffer MB57 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [56] ,Buffer MB56 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [55] ,Buffer MB55 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [54] ,Buffer MB54 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [53] ,Buffer MB53 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [52] ,Buffer MB52 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [51] ,Buffer MB51 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [50] ,Buffer MB50 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [49] ,Buffer MB49 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [48] ,Buffer MB48 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [47] ,Buffer MB47 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [46] ,Buffer MB46 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [45] ,Buffer MB45 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [44] ,Buffer MB44 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [43] ,Buffer MB43 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [42] ,Buffer MB42 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [41] ,Buffer MB41 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [40] ,Buffer MB40 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [39] ,Buffer MB39 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " [38] ,Buffer MB38 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " [37] ,Buffer MB37 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " [36] ,Buffer MB36 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [35] ,Buffer MB35 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [34] ,Buffer MB34 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [33] ,Buffer MB33 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [32] ,Buffer MB32 interrupt" "No interrupt,Interrupt" endif group.long 0x30++0x03 line.long 0x00 "CAN2_IFLAG1,CAN2 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF[31] ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Buffer MB29 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Buffer MB28 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " [27] ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Buffer MB26 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Buffer MB24 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " [23] ,Buffer MB23 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Buffer MB20 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " [19] ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Buffer MB17 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Buffer MB16 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " [15] ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Buffer MB14 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Buffer MB12 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " [11] ,Buffer MB11 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Buffer MB8 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " [7] ,Buffer MB7 interrupt/Rx FIFO overflow" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Buffer MB6 interrupt/Rx FIFO warning" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Buffer MB5 interrupt/frames available in Rx FIFO" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Buffer MB4 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [3] ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Buffer MB2 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Buffer MB0 interrupt/clear FIFO bit" "No interrupt,Interrupt" if ((per.l(ad:0x400A4000)&0x40000000)==0x00) rgroup.long 0x34++0x3 line.long 0x00 "CAN2_CTRL2,CAN2 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif else group.long 0x34++0x3 line.long 0x00 "CAN2_CTRL2,CAN2 Control 2 Register" sif (cpuis("MKV5*")) bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" textline " " bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" else bitfld.long 0x00 31. " ERRMSK_FAST ,Error interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " ECRWRE ,Error correction configuration register write enable" "Disabled,Enabled" bitfld.long 0x00 28. " WRMFRZ ,Write-access to memory in freeze mode" "Restricted,Unrestricted" textline " " bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" textline " " bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for Rx mailboxes" "Disabled,Enabled" bitfld.long 0x00 15. " TIMER_SRC ,Timer source" "CAN bit clock,External time tick" endif endif rgroup.long 0x38++0x3 line.long 0x00 "CAN2_ESR2,CAN2 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No Mailbox,Mailbox" rgroup.long 0x44++0x3 line.long 0x00 "CAN2_CRCR,CAN2 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x400A4000)&0x40000000)==0x00) rgroup.long 0x48++0x3 line.long 0x00 "CAN2_RXFGMASK,CAN2 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" else group.long 0x48++0x3 line.long 0x00 "CAN2_RXFGMASK,CAN2 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,Rx FIFO global mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Rx FIFO global mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Rx FIFO global mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Rx FIFO global mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Rx FIFO global mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Rx FIFO global mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Rx FIFO global mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Rx FIFO global mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Rx FIFO global mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Rx FIFO global mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Rx FIFO global mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Rx FIFO global mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Rx FIFO global mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Rx FIFO global mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Rx FIFO global mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Rx FIFO global mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Rx FIFO global mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Rx FIFO global mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Rx FIFO global mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Rx FIFO global mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Rx FIFO global mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Rx FIFO global mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Rx FIFO global mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Rx FIFO global mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Rx FIFO global mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Rx FIFO global mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Rx FIFO global mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Rx FIFO global mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Rx FIFO global mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Rx FIFO global mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Rx FIFO global mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Rx FIFO global mask bit 0" "Masked,Not masked" endif hgroup.long 0x4C++0x3 hide.long 0x00 "CAN2_RXFIR,CAN2 Rx FIFO Information Register" in if ((per.l(ad:0x400A4000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN2_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" sif (cpuis("MKV5*")) hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" else hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" endif bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN2_CBT,CAN Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 20.--29. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta,33 x Time-Quanta,34 x Time-Quanta,35 x Time-Quanta,36 x Time-Quanta,37 x Time-Quanta,38 x Time-Quanta,39 x Time-Quanta,40 x Time-Quanta,41 x Time-Quanta,42 x Time-Quanta,43 x Time-Quanta,44 x Time-Quanta,45 x Time-Quanta,46 x Time-Quanta,47 x Time-Quanta,48 x Time-Quanta,49 x Time-Quanta,50 x Time-Quanta,51 x Time-Quanta,52 x Time-Quanta,53 x Time-Quanta,54 x Time-Quanta,55 x Time-Quanta,56 x Time-Quanta,57 x Time-Quanta,58 x Time-Quanta,59 x Time-Quanta,60 x Time-Quanta,61 x Time-Quanta,62 x Time-Quanta,63 x Time-Quanta,64 x Time-Quanta" textline " " bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta,9 x Time-Quanta,10 x Time-Quanta,11 x Time-Quanta,12 x Time-Quanta,13 x Time-Quanta,14 x Time-Quanta,15 x Time-Quanta,16 x Time-Quanta,17 x Time-Quanta,18 x Time-Quanta,19 x Time-Quanta,20 x Time-Quanta,21 x Time-Quanta,22 x Time-Quanta,23 x Time-Quanta,24 x Time-Quanta,25 x Time-Quanta,26 x Time-Quanta,27 x Time-Quanta,28 x Time-Quanta,29 x Time-Quanta,30 x Time-Quanta,31 x Time-Quanta,32 x Time-Quanta" endif if (((per.l(ad:0x400A4000)&0x40000000)==0x40000000)) group.long 0x880++0x3 line.long 0x00 "CAN2_RXIMR0,CAN2 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x884++0x3 line.long 0x00 "CAN2_RXIMR1,CAN2 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x888++0x3 line.long 0x00 "CAN2_RXIMR2,CAN2 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x88C++0x3 line.long 0x00 "CAN2_RXIMR3,CAN2 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x890++0x3 line.long 0x00 "CAN2_RXIMR4,CAN2 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x894++0x3 line.long 0x00 "CAN2_RXIMR5,CAN2 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x898++0x3 line.long 0x00 "CAN2_RXIMR6,CAN2 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x89C++0x3 line.long 0x00 "CAN2_RXIMR7,CAN2 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A0++0x3 line.long 0x00 "CAN2_RXIMR8,CAN2 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A4++0x3 line.long 0x00 "CAN2_RXIMR9,CAN2 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8A8++0x3 line.long 0x00 "CAN2_RXIMR10,CAN2 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8AC++0x3 line.long 0x00 "CAN2_RXIMR11,CAN2 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B0++0x3 line.long 0x00 "CAN2_RXIMR12,CAN2 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B4++0x3 line.long 0x00 "CAN2_RXIMR13,CAN2 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8B8++0x3 line.long 0x00 "CAN2_RXIMR14,CAN2 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " group.long 0x8BC++0x3 line.long 0x00 "CAN2_RXIMR15,CAN2 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " else rgroup.long 0x880++0x3 line.long 0x00 "CAN2_RXIMR0,CAN2 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x884++0x3 line.long 0x00 "CAN2_RXIMR1,CAN2 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x888++0x3 line.long 0x00 "CAN2_RXIMR2,CAN2 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x88C++0x3 line.long 0x00 "CAN2_RXIMR3,CAN2 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x890++0x3 line.long 0x00 "CAN2_RXIMR4,CAN2 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x894++0x3 line.long 0x00 "CAN2_RXIMR5,CAN2 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x898++0x3 line.long 0x00 "CAN2_RXIMR6,CAN2 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x89C++0x3 line.long 0x00 "CAN2_RXIMR7,CAN2 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A0++0x3 line.long 0x00 "CAN2_RXIMR8,CAN2 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A4++0x3 line.long 0x00 "CAN2_RXIMR9,CAN2 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8A8++0x3 line.long 0x00 "CAN2_RXIMR10,CAN2 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8AC++0x3 line.long 0x00 "CAN2_RXIMR11,CAN2 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B0++0x3 line.long 0x00 "CAN2_RXIMR12,CAN2 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B4++0x3 line.long 0x00 "CAN2_RXIMR13,CAN2 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8B8++0x3 line.long 0x00 "CAN2_RXIMR14,CAN2 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " rgroup.long 0x8BC++0x3 line.long 0x00 "CAN2_RXIMR15,CAN2 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Masked,Not masked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Masked,Not masked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Masked,Not masked" bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Masked,Not masked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Masked,Not masked" bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Masked,Not masked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Masked,Not masked" bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Masked,Not masked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Masked,Not masked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Masked,Not masked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Masked,Not masked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Masked,Not masked" bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Masked,Not masked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Masked,Not masked" bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Masked,Not masked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Masked,Not masked" bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Masked,Not masked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Masked,Not masked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Masked,Not masked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Masked,Not masked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Masked,Not masked" bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Masked,Not masked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Masked,Not masked" bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Masked,Not masked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Masked,Not masked" textline " " endif sif (!cpuis("MKV5*")) if (((per.l(ad:0x400A4000+0x34)&0x20000000)==0x00)) group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" rbitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" rbitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " rbitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" rbitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" rbitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " rbitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" rbitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" else group.long 0xAE0++0x03 line.long 0x00 "CAN_MECR,Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ,Error configuration register write disable" "No,Yes" bitfld.long 0x00 19. " HANCEI_MSK ,Host access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " FANCEI_MSK ,FlexCAN access with non-correctable errors interrupt mask" "Masked,Not masked" bitfld.long 0x00 16. " CEI_MSK ,Correctable errors interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " HAERRIE ,Host access error injection enable" "Disabled,Enabled" bitfld.long 0x00 14. " FAERRIE ,FlexCAN access error injection enable" "Disabled,Enabled" bitfld.long 0x00 13. " EXTERRIE ,Extended error injection enable" "32-bit,64-bit" bitfld.long 0x00 9. " RERRDIS ,Error report disable" "No,Yes" textline " " bitfld.long 0x00 8. " ECCDIS ,Error correction disable" "No,Yes" bitfld.long 0x00 7. " NCEFAFRZ ,Non-correctable errors in FlexCAN access put device in freeze mode" "Normal operation,Freeze mode" endif group.long 0xAE4++0x0B line.long 0x00 "CAN_ERRIAR,Error Injection Address Register" hexmask.long.word 0x00 0.--13. 1. " INJADDR ,Error injection address" line.long 0x04 "CAN_ERRIDPR,Error Injection Data Pattern Register" line.long 0x08 "CAN_ERRIPPR,Error Injection Parity Pattern Register" bitfld.long 0x08 24.--28. " PFLIP3 ,Parity flip pattern for byte 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " PFLIP2 ,Parity flip pattern for byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " PFLIP1 ,Parity flip pattern for byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " PFLIP0 ,Parity flip pattern for byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xAF0++0x0B line.long 0x00 "CAN_RERRAR,Error Report Address Register" bitfld.long 0x00 24. " NCE ,Non-correctable error" "Correctable,Non-correctable" bitfld.long 0x00 16.--18. " SAID ,Source of memory access error" "Move-out,Move-in,TX arbitration,RX matching,Move-out host access,?..." hexmask.long.word 0x00 0.--13. 1. " ERRADDR ,Address where the error was detected" line.long 0x04 "CAN_RERRDR,Error Report Data Register" line.long 0x08 "CAN_RERRSYNR,Error Report Syndrome Register" bitfld.long 0x08 31. " BE3 ,Byte enabled for byte 3" "Not read,Read" bitfld.long 0x08 24.--28. " SYND3 ,Error syndrome for byte 3" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 23. " BE2 ,Byte enabled for byte 2" "Not read,Read" bitfld.long 0x08 16.--20. " SYND2 ,Error syndrome for byte 2" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" textline " " bitfld.long 0x08 15. " BE1 ,Byte enabled for byte 1" "Not read,Read" bitfld.long 0x08 8.--12. " SYND1 ,Error syndrome for byte 1" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" bitfld.long 0x08 7. " BE0 ,Byte enabled for byte 0" "Not read,Read" bitfld.long 0x08 0.--4. " SYND0 ,Error syndrome for byte 0" "No error,Code/0,Code/1,Non-correctable,Code/2,Non-correctable,-/All-zeros non-correctable,Data/5,Code/3,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Non-correctable,Code/4,Non-correctable,Non-correctable,Data/2,Non-correctable,Data/6,Data/1,Non-correctable,Non-correctable,Non-correctable,Data/4,Non-correctable,Data/0,Non-correctable,Non-correctable,-/All-ones non-correctable" group.long 0xAFC++0x03 line.long 0x00 "CAN_ERRSR,Error Status Register" eventfld.long 0x00 19. " HANCEIF ,Host access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 18. " FANCEIF ,FlexCAN access with non-correctable error interrupt flag" "No error,Error" eventfld.long 0x00 16. " CEIF ,Correctable error interrupt flag" "No error,Error" eventfld.long 0x00 3. " HANCEIOF ,Host access with non-correctable error interrupt overrun flag" "No overrun,Overrun" textline " " eventfld.long 0x00 2. " FANCEIOF ,FlexCAN access with non-correctable error interrupt overrun flag" "No overrun,Overrun" eventfld.long 0x00 0. " CEIOF ,Correctable error interrupt overrun flag" "No overrun,Overrun" sif !cpuis("MAC57D54H-CA5")&&!cpuis("MAC57D54H-CM0")&&!cpuis("MAC57D54H-CM4") if (((per.l(ad:0x400A4000)&0x40000000)==0x40000000)) group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" bitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" bitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" bitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" bitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0xC00++0x03 line.long 0x00 "CAN_FDCTRL,CAN FD Control Register" bitfld.long 0x00 31. " FDRATE , Bit rate switch enable" "Nominal rate,Rate switching" rbitfld.long 0x00 19.--20. " MBDSR1 ,Message buffer data size for region 1" "8,16,32,64" rbitfld.long 0x00 16.--17. " MBDSR0 ,Message buffer data size for region 0" "8,16,32,64" rbitfld.long 0x00 15. " TDCEN ,Transceiver delay compensation enable" "Disabled,Enabled" textline " " eventfld.long 0x00 14. " TDCFAIL ,Transceiver delay compensation fail" "In range,Out of range" rbitfld.long 0x00 8.--12. " TDCOFF ,Transceiver delay compensation offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCVAL ,Transceiver delay compenstaion value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0x400A4000)&0x40000000)==0x40000000)) group.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" else rgroup.long 0xC04++0x03 line.long 0x00 "CAN_FDCBT,CAN FD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ,Fast prescaler division factor" bitfld.long 0x00 16.--17. " FRJW ,Fast resync jump width" "1,2,3,4" bitfld.long 0x00 10.--14. " FPROPSEG ,Fast propagation segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " FPSEG1 ,Fast phase segment 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--2. " FPSEG2 ,Fast phase segment 2" "0,1,2,3,4,5,6,7" endif group.long 0xC08++0x03 line.long 0x00 "CAN_FDCRC,CAN FD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " FD_MBCRC ,CRC mailbox number for FD_TXCRC" hexmask.long.tbyte 0x00 0.--20. 1. " FD_TXCTC ,Extended transmitted CTC value" endif endif width 0x0B tree.end endif tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIOA" base ad:0x400FF000 width 6. sif cpuis("K32W0?2S1M*") group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31] ,Port data output bit 31" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Port data output bit 30" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Port data output bit 27" "Low,High" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Port data output bit 26" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Port data output bit 25" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Port data output bit 24" "Low,High" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Port data output bit 23" "Low,High" textline " " setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Port data output bit 22" "Low,High" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Port data output bit 21" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Port data output bit 20" "Low,High" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output bit 19" "Low,High" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" textline " " setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" else group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif (!cpuis("MKV5?F1M0VLL24")) setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port data output bit 29" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Port data output bit 27" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Port data output bit 26" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Port data output bit 25" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Port data output bit 24" "Low,High" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output bit 19" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output bit 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output bit 6" "Low,High" textline " " else setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port data output bit 19" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" textline " " endif setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output bit 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" endif wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PTOR[31] ,Port toggle output bit 31" "No effect,Toggle" bitfld.long 0x00 30. " [30] ,Port toggle output bit 30" "No effect,Toggle" endif sif (!cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 28. " [28] ,Port toggle output bit 28" "No effect,Toggle" bitfld.long 0x00 27. " [27] ,Port toggle output bit 27" "No effect,Toggle" bitfld.long 0x00 26. " [26] ,Port toggle output bit 26" "No effect,Toggle" textline " " bitfld.long 0x00 25. " [25] ,Port toggle output bit 25" "No effect,Toggle" bitfld.long 0x00 24. " [24] ,Port toggle output bit 24" "No effect,Toggle" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 23. " [24] ,Port toggle output bit 23" "No effect,Toggle" bitfld.long 0x00 22. " [22] ,Port toggle output bit 22" "No effect,Toggle" bitfld.long 0x00 21. " [21] ,Port toggle output bit 21" "No effect,Toggle" bitfld.long 0x00 20. " [20] ,Port toggle output bit 20" "No effect,Toggle" endif bitfld.long 0x00 19. " [19] ,Port toggle output bit 19" "No effect,Toggle" bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" endif bitfld.long 0x00 15. " [15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" textline " " sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" textline " " bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" endif bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" textline " " bitfld.long 0x00 7. " [7] ,Port toggle output bit 7" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" endif textline " " else bitfld.long 0x00 19. " PTTO[19] ,Port toggle output bit 19" "No effect,Toggle" bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" textline " " bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" bitfld.long 0x00 15. " [15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" textline " " bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" endif bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PDI[31] ,Port data input bit 31" "Low,High" bitfld.long 0x00 30. " PDI[30] ,Port data input bit 30" "Low,High" endif sif (!cpuis("MKV5?F1M0VLL24")) sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 29. " PDI[29] ,Port data input bit 29" "Low,High" endif bitfld.long 0x00 28. " [28] ,Port data input bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data input bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data input bit 26" "Low,High" textline " " bitfld.long 0x00 25. " [25] ,Port data input bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data input bit 24" "Low,High" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 24. " PDI[24] ,Port data input bit 24" "Low,High" bitfld.long 0x00 23. " PDI[23] ,Port data input bit 23" "Low,High" bitfld.long 0x00 22. " PDI[22] ,Port data input bit 22" "Low,High" bitfld.long 0x00 21. " PDI[21] ,Port data input bit 21" "Low,High" bitfld.long 0x00 20. " PDI[20] ,Port data input bit 20" "Low,High" endif bitfld.long 0x00 19. " [19] ,Port data input bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" textline " " bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" endif bitfld.long 0x00 15. " [15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" textline " " sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" textline " " bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" endif bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Port data input bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" textline " " endif else bitfld.long 0x00 19. " PDI[19] ,Port data input bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" textline " " bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" textline " " bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" endif bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" textline " " bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PDD[31] ,Port data direction bit 31" "Input,Output" bitfld.long 0x00 30. " PDD[30] ,Port data direction bit 30" "Input,Output" endif sif (!cpuis("MKV5?F1M0VLL24")) sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 29. " PDD[29] ,Port data direction bit 29" "Input,Output" endif bitfld.long 0x00 28. " [28] ,Port data direction bit 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Port data direction bit 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction bit 26" "Input,Output" textline " " bitfld.long 0x00 25. " [25] ,Port data direction bit 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction bit 24" "Input,Output" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 23. " PDD[23] ,Port data direction bit 23" "Input,Output" bitfld.long 0x00 22. " PDD[22] ,Port data direction bit 22" "Input,Output" bitfld.long 0x00 21. " PDD[21] ,Port data direction bit 21" "Input,Output" bitfld.long 0x00 20. " PDD[20] ,Port data direction bit 20" "Input,Output" endif bitfld.long 0x00 19. " [19] ,Port data direction bit 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" textline " " bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" endif bitfld.long 0x00 15. " [15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" textline " " sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" textline " " bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" endif bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" textline " " bitfld.long 0x00 7. " [7] ,Port data direction bit 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" endif textline " " else bitfld.long 0x00 19. " PDD[19] ,Port data direction bit 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" textline " " bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" textline " " bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" endif bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" textline " " bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B tree.end tree "GPIOB" base ad:0x400FF040 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PDO[31] ,Port data output bit 31" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30] ,Port data output bit 30" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port data output bit 29" "Low,High" textline " " setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port data output bit 26" "Low,High" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port data output bit 25" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port data output bit 24" "Low,High" endif sif !cpuis("K32W0?2S1M*") setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23] ,Port data output bit 23" "Low,High" endif setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Port data output bit 22" "Low,High" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Port data output bit 21" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Port data output bit 20" "Low,High" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output bit 19" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" endif textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" sif !cpuis("K32W0?2S1M*") setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" endif setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" sif (!cpuis("MKV5?F1M0VLL24")) sif cpuis("K32*") setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" endif setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output bit 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output bit 6" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output bit 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" endif textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PTTO[31] ,Port toggle output bit 31" "No effect,Toggle" bitfld.long 0x00 30. " [30] ,Port toggle output bit 30" "No effect,Toggle" bitfld.long 0x00 29. " [29] ,Port toggle output bit 29" "No effect,Toggle" bitfld.long 0x00 28. " [28] ,Port toggle output bit 29" "No effect,Toggle" bitfld.long 0x00 26. " [26] ,Port toggle output bit 26" "No effect,Toggle" bitfld.long 0x00 25. " [25] ,Port toggle output bit 25" "No effect,Toggle" bitfld.long 0x00 24. " [24] ,Port toggle output bit 24" "No effect,Toggle" else bitfld.long 0x00 23. " PTTO[23] ,Port toggle output bit 23" "No effect,Toggle" endif bitfld.long 0x00 22. " [22] ,Port toggle output bit 22" "No effect,Toggle" bitfld.long 0x00 21. " [21] ,Port toggle output bit 21" "No effect,Toggle" bitfld.long 0x00 20. " [20] ,Port toggle output bit 20" "No effect,Toggle" textline " " bitfld.long 0x00 19. " [19] ,Port toggle output bit 19" "No effect,Toggle" bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" endif textline " " bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" endif bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" sif (!cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" textline " " bitfld.long 0x00 7. " [7] ,Port toggle output bit 7" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" endif textline " " bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PDI[31] ,Port data input bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port data input bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input bit 28" "Low,High" bitfld.long 0x00 28. " [26] ,Port data input bit 26" "Low,High" bitfld.long 0x00 28. " [25] ,Port data input bit 25" "Low,High" bitfld.long 0x00 28. " [24] ,Port data input bit 24" "Low,High" else bitfld.long 0x00 23. " PDI[23] ,Port data input bit 23" "Low,High" endif bitfld.long 0x00 22. " [22] ,Port data input bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input bit 20" "Low,High" textline " " bitfld.long 0x00 19. " [19] ,Port data input bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" endif textline " " bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" endif bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" sif (!cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Port data input bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" endif textline " " bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " PDD[31] ,Port data direction bit 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Port data direction bit 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction bit 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction bit 28" "Input,Output" bitfld.long 0x00 26. " [26] ,Port data direction bit 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction bit 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction bit 24" "Input,Output" else bitfld.long 0x00 23. " PDD[23] ,Port data direction bit 23" "Input,Output" endif bitfld.long 0x00 22. " [22] ,Port data direction bit 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction bit 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction bit 20" "Input,Output" textline " " bitfld.long 0x00 19. " [19] ,Port data direction bit 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" endif textline " " bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" endif bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" sif (!cpuis("MKV5?F1M0VLL24")) bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" textline " " bitfld.long 0x00 7. " [7] ,Port data direction bit 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" endif textline " " bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B tree.end tree "GPIOC" base ad:0x400FF080 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30] ,Port data output bit 30" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port data output bit 29" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port data output bit 27" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port data output bit 26" "Low,High" endif sif (!cpuis("MKV5?F1M0VLL24")&&!cpuis("K32W0?2S1M*")) setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port data output bit 19" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" textline " " else setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" textline " " endif sif !cpuis("K32W0?2S1M*") setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" elif cpuis("K32W0?2S1M*") setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output bit 7" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" endif wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 30. " [30] ,Port toggle output bit 30" "No effect,Toggle" bitfld.long 0x00 29. " [29] ,Port toggle output bit 29" "No effect,Toggle" bitfld.long 0x00 28. " [28] ,Port toggle output bit 28" "No effect,Toggle" bitfld.long 0x00 27. " [27] ,Port toggle output bit 27" "No effect,Toggle" bitfld.long 0x00 26. " [26] ,Port toggle output bit 26" "No effect,Toggle" endif sif (!cpuis("MKV5?F1M0VLL24")&&!cpuis("K32W0?2S1M*")) bitfld.long 0x00 19. " PTTO[19] ,Port toggle output bit 19" "No effect,Toggle" bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" textline " " else bitfld.long 0x00 18. " PTTO[18] ,Port toggle output bit 18" "No effect,Toggle" bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" endif bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" textline " " bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" textline " " bitfld.long 0x00 7. " [7] ,Port toggle output bit 7" "No effect,Toggle" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" textline " " bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" endif bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 30. " PDI[30] ,Port data input bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data input bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port data input bit 26" "Low,High" endif sif (!cpuis("MKV5?F1M0VLL24")&&!cpuis("K32W0?2S1M*")) bitfld.long 0x00 19. " PDI[19] ,Port data input bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" textline " " else bitfld.long 0x00 18. " PDI[18] ,Port data input bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" endif textline " " bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Port data input bit 7" "Low,High" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" textline " " bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" endif bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 30. " PDD[30] ,Port data direction bit 30" "Input,Output" bitfld.long 0x00 29. " PDD[29] ,Port data direction bit 29" "Input,Output" bitfld.long 0x00 28. " PDD[28] ,Port data direction bit 28" "Input,Output" bitfld.long 0x00 27. " PDD[27] ,Port data direction bit 27" "Input,Output" bitfld.long 0x00 26. " PDD[26] ,Port data direction bit 26" "Input,Output" endif sif (!cpuis("MKV5?F1M0VLL24")&&!cpuis("K32W0?2S1M*")) bitfld.long 0x00 19. " PDD[19] ,Port data direction bit 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" textline " " else bitfld.long 0x00 18. " PDD[18] ,Port data direction bit 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" textline " " endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" textline " " endif bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" textline " " bitfld.long 0x00 7. " [7] ,Port data direction bit 7" "Input,Output" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" textline " " bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" endif bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B tree.end tree "GPIOD" base ad:0x400FF0C0 width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" sif (!cpuis("MKV5?F1M0VLL24")&&!cpuis("K32W0?2S1M*")) setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" textline " " elif cpuis("K32W0?2S1M*") setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output bit 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output bit 6" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output bit 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" endif wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif (!cpuis("MKV5?F1M0VLL24")) sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " PTTO[15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" endif textline " " bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" textline " " bitfld.long 0x00 7. " [7] ,Port toggle output bit 7" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" textline " " bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" endif rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif (!cpuis("MKV5?F1M0VLL24")) sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " PDI[15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" endif textline " " bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" textline " " bitfld.long 0x00 7. " [7] ,Port data input bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" textline " " bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" endif group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif (!cpuis("MKV5?F1M0VLL24")) sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " PDD[15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" endif textline " " bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" textline " " bitfld.long 0x00 7. " [7] ,Port data direction bit 7" "Input,Output" endif bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" textline " " bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B tree.end tree "GPIOE" base ad:0x400FF100 sif cpuis("MKV5?F1M0VLL24") width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30] ,Port data output bit 30" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Port data output bit 29" "Low,High" sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Port data output bit 27" "Low,High" else setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Port data output bit 26" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Port data output bit 25" "Low,High" textline " " setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Port data output bit 24" "Low,High" endif sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Port data output bit 22" "Low,High" endif setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Port data output bit 21" "Low,High" sif !cpuis("K32W0?2S1M*") setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Port data output bit 20" "Low,High" endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output bit 19" "Low,High" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" sif cpuis("K32W0?2S1M*") setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Port data output bit 15" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Port data output bit 14" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" textline " " setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 12" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" else setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output bit 6" "Low,High" endif textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output bit 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" bitfld.long 0x00 30. " PTTO[30] ,Port toggle output bit 30" "No effect,Toggle" bitfld.long 0x00 29. " [29] ,Port toggle output bit 29" "No effect,Toggle" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 27. " [27] ,Port toggle output bit 27" "No effect,Toggle" else bitfld.long 0x00 26. " [26] ,Port toggle output bit 26" "No effect,Toggle" bitfld.long 0x00 25. " [25] ,Port toggle output bit 25" "No effect,Toggle" textline " " bitfld.long 0x00 24. " [24] ,Port toggle output bit 24" "No effect,Toggle" endif sif cpuis("K32W0?2S1M*") bitfld.long 0x00 22. " [22] ,Port toggle output bit 22" "No effect,Toggle" endif bitfld.long 0x00 21. " [21] ,Port toggle output bit 21" "No effect,Toggle" sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 20. " [20] ,Port toggle output bit 20" "No effect,Toggle" endif bitfld.long 0x00 19. " [19] ,Port toggle output bit 19" "No effect,Toggle" textline " " bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port toggle output bit 15" "No effect,Toggle" bitfld.long 0x00 14. " [14] ,Port toggle output bit 14" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" else bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" textline " " endif bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" textline " " bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 30. " PDI[30] ,Port data input bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input bit 29" "Low,High" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 27. " [27] ,Port data input bit 27" "Low,High" else bitfld.long 0x00 26. " [26] ,Port data input bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data input bit 25" "Low,High" textline " " bitfld.long 0x00 24. " [24] ,Port data input bit 24" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input bit 21" "Low,High" endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 20. " [20] ,Port data input bit 20" "Low,High" endif bitfld.long 0x00 19. " [19] ,Port data input bit 19" "Low,High" textline " " bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data input bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port data input bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" else bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" endif textline " " bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" textline " " bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 30. " PDD[30] ,Port data direction bit 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction bit 29" "Input,Output" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 27. " [27] ,Port data direction bit 27" "Input,Output" else bitfld.long 0x00 26. " [26] ,Port data direction bit 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction bit 25" "Input,Output" textline " " bitfld.long 0x00 24. " [24] ,Port data direction bit 24" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction bit 21" "Input,Output" endif sif !cpuis("K32W0?2S1M*") bitfld.long 0x00 20. " [20] ,Port data direction bit 20" "Input,Output" endif bitfld.long 0x00 19. " [19] ,Port data direction bit 19" "Input,Output" textline " " bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 15. " [15] ,Port data direction bit 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Port data direction bit 14" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" else bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" endif textline " " bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" textline " " bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B else width 6. group.long 0x00++0x03 line.long 0x00 "PDOR,Port Data Output Register" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30] ,Port data output bit 30" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Port data output bit 29" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Port data output bit 28" "Low,High" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Port data output bit 27" "Low,High" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Port data output bit 26" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Port data output bit 25" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Port data output bit 24" "Low,High" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Port data output bit 23" "Low,High" textline " " setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Port data output bit 22" "Low,High" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Port data output bit 21" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Port data output bit 20" "Low,High" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output bit 19" "Low,High" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output bit 18" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output bit 17" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output bit 16" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output bit 13" "Low,High" textline " " setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output bit 12" "Low,High" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Port data output bit 11" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output bit 10" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output bit 9" "Low,High" textline " " setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output bit 8" "Low,High" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output bit 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output bit 6" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output bit 5" "Low,High" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output bit 4" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output bit 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output bit 2" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output bit 1" "Low,High" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output bit 0" "Low,High" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" bitfld.long 0x00 30. " PTTO[30] ,Port toggle output bit 30" "No effect,Toggle" bitfld.long 0x00 29. " [29] ,Port toggle output bit 29" "No effect,Toggle" bitfld.long 0x00 28. " [28] ,Port toggle output bit 28" "No effect,Toggle" bitfld.long 0x00 27. " [27] ,Port toggle output bit 27" "No effect,Toggle" textline " " bitfld.long 0x00 26. " [26] ,Port toggle output bit 26" "No effect,Toggle" bitfld.long 0x00 25. " [25] ,Port toggle output bit 25" "No effect,Toggle" bitfld.long 0x00 24. " [24] ,Port toggle output bit 24" "No effect,Toggle" bitfld.long 0x00 23. " [23] ,Port toggle output bit 23" "No effect,Toggle" textline " " bitfld.long 0x00 22. " [22] ,Port toggle output bit 22" "No effect,Toggle" bitfld.long 0x00 21. " [21] ,Port toggle output bit 21" "No effect,Toggle" bitfld.long 0x00 20. " [20] ,Port toggle output bit 20" "No effect,Toggle" bitfld.long 0x00 19. " [19] ,Port toggle output bit 19" "No effect,Toggle" textline " " bitfld.long 0x00 18. " [18] ,Port toggle output bit 18" "No effect,Toggle" bitfld.long 0x00 17. " [17] ,Port toggle output bit 17" "No effect,Toggle" bitfld.long 0x00 16. " [16] ,Port toggle output bit 16" "No effect,Toggle" bitfld.long 0x00 13. " [13] ,Port toggle output bit 13" "No effect,Toggle" textline " " bitfld.long 0x00 12. " [12] ,Port toggle output bit 12" "No effect,Toggle" bitfld.long 0x00 11. " [11] ,Port toggle output bit 11" "No effect,Toggle" bitfld.long 0x00 10. " [10] ,Port toggle output bit 10" "No effect,Toggle" bitfld.long 0x00 9. " [9] ,Port toggle output bit 9" "No effect,Toggle" textline " " bitfld.long 0x00 8. " [8] ,Port toggle output bit 8" "No effect,Toggle" bitfld.long 0x00 7. " [7] ,Port toggle output bit 7" "No effect,Toggle" bitfld.long 0x00 6. " [6] ,Port toggle output bit 6" "No effect,Toggle" bitfld.long 0x00 5. " [5] ,Port toggle output bit 5" "No effect,Toggle" textline " " bitfld.long 0x00 4. " [4] ,Port toggle output bit 4" "No effect,Toggle" bitfld.long 0x00 3. " [3] ,Port toggle output bit 3" "No effect,Toggle" bitfld.long 0x00 2. " [2] ,Port toggle output bit 2" "No effect,Toggle" bitfld.long 0x00 1. " [1] ,Port toggle output bit 1" "No effect,Toggle" textline " " bitfld.long 0x00 0. " [0] ,Port toggle output bit 0" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 30. " PDI[30] ,Port data input bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port data input bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port data input bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port data input bit 27" "Low,High" textline " " bitfld.long 0x00 26. " [26] ,Port data input bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port data input bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port data input bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port data input bit 23" "Low,High" textline " " bitfld.long 0x00 22. " [22] ,Port data input bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port data input bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port data input bit 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port data input bit 19" "Low,High" textline " " bitfld.long 0x00 18. " [18] ,Port data input bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port data input bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port data input bit 16" "Low,High" bitfld.long 0x00 13. " [13] ,Port data input bit 13" "Low,High" textline " " bitfld.long 0x00 12. " [12] ,Port data input bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port data input bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port data input bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port data input bit 9" "Low,High" textline " " bitfld.long 0x00 8. " [8] ,Port data input bit 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port data input bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port data input bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port data input bit 5" "Low,High" textline " " bitfld.long 0x00 4. " [4] ,Port data input bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port data input bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port data input bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port data input bit 1" "Low,High" textline " " bitfld.long 0x00 0. " [0] ,Port data input bit 0" "Low,High" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 30. " PDD[30] ,Port data direction bit 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction bit 29" "Input,Output" bitfld.long 0x00 28. " [28] ,Port data direction bit 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Port data direction bit 27" "Input,Output" textline " " bitfld.long 0x00 26. " [26] ,Port data direction bit 26" "Input,Output" bitfld.long 0x00 25. " [25] ,Port data direction bit 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction bit 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Port data direction bit 23" "Input,Output" textline " " bitfld.long 0x00 22. " [22] ,Port data direction bit 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Port data direction bit 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction bit 20" "Input,Output" bitfld.long 0x00 19. " [19] ,Port data direction bit 19" "Input,Output" textline " " bitfld.long 0x00 18. " [18] ,Port data direction bit 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Port data direction bit 17" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction bit 16" "Input,Output" bitfld.long 0x00 13. " [13] ,Port data direction bit 13" "Input,Output" textline " " bitfld.long 0x00 12. " [12] ,Port data direction bit 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Port data direction bit 11" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction bit 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction bit 9" "Input,Output" textline " " bitfld.long 0x00 8. " [8] ,Port data direction bit 8" "Input,Output" bitfld.long 0x00 7. " [7] ,Port data direction bit 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction bit 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction bit 5" "Input,Output" textline " " bitfld.long 0x00 4. " [4] ,Port data direction bit 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Port data direction bit 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction bit 2" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction bit 1" "Input,Output" textline " " bitfld.long 0x00 0. " [0] ,Port data direction bit 0" "Input,Output" width 0x0B endif tree.end tree.end elif cpuis("MKV4*") tree.open "PORT (Port Control and Interrupts)" tree "PORTA" base ad:0x40049000 width 13. group.long 0x00++0x13 line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA0,UART0_CTS_b/UART0_COL_b,FTM0_CH5,XBAR0_IN4,EWM_IN,,JTAG_TCLK/SWD_CLK" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA1,UART0_RX,FTM0_CH6,CMP0_OUT,,FTM1_CH1,JTAG_TDI" newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull Select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA2,UART0_TX,FTM0_CH7,CMP1_OUT,,FTM1_CH0,JTAG_TDO/TRACE_SWO" newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA3,UART0_RTS_b,FTM0_CH0,XBAR0_IN9,EWM_OUT_b,FlexPWMA_A0,JTAG_TMS/SWD_DIO" newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTA4/LLWU_P3,,FTM0_CH1,XBAR0_IN10,FTM0_FLT3,FlexPWMA_B0,NMI_b" newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA5,,FTM0_CH2,,CMP2_OUT,,JTAG_TRST_b" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x30++0x07 line.long 0x00 "PORTA_PCR12,Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP2_IN0,PTA12,CAN0_TX,FTM1_CH0,,,,FTM1_QD_PHA" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR13,Pin Control Register 13" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "CMP2_IN1,PTA13/LLWU_P4,CAN0_RX,FTM1_CH1,,,,FTM1_QD_PHB" newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x48++0x07 line.long 0x00 "PORTA_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTA18,XBAR0_IN7,FTM0_FLT2,FTM_CLKIN0,XBAR0_OUT8,FTM3_CH2,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTA19,XBAR0_IN8,FTM1_FLT0,FTM_CLKIN1,XBAR0_OUT9,LPTMR0_ALT1,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" newline wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 29. " GPWE[13] ,Global pin 13 write enable" "Disabled,Enabled" bitfld.long 0x00 28. " [12] ,Global pin 12 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" else bitfld.long 0x00 20. " GPWE[4] ,Global pin 4 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" newline hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status flag register" eventfld.long 0x00 19. " ISF[19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") eventfld.long 0x00 13. " [13] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 12. " [12] ,Interrupt status Flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" newline endif eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x03 line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" bitfld.long 0x00 19. " DFE[19] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Digital filter" "Disabled,Enabled" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") bitfld.long 0x00 13. " [13] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter" "Disabled,Enabled" newline endif bitfld.long 0x00 4. " [4] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" group.long 0xC4++0x07 line.long 0x00 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x04 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x04 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTB" base ad:0x4004A000 width 13. group.long 0x00++0x0F line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCB_CH2,PTB0/LLWU_P5,I2C0_SCL,FTM1_CH0,,,FTM1_QD_PHA,UART0_RX" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCB_CH3,PTB1,I2C0_SDA,FTM1_CH1,FTM0_FLT2,EWM_IN,FTM1_QD_PHB,UART0_TX" newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADCA_CH6e/CMP2_IN2,PTB2,I2C0_SCL,UART0_RTS_b,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive Filter Enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADCB_CH7e/CMP3_IN5,PTB3,I2C0_SDA,UART0_CTS_b/UART0_COL_b,,,FTM0_FLT0,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x40++0x07 line.long 0x00 "PORTB_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,UART0_RX,FTM_CLKIN2,CAN0_TX,EWM_IN,XBARIN5" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,UART0_TX,FTM_CLKIN1,CAN0_RX,EWM_OUT_b,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.long 0x48++0x07 line.long 0x00 "PORTB_PCR18,Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTB16,,UART0_RX,FTM_CLKIN2,CAN0_TX,EWM_IN,XBARIN5" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR19,Pin Control Register 19" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTB17,,UART0_TX,FTM_CLKIN1,CAN0_RX,EWM_OUT_b,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif newline wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 19. " GPWE[3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x04 19. " GPWE[19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" else bitfld.long 0x04 17. " GPWE[17] ,Global pin 17 write enable" "Disabled,Enabled" endif newline bitfld.long 0x04 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 17. " ISF[17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" else group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 19. " ISF[19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xC0++0x03 line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" bitfld.long 0x00 17. " DFE[17] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" else group.long 0xC0++0x03 line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" bitfld.long 0x00 19. " DFE[19] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" endif group.long 0xC4++0x07 line.long 0x00 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x04 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x04 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTC" base ad:0x4004B000 width 13. group.long 0x00++0x1F line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCB_CH6b,PTC0,SPI0_PCS4,PDB0_EXTRG,,,FTM0_FLT1,SPI0_PCS0" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCB_CH7b,PTC1/LLWU_P6,SPI0_PCS3,UART1_RTS_b,FTM0_CH0,FLEXPWMA_A3,XBARIN11,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADCB_CH6c/CMP1_IN0,PTC2,SPI0_PCS2,UART1_CTS_b,FTM0_CH1,FLEXPWMA_B3,XBARIN6,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "CMP1_IN1,PTC3/LLWU_P7,SPI0_PCS1,UART1_RX,FTM0_CH2,CLKOUT,FTM3_FLT0,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTC4/LLWU_P8,SPI0_PCS0,UART1_TX,FTM0_CH3,,CMP1_OUT,?..." newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTC5/LLWU_P9,SPI0_SCK,LPTMR0_ALT2,XBARIN2,,CMP0_OUT,FTM0_CH2" newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "CMP2_IN4/CMP0_IN0,PTC6/LLWU_P10,SPI0_SOUT,PDB0_EXTRG,XBARIN3,UART0_RX,XBAROUT6,I2C0_SCL" newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open Drain Enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x18 0. " PS ,Pull Select" "Pull-down,Pull-up" line.long 0x1C "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "CMP3_IN4/CMP0_IN1,PTC7,SPI0_SIN,,XBARIN4,UART0_TX,XBAROUT7,I2C0_SDA" newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") group.long 0x20++0x0F line.long 0x00 "PORTC_PCR8,Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCB_CH7c/CMP0_IN2,PTC8,,FTM3_CH4,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR9,Pin Control Register 9" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCB_CH6d/CMP0_IN3,PTC9,,FTM3_CH5,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR10,Pin Control Register 10" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADCB_CH7d,PTC10,,FTM3_CH6,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR11,Pin Control Register 11" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADCB_CH6e,PTC11/LLWU_P11,,FTM3_CH7,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif newline wgroup.long 0x80++0x03 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 27. " GPWE[11] ,Global pin 11 write enable" "Disabled,Enabled" bitfld.long 0x00 26. " [10] ,Global pin 10 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [9] ,Global pin 9 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [8] ,Global pin 8 write enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [7] ,Global pin 7 write enable" "Disabled,Enabled" else bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Disabled,Enabled" endif newline bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 7. " ISF[7] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" else group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 11. " ISF[11] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 10. " [10] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 9. " [9] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 8. " [8] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 7. " [7] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xC0++0x03 line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 7. " DFE[7] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital Filter" "Disabled,Enabled" else group.long 0xC0++0x03 line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 11. " DFE[11] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital Filter" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" endif group.long 0xC4++0x07 line.long 0x00 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x04 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x04 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTD" base ad:0x4004C000 width 13. group.long 0x00++0x1F line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD0/LLWU_P12,SPI0_PCS0,,FTM3_CH0,FTM0_CH0,FlexPWMA_A0,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCA_CH7f,PTD1,SPI0_SCK,,FTM3_CH1,FTM0_CH1,FlexPWMA_B0,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD2/LLWU_P13,SPI0_SOUT,,FTM3_CH2,FTM0_CH2,FlexPWMA_A1,I2C0_SCL" newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTD3,SPI0_SIN,,FTM3_CH3,FTM0_CH3,FlexPWMA_B1,I2C0_SDA" newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTD4/LLWU_P14,SPI0_PCS1,UART0_RTS_b,FTM0_CH4,FlexPWMA_A2,EWM_IN,SPI0_PCS0" newline bitfld.long 0x10 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x10 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x10 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "ADCA_CH6g,PTD5,SPI0_PCS2,UART0_CTS_b/UART0_COL_b,FTM0_CH5,FlexPWMA_B2,EWM_OUT_b,SPI0_SCK" newline bitfld.long 0x14 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x14 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x14 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "ADCA_CH7g,PTD6/LLWU_P15,SPI0_PCS3,UART0_RX,FTM0_CH6,FTM1_CH0,FTM0_FLT0,SPI0_SOUT" newline bitfld.long 0x18 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x18 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x18 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" ",PTD7,,UART0_TX,FTM0_CH7,FTM1_CH1,FTM0_FLT1,SPI0_SIN" newline bitfld.long 0x1C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x1C 5. " ODE ,Open Drain Enable" "Disabled,Enabled" newline bitfld.long 0x1C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" newline wgroup.long 0x80++0x03 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 23. " GPWE[7] ,Global pin 7 write enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Global pin 6 write enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Global pin 5 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Global pin 4 write enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Global pin 3 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Global pin 2 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 7. " ISF[7] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " [6] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " [5] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 4. " [4] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " [3] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " [2] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 7. " DFE[7] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTD_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTE" base ad:0x4004D000 width 13. sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") group.long 0x00++0x07 line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCB_CH6f,PTE0/CLKOUT32K,,UART1_TX,XBAR0_OUT10,XBAR0_IN11,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCB_CH7f,PTE1/LLWU_P0,,UART1_RX,XBAR0_OUT11,XBAR0_IN7,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x40++0x0F line.long 0x00 "PORTE_PCR16,Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCA_CH0,PTE16,SPI0_PCS0,UART1_TX,FTM_CLKIN0,,FTM0_FLT3,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR17,Pin Control Register 17" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCA_CH1,PTE17/LLWU_P19,SPI0_SCK,UART1_RX,FTM_CLKIN1,,LPTMR0_ALT3,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTE_PCR18,Pin Control Register 18" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADCB_CH0,PTE18/LLWU_P20,SPI0_SOUT,UART1_CTS_b,I2C0_SDA,?..." newline bitfld.long 0x08 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x08 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTE_PCR19,Pin Control Register 19" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADCB_CH1,PTE19,SPI0_SIN,UART1_RTS_b,I2C0_SCL,,CMP3_OUT,?..." newline bitfld.long 0x0C 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x0C 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0x50++0x07 line.long 0x00 "PORTE_PCR20,Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCA_CH6b,PTE20,,FTM1_CH0,UART0_TX,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open Drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR21,Pin Control Register 21" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCA_CH7b,PTE21,,FTM1_CH1,UART0_RX,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x60++0x07 line.long 0x00 "PORTE_PCR24,Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCB_CH4,PTE24,CAN1_TX,FTM0_CH0,XBAR0_IN2,I2C0_SCL,EWM_OUT_b,XBAR0_OUT4" newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR25,Pin Control Register 25" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADCB_CH5,PTE25/LLWU_P21,CAN1_RX,FTM0_CH1,XBAR0_IN3,I2C0_SDA,EWM_IN,XBAR0_OUT5" newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" group.long 0x74++0x07 line.long 0x00 "PORTE_PCR29,Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt Status Flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADCA_CH4/CMP1_IN5/CMP0_IN5,PTE29,,FTM0_CH2,,FTM_CLKIN0,?..." newline bitfld.long 0x00 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x00 5. " ODE ,Open Drain Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR30,Pin Control Register 30" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA rising edge,DMA falling edge,DMA either edge,,,,,Interrupt when logic 0,Interrupt on rising edge,Interrupt on falling edge,Interrupt on either edge,Interrupt when logic 1,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" newline bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "DAC0_OUT/CMP1_IN3/ADCA_CH5,PTE30,,FTM0_CH3,,FTM_CLKIN1,?..." newline bitfld.long 0x04 6. " DSE ,Drive strength enable" "Low,High" bitfld.long 0x04 5. " ODE ,Open drain enable" "Disabled,Enabled" newline bitfld.long 0x04 4. " PFE ,Passive filter enable" "Disabled,Enabled" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" newline sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") wgroup.long 0x80++0x03 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" bitfld.long 0x00 17. " GPWE[1] ,Global pin 1 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Global pin 0 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" endif wgroup.long 0x84++0x03 line.long 0x00 "PORTE_GPCHR,Global Pin Control High Register" bitfld.long 0x00 30. " GPWE[30] ,Global pin 30 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Global pin 29 write enable" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Global pin 25 write enable" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Global pin 24 write enable" "Disabled,Enabled" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 21. " [21] ,Global pin 21 write enable" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Global pin 20 write enable" "Disabled,Enabled" newline endif bitfld.long 0x00 19. " [19] ,Global pin 19 write enable" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Global pin 18 write enable" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Global pin 17 write enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Global pin 16 write enable" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 30. " ISF[30] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 29. " [29] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 25. " [25] ,Interrupt Status Flag" "Not detected,Detected" newline eventfld.long 0x00 24. " [24] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 21. " [21] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 20. " [20] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 19. " [19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" else group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 30. " ISF[30] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 29. " [29] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 25. " [25] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 24. " [24] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 19. " [19] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 18. " [18] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 17. " [17] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 16. " [16] ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " [1] ,Interrupt status flag" "Not detected,Detected" newline eventfld.long 0x00 0. " [0] ,Interrupt status flag" "Not detected,Detected" endif sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") group.long 0xC0++0x03 line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" bitfld.long 0x00 30. " DFE[30] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 24. " [24] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Digital filter" "Disabled,Enabled" else group.long 0xC0++0x03 line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" bitfld.long 0x00 30. " DFE[30] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 24. " [24] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 17. " [17] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Digital filter" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Digital filter" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Digital filter" "Disabled,Enabled" endif group.long 0xC4++0x07 line.long 0x00 "PORTE_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x04 "PORTE_DFWR,Digital Filter Width Register" bitfld.long 0x04 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end tree "SIM (System Integration Module)" base ad:0x40048000 width 10. group.long 0x00++0x07 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,,,LPO 1 kHz" rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",,,16kB,24kB,32kB,?..." line.long 0x04 "SOPT2,System Options Register 2" bitfld.long 0x04 12. " TRACECLKSEL ,Debug trace clock select" "MCGOUTCLK,Core/system clock" bitfld.long 0x04 5.--7. " CLKOUTSEL ,CLKOUT select" ",,Flash Clock,LPO Clock,MCGIRCLK,OSCERCLK_UNDIV,OSCERCLK,?..." group.long 0x0C++0x07 line.long 0x00 "SOPT4,System Options Register 4" bitfld.long 0x00 30. " FTM3TRG2SRC ,FlexTimer 3 hardware trigger 2 source select" "FTM3_FLT0,XBARA[37]" bitfld.long 0x00 29. " FTM3TRG1SRC ,FlexTimer 3 hardware trigger 1 source select" "PDB1,FTM1" bitfld.long 0x00 28. " FTM3TRG0SRC ,FlexTimer 3 hardware trigger 0 source select" "CMP0,FTM1" newline bitfld.long 0x00 22. " FTM1TRG2SRC ,FlexTimer 1 hardware trigger 2 source select" "FTM1_FLT0,XBARA[35]" bitfld.long 0x00 20. " FTM1TRG0SRC ,FlexTimer 1 hardware trigger 0 source select" "HSCMP0,FTM0" bitfld.long 0x00 18. " FTM0TRG2SRC ,FlexTimer 0 hardware trigger 2 source select" "FTM0_FLT0,XBARA[34]" newline bitfld.long 0x00 17. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 source select" "PDB0,FTM1" bitfld.long 0x00 16. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 source select" "CMP0,FTM1" bitfld.long 0x00 12. " FTM3FLT0 ,FTM3 fault 0 select" "FTM3_FLT0,CMP0" newline bitfld.long 0x00 4. " FTM1FLT0 ,FTM1 fault 0 select" "FTM1_FLT0,CMP0" bitfld.long 0x00 3. " FTM0FLT3 ,Selects the source of FTM0 fault 3" "FTM0_FLT3,XBARA[49]" bitfld.long 0x00 2. " FTM0FLT2 ,FTM0 fault 2 select" "FTM0_FLT2,CMP2" newline bitfld.long 0x00 1. " FTM0FLT1 ,FTM0 fault 1 select" "FTM0_FLT1,CMP1" bitfld.long 0x00 0. " FTM0FLT0 ,FTM0 fault 0 select" "FTM0_FLT0,CMP0" line.long 0x04 "SOPT5,System Options Register 5" bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..." bitfld.long 0x04 4. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX(FTM1_0)" bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX,CMP0,CMP1,?..." newline bitfld.long 0x04 0. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX,UART0_TX(FTM1_0)" group.long 0x18++0x0B line.long 0x00 "SOPT7,System Options Register 7" bitfld.long 0x00 14.--15. " ADCBALTTRGEN ,ADCB alternate trigger enable" "XBARA[13],PDB1,Alternate,Alternate" bitfld.long 0x00 8.--11. " ADCBTRGSEL ,ADCB trigger select" ",High Speed Comp. 0,High Speed Comp. 1,High Speed Comp. 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,,FTM3 trigger,XBARA[41],,Low-power timer trigger,?..." bitfld.long 0x00 6.--7. " ADCAALTTRGEN ,ADCA alternate trigger enable" "XBARA[12],PDB0,Alternate,Alternate" newline bitfld.long 0x00 0.--3. " ADCATRGSEL , ADCA trigger select" "PDB0_EXTRG,High Speed Comp. 0,High Speed Comp. 1,High Speed Comp. 2,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,,FTM3 trigger,XBARA[38],,Low-power timer trigger,?..." line.long 0x04 "SOPT8,System Options Register 8" bitfld.long 0x04 31. " FTM3OCH7SRC ,FTM3 channel 7 output source" "Normal,Modulated" bitfld.long 0x04 30. " FTM3OCH6SRC ,FTM3 channel 6 output source" "Normal,Modulated" bitfld.long 0x04 29. " FTM3OCH5SRC ,FTM3 channel 5 output source" "Normal,Modulated" newline bitfld.long 0x04 28. " FTM3OCH4SRC ,FTM3 channel 4 output source" "Normal,Modulated" bitfld.long 0x04 27. " FTM3OCH3SRC ,FTM3 channel 3 output source" "Normal,Modulated" bitfld.long 0x04 26. " FTM3OCH2SRC ,FTM3 channel 2 output source" "Normal,Modulated" newline bitfld.long 0x04 25. " FTM3OCH1SRC ,FTM3 channel 1 output source" "Normal,Modulated" bitfld.long 0x04 24. " FTM3OCH0SRC ,FTM3 channel 0 output source" "Normal,Modulated" bitfld.long 0x04 23. " FTM0OCH7SRC ,FTM0 channel 7 output source" "Normal,Modulated" newline bitfld.long 0x04 22. " FTM0OCH6SRC ,FTM0 channel 6 output source" "Normal,Modulated" bitfld.long 0x04 21. " FTM0OCH5SRC ,FTM0 channel 5 output source" "Normal,Modulated" bitfld.long 0x04 20. " FTM0OCH4SRC ,FTM0 channel 4 output source" "Normal,Modulated" newline bitfld.long 0x04 19. " FTM0OCH3SRC ,FTM0 channel 3 output source" "Normal,Modulated" bitfld.long 0x04 18. " FTM0OCH2SRC ,FTM0 channel 2 output source" "Normal,Modulated" bitfld.long 0x04 17. " FTM0OCH1SRC ,FTM0 channel 1 output source" "Normal,Modulated" newline bitfld.long 0x04 16. " FTM0OCH0SRC ,FTM0 channel 0 output source" "Normal,Modulated" bitfld.long 0x04 9. " FTM3CFSEL ,Carrier frequency selection for FTM3 output channel" "FTM1,LPTMR0" bitfld.long 0x04 8. " FTM0CFSEL ,Carrier frequency selection for FTM0 output channel" "FTM1,LPTMR0" newline bitfld.long 0x04 3. " FTM3SYNCBIT ,FTM3 hardware trigger 0 software synchronization" "No effect,Sync" bitfld.long 0x04 1. " FTM1SYNCBIT ,FTM1 hardware trigger 0 software synchronization" "No effect,Sync" bitfld.long 0x04 0. " FTM0SYNCBIT ,FTM0 hardware trigger 0 software synchronization" "No effect,Sync" line.long 0x08 "SOPT9,System Options Register 9" bitfld.long 0x08 30.--31. " FTM3CLKSEL ,FlexTimer 3 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." bitfld.long 0x08 26.--27. " FTM1CLKSEL ,FlexTimer 1 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." bitfld.long 0x08 24.--25. " FTM0CLKSEL ,FlexTimer 0 external clock pin select" "FTM_CLK0,FTM_CLK1,FTM_CLK2,?..." newline bitfld.long 0x08 6. " FTM1ICH1SRC ,FTM1 channel 0 input capture source select" "FTM1_CH1,XOR" bitfld.long 0x08 4.--5. " FTM1ICH0SRC ,FTM1 Channel 0 input capture source select" "FTM1_CH0,CMP0,CMP1,?..." rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" bitfld.long 0x00 28.--31. " FAMILYID ,Kinetis family ID" ",,,,V series,?..." bitfld.long 0x00 24.--27. " SUBFAMID ,Kinetis sub-family ID" ",KVx2,,,KVx4,,KVx6,?..." bitfld.long 0x00 20.--23. " SERIESID ,Kinetis series ID" "K,L,,,,W,V,?..." newline bitfld.long 0x00 12.--15. " REVID ,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--11. " DIEID ,Device die number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,48-pin,64-pin,,,100-pin,?..." group.long 0x34++0x13 line.long 0x00 "SCGC4,System Clock Gating Control Register 4" sif !cpuis("MKV42*") bitfld.long 0x00 27. " EFLEXPWM3 ,EFlexPWM submodule 3 clock gate control" "Disabled,Enabled" bitfld.long 0x00 26. " EFLEXPWM2 ,EFlexPWM submodule 2 clock gate control" "Disabled,Enabled" bitfld.long 0x00 25. " EFLEXPWM1 ,EFlexPWM submodule 1 clock gate control" "Disabled,Enabled" newline bitfld.long 0x00 24. " EFLEXPWM0 ,EFlexPWM submodule 0 clock gate control" "Disabled,Enabled" endif newline bitfld.long 0x00 19. " CMP ,Comparators clock gate control" "Disabled,Enabled" bitfld.long 0x00 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x00 6. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled" bitfld.long 0x00 1. " EWM ,EWM clock gate control" "Disabled,Enabled" line.long 0x04 "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x04 28. " ADC ,ADC clock gate control" "Disabled,Enabled" bitfld.long 0x04 27. " AOI ,AOI clock gate control" "Disabled,Enabled" bitfld.long 0x04 26. " XBARB ,XBARB clock gate control" "Disabled,Enabled" newline bitfld.long 0x04 25. " XBARA ,XBARA clock gate control" "Disabled,Enabled" bitfld.long 0x04 21. " ENC ,This bit controls the clock gate to the ENC module" "Disabled,Enabled" bitfld.long 0x04 13. " PORTE ,Port E clock gate control" "Disabled,Enabled" newline bitfld.long 0x04 12. " PORTD ,Port D clock gate control" "Disabled,Enabled" bitfld.long 0x04 11. " PORTC ,Port C clock gate control" "Disabled,Enabled" bitfld.long 0x04 10. " PORTB ,Port B clock gate control" "Disabled,Enabled" newline bitfld.long 0x04 9. " PORTA ,Port A clock gate control" "Disabled,Enabled" bitfld.long 0x04 0. " LPTMR ,Low power timer access control" "Disabled,Enabled" line.long 0x08 "SCGC6,System Clock Gating Control Register 6" sif !cpuis("MKV42*") bitfld.long 0x08 31. " DAC0 ,DAC0 clock gate control" "Disabled,Enabled" newline endif bitfld.long 0x08 25. " FTM1 ,FTM1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 24. " FTM0 ,FTM0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 23. " PIT ,PIT clock gate control" "Disabled,Enabled" bitfld.long 0x08 22. " PDB0 ,PDB0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 18. " CRC ,CRC clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 17. " PDB1 ,PDB1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 12. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled" newline bitfld.long 0x08 6. " FTM3 ,FTM3 clock gate control" "Disabled,Enabled" sif !cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16") newline bitfld.long 0x08 5. " FLEXCAN1 ,FlexCAN1 clock gate control" "Disabled,Enabled" endif newline bitfld.long 0x08 4. " FLEXCAN0 ,FlexCAN0 clock gate control" "Disabled,Enabled" bitfld.long 0x08 1. " DMAMUX ,DMA mux clock gate control" "Disabled,Enabled" bitfld.long 0x08 0. " FTF ,Flash memory clock gate control" "Disabled,Enabled" line.long 0x0C "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x0C 8. " DMA ,DMA clock gate control" "Disabled,Enabled" line.long 0x10 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x10 28.--31. " OUTDIV1 ,Clock 1 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 24.--27. " OUTDIV2 ,Clock 2 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 16.--19. " OUTDIV4 ,Clock 4 output divider value" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" group.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,,,64kB,,128kB,,256kB,?..." bitfld.long 0x00 1. " FLASHDOZE ,Flash doze" "No,Yes" bitfld.long 0x00 0. " FLASHDIS ,Flash disable" "No,Yes" rgroup.long 0x50++0x13 line.long 0x00 "FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 1. " MAXADDR0 ,Max address block 0" line.long 0x04 "UIDH,Unique Identification Register High" line.long 0x08 "UIDMH,Unique Identification Register Mid-High" line.long 0x0C "UIDML,Unique Identification Register Mid Low" line.long 0x10 "UIDL,Unique Identification Register Low" group.long 0x68++0x0B line.long 0x00 "CLKDIV4,System Clock Divider Register 4" bitfld.long 0x00 28. " TRACEDIVEN ,Debug trace divider control" "Disabled,Enabled" bitfld.long 0x00 1.--3. " TRACEDIV ,Trace clock divider divisor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0. " TRACEFRAC ,Trace clock divider fraction" "1,2" line.long 0x04 "MISCTRL0,Miscellaneous Control Register 0" bitfld.long 0x04 18.--19. " DACTRIGSRC ,DAC0 hardware trigger input source" "XBARA[15],PDB0/PDB1,PDB0,PDB1" bitfld.long 0x04 16. " EWMINSRC ,EWM_IN source" "XBARA[58],EWM_IN" bitfld.long 0x04 14.--15. " CMPWIN3SRC ,CMP sample/window input 3 source" "XBARA[19],PDB0/PDB1,PDB0,PDB1" newline bitfld.long 0x04 12.--13. " CMPWIN2SRC ,CMP sample/window input 2 source" "XBARA[18],PDB0/PDB1,PDB0,PDB1" bitfld.long 0x04 10.--11. " CMPWIN1SRC ,CMP sample/window input 1 source" "XBARA[17],PDB0/PDB1,PDB0,PDB1" bitfld.long 0x04 8.--9. " CMPWIN0SRC ,CMP sample/window input 0 source" "XBARA[16],PDB0/PDB1,PDB0,PDB1" line.long 0x08 "MISCTRL2,Miscellaneous Control Register 2" bitfld.long 0x08 23. " SYNCCMP3SAMPLEWIN ,Synchronize XBARA's output for CMP3's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 22. " SYNCCMP2SAMPLEWIN ,Synchronize XBARA's output for CMP2's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 21. " SYNCCMP1SAMPLEWIN ,Synchronize XBARA's output for CMP1's sample/window input with flash/slow clock" "Disabled,Enabled" newline bitfld.long 0x08 20. " SYNCCMP0SAMPLEWIN ,Synchronize XBARA's output for CMP0's sample/window input with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 17. " SYNCEWMIN ,Synchronize XBARA's output for EWM's ewm_in with flash/slow clock" "Disabled,Enabled" bitfld.long 0x08 16. " SYNCDACHWTRIG ,Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock" "Disabled,Enabled" newline bitfld.long 0x08 13. " SYNCXBARBPITTRIG1 ,Synchronize XBARB's input PIT trigger 1 with fast clock" "Disabled,Enabled" bitfld.long 0x08 12. " SYNCXBARBPITTRIG0 ,Synchronize XBARB's input PIT trigger 0 with fast clock" "Disabled,Enabled" bitfld.long 0x08 11. " SYNCXBARAPITTRIG3 ,Synchronize XBARA's input PIT trigger 3 with fast clock" "Disabled,Enabled" newline bitfld.long 0x08 10. " SYNCXBARAPITTRIG2 ,Synchronize XBARA's input PIT trigger 2 with fast clock" "Disabled,Enabled" bitfld.long 0x08 9. " SYNCXBARAPITTRIG1 ,Synchronize XBARA's input PIT trigger 1 with fast clock" "Disabled,Enabled" bitfld.long 0x08 8. " SYNCXBARAPITTRIG0 ,Synchronize XBARA's input PIT trigger 0 with fast clock" "Disabled,Enabled" group.long 0x100++0x0B line.long 0x00 "WDOGC,WDOG Control Register" bitfld.long 0x00 1. " WDOGCLKS ,WDOG clock select" "Internal 1kHz,MCGIRCLK" line.long 0x04 "PWRC,Power Control Register" rbitfld.long 0x04 16. " SRPWROK ,Nanoedge PMC status" "Not ready,Ready" bitfld.long 0x04 9. " SRPWRRDY ,Nanoedge PMC POWER ready" "Not ready,Ready" bitfld.long 0x04 8. " SRPWRDETEN ,Nanoedge PMC POWER dectect enable" "Disabled,Enabled" newline bitfld.long 0x04 6.--7. " SR12STDBY ,Nanoedge regulator 1.2 V supply standby control" "Normal mode,Standby mode,Normal mode/protected,Standby mode/protected" bitfld.long 0x04 2.--3. " SR27STDBY ,Nanoedge regulator 2.7 V supply standby control" "Normal mode,Standby mode,Normal mode/protected,Standby mode/protected" bitfld.long 0x04 0.--1. " SRPDN ,Nanoedge regulator 2.7V and 1.2V supply powerdown control" "Normal mode,Powerdown mode,Normal mode/protected,Powerdown mode/protected" line.long 0x08 "ADCOPT,ADC Channel 6/7 Mux Control Register" rbitfld.long 0x08 25. " ADCIRCLK ,ADC clock status" "Peripheral,MCGIRCLK" bitfld.long 0x08 24. " ROSB ,Enable ADC low current mode" "Disabled,Enabled" bitfld.long 0x08 12.--14. " ADCBCH7SEL ,ADCB MUX1 selection for ADCB channel 7" "Channel A,Channel B,Channel C,Channel D,Channel E,Channel F,Channel G,?..." newline bitfld.long 0x08 8.--10. " ADCBCH6SEL ,ADCB MUX1 selection for ADCB channel 6" "Channel A,Channel B,Channel C,Channel D,Channel E,Channel F,Channel G,PMC 1V" bitfld.long 0x08 4.--6. " ADCACH7SEL ,ADCA MUX1 selection for ADCA channel 7" "Channel A,Channel B,Channel C,,Channel E,Channel F,Channel G,PMC 1V" bitfld.long 0x08 0.--2. " ADCACH6SEL ,ADCA MUX0 selection for ADCA channel 6" "Channel A,Channel B,Channel C,Channel D,Channel E,,Channel G,?..." width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "No reset,Reset" bitfld.byte 0x00 6. " PIN ,External reset pin" "No reset,Reset" bitfld.byte 0x00 5. " WDOG ,Watchdog" "No reset,Reset" newline bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "No reset,Reset" bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "No reset,Reset" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "No reset,Reset" newline bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "No reset,Reset" line.byte 0x01 "SRS1,System Reset Status Register 1" bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "No reset,Reset" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "No reset,Reset" bitfld.byte 0x01 2. " SW ,Software" "No reset,Reset" newline bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "No reset,Reset" group.byte 0x04++0x01 line.byte 0x00 "RPFC,Reset Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "Disabled,LPO clock" bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "Disabled,Bus clock,LPO clock,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.byte 0x08++0x01 line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "No reset,Reset" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "No reset,Reset" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog timeout" "No reset,Reset" newline eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "No reset,Reset" eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "No reset,Reset" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "No reset,Reset" newline eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "No reset,Reset" line.byte 0x01 "SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "No reset,Reset" eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "No reset,Reset" newline eventfld.byte 0x01 2. " SSW ,Sticky software setting of SYSRESETREQ bit" "No reset,Reset" eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "No reset,Reset" width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" bitfld.byte 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.byte 0x00 1. " AVLLS ,Allow very low leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "RUN,,VLPR,HSRUN" rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "STOP,,VLPS,,VLLSx,?..." if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) if (((per.b(ad:0x4007E000+0x02))&0x07)==0x00) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x02))&0x07)==0x02) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option in VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 3. " LPOPO ,LPO power option" "No,Yes" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,Stop Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "No,Yes" endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status Register" bitfld.byte 0x00 7. " PMSTAT[7] ,Current power mode is HSRUN" "No,Yes" bitfld.byte 0x00 6. " [6] ,Current power mode is VLLS" "No,Yes" bitfld.byte 0x00 4. " [4] ,Current power mode is VLPS" "No,Yes" bitfld.byte 0x00 3. " [3] ,Current power mode is VLPW" "No,Yes" newline bitfld.byte 0x00 2. " [2] ,Current power mode is VLPR" "No,Yes" bitfld.byte 0x00 1. " [1] ,Current power mode is STOP" "No,Yes" bitfld.byte 0x00 0. " [0] ,Current power mode is RUN" "No,Yes" width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 7. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration" bitfld.word 0x00 2. " ASC[2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration" bitfld.word 0x02 2. " AMC[2] ,Connection to the AXBS master input port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected" group.long 0x0C++0x07 line.long 0x00 "CR,Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority [processor/SRAM backdoor]" "Round robin,Special round robin,Fixed hi/low,Fixed low/hi" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority [processor/SRAM backdoor]" "Round robin,Special round robin,Fixed hi/low,Fixed low/hi" line.long 0x04 "ISCR,Interrupt Status And Control Register" bitfld.long 0x04 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x04 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x04 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" rbitfld.long 0x04 15. " FIDC ,FPU input denormal interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 12. " FIXC ,FPU inexact interrupt status" "No interrupt,Interrupt" newline rbitfld.long 0x04 11. " FUFC ,FPU underflow interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 10. " FOFC ,FPU overflow interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 9. " FDZC ,FPU divide-by-zero interrupt status" "No interrupt,Interrupt" rbitfld.long 0x04 8. " FIOC ,FPU invalid operation interrupt status" "No interrupt,Interrupt" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wake-up on interrupt" "No effect,CPOREQ cleared" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Not completed,Completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Cleared" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low,High,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Acknowledge" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low,Mid 1,Mid 2,High" line.byte 0x02 "REGSC,Regulator Status And Control Register" bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Disabled,Enabled" eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Normal run,Isolated/latched" rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run" newline bitfld.byte 0x02 1. " BGBDS ,Bandgap buffer drive select" "Low,High" bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" width 0x0B tree.end tree "LLWU (Low-Leakage Wakeup Unit)" base ad:0x4007C000 width 7. group.byte 0x00++0x05 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE[3] ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any change" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") bitfld.byte 0x00 0.--1. " [0] ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE[7] ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 4.--5. " [6] ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x01 2.--3. " [5] ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any change" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") newline bitfld.byte 0x01 0.--1. " [4] ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any change" endif line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") bitfld.byte 0x02 6.--7. " WUPE[11] ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any change" newline endif bitfld.byte 0x02 4.--5. " WUPE[10] ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 2.--3. " [9] ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x02 0.--1. " [8] ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE[15] ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 4.--5. " [14] ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 2.--3. " [13] ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x03 0.--1. " [12] ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x04 "PE5,LLWU Pin Enable 5 Register" bitfld.byte 0x04 6.--7. " WUPE[19] ,Wakeup pin enable for LLWU_P19" "Disabled,Rising edge,Falling edge,Any change" line.byte 0x05 "PE6,LLWU Pin Enable 6 Register" bitfld.byte 0x05 2.--3. " WUPE[21] ,Wakeup pin enable for LLWU_P21" "Disabled,Rising edge,Falling edge,Any change" bitfld.byte 0x05 0.--1. " [20] ,Wakeup pin enable for LLWU_P20" "Disabled,Rising edge,Falling edge,Any change" group.byte 0x08++0x03 line.byte 0x00 "ME,LLWU Module Enable Register" bitfld.byte 0x00 3. " WUME[3] ,Wakeup module enable for module 3" "Disabled,Enabled" newline bitfld.byte 0x00 2. " [2] ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x00 1. " [1] ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x00 0. " [0] ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x01 "PF1,LLWU Pin Flag 1 Register" eventfld.byte 0x01 7. " WUF[7] ,Wakeup flag for LLWU_P7" "Disabled,Enabled" eventfld.byte 0x01 6. " [6] ,Wakeup flag for LLWU_P6" "Disabled,Enabled" eventfld.byte 0x01 5. " [5] ,Wakeup flag for LLWU_P5" "Disabled,Enabled" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") eventfld.byte 0x01 4. " [4] ,Wakeup flag for LLWU_P4" "Disabled,Enabled" newline endif eventfld.byte 0x01 3. " [3] ,Wakeup Flag for LLWU_P3" "Disabled,Enabled" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") eventfld.byte 0x01 0. " [0] ,Wakeup flag for LLWU_P0" "Disabled,Enabled" endif line.byte 0x02 "PF2,LLWU Pin Flag 2 Register" eventfld.byte 0x02 7. " WUF[15] ,Wakeup flag for LLWU_P15" "Disabled,Enabled" eventfld.byte 0x02 6. " [14] ,Wakeup flag for LLWU_P14" "Disabled,Enabled" eventfld.byte 0x02 5. " [13] ,Wakeup flag for LLWU_P13" "Disabled,Enabled" eventfld.byte 0x02 4. " [12] ,Wakeup flag for LLWU_P12" "Disabled,Enabled" newline sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16") eventfld.byte 0x02 3. " [11] ,Wakeup flag for LLWU_P11" "Disabled,Enabled" newline endif eventfld.byte 0x02 2. " [10] ,Wakeup Flag for LLWU_P10" "Disabled,Enabled" eventfld.byte 0x02 1. " [9] ,Wakeup Flag for LLWU_P9" "Disabled,Enabled" eventfld.byte 0x02 0. " [8] ,Wakeup Flag for LLWU_P8" "Disabled,Enabled" line.byte 0x03 "PF3,LLWU Pin Flag 3 Register" eventfld.byte 0x03 5. " WUF[21] ,Wakeup flag for module 21" "Disabled,Enabled" eventfld.byte 0x03 4. " [20] ,Wakeup flag for module 20" "Disabled,Enabled" eventfld.byte 0x03 3. " [19] ,Wakeup flag for module 19" "Disabled,Enabled" newline rgroup.byte 0x0D++0x00 line.byte 0x00 "MF5,LLWU Module Flag 5 Register" bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag For module 3" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag For module 2" "Not a wakeup source,Wakeup source" newline bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag For module 1" "Not a wakeup source,Wakeup source" bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag For module 0" "Not a wakeup source,Wakeup source" group.byte 0x0E++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." else bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." endif line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." else bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15,,,,LLWU_P19,LLWU_P20,LLWU_P21,?..." endif width 0x0B tree.end tree "AIPS-Lite (Peripheral Bridge)" base ad:0x40000000 width 13. group.long 0x00++0x03 line.long 0x00 "AIPS0_MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master 0 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master 0 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master 0 privilege level" "Forced,Not forced" bitfld.long 0x00 26. " MTR1 ,Master 1 trusted for read" "Not trusted,Trusted" newline bitfld.long 0x00 25. " MTW1 ,Master 1 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master 1 privilege level" "Forced,Not forced" bitfld.long 0x00 22. " MTR2 ,Master 2 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master 2 trusted for writes" "Not trusted,Trusted" newline bitfld.long 0x00 20. " MPL2 ,Master 2 privilege level" "Forced,Not forced" sif !cpuis("MKV42F64VLF16")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") bitfld.long 0x00 18. " MTW3 ,Master 3 trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MPL3 ,Master 3 trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MTR3 ,Master 3 privilege level" "Forced,Not forced" endif newline group.long 0x20++0x03 line.long 0x00 "AIPS0_PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x24++0x03 line.long 0x00 "AIPS0_PACRB,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x28++0x03 line.long 0x00 "AIPS0_PACRC,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x2C++0x03 line.long 0x00 "AIPS0_PACRD,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x40++0x03 line.long 0x00 "AIPS0_PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x44++0x03 line.long 0x00 "AIPS0_PACRF,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x48++0x03 line.long 0x00 "AIPS0_PACRG,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x4C++0x03 line.long 0x00 "AIPS0_PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x50++0x03 line.long 0x00 "AIPS0_PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x54++0x03 line.long 0x00 "AIPS0_PACRJ,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x58++0x03 line.long 0x00 "AIPS0_PACRK,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x5C++0x03 line.long 0x00 "AIPS0_PACRL,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x60++0x03 line.long 0x00 "AIPS0_PACRM,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x64++0x03 line.long 0x00 "AIPS0_PACRN,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x68++0x03 line.long 0x00 "AIPS0_PACRO,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" group.long 0x6C++0x03 line.long 0x00 "AIPS0_PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 29. " WP0 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 28. " TP0 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 26. " SP1 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 25. " WP1 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 24. " TP1 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 22. " SP2 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 21. " WP2 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 20. " TP2 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 18. " SP3 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 17. " WP3 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 16. " TP3 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 14. " SP4 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 13. " WP4 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 12. " TP4 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 10. " SP5 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 9. " WP5 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 8. " TP5 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 6. " SP6 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 5. " WP6 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 4. " TP6 ,Trusted protect" "Unprotected,Protected" newline bitfld.long 0x00 2. " SP7 ,Supervisor protect" "Unprotected,Protected" bitfld.long 0x00 1. " WP7 ,Write protect" "Unprotected,Protected" bitfld.long 0x00 0. " TP7 ,Trusted protect" "Unprotected,Protected" width 0x0B tree.end tree "DMAMUX (Direct memory access multiplexer)" base ad:0x40021000 width 9. group.byte (0x00+0x0)++0x00 line.byte 0x00 "CHCFG0,Channel Configuration Register 0" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x1)++0x00 line.byte 0x00 "CHCFG1,Channel Configuration Register 1" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x2)++0x00 line.byte 0x00 "CHCFG2,Channel Configuration Register 2" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x3)++0x00 line.byte 0x00 "CHCFG3,Channel Configuration Register 3" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x4)++0x00 line.byte 0x00 "CHCFG4,Channel Configuration Register 4" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x5)++0x00 line.byte 0x00 "CHCFG5,Channel Configuration Register 5" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x6)++0x00 line.byte 0x00 "CHCFG6,Channel Configuration Register 6" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x7)++0x00 line.byte 0x00 "CHCFG7,Channel Configuration Register 7" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x8)++0x00 line.byte 0x00 "CHCFG8,Channel Configuration Register 8" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0x9)++0x00 line.byte 0x00 "CHCFG9,Channel Configuration Register 9" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xA)++0x00 line.byte 0x00 "CHCFG10,Channel Configuration Register 10" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xB)++0x00 line.byte 0x00 "CHCFG11,Channel Configuration Register 11" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xC)++0x00 line.byte 0x00 "CHCFG12,Channel Configuration Register 12" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xD)++0x00 line.byte 0x00 "CHCFG13,Channel Configuration Register 13" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xE)++0x00 line.byte 0x00 "CHCFG14,Channel Configuration Register 14" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif group.byte (0x00+0xF)++0x00 line.byte 0x00 "CHCFG15,Channel Configuration Register 15" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger enable" "Disabled,Enabled" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (slot)" "Disabled,,UART0 Receive,UART0 Transmit,UART1 Receive,UART1 Transmit,FlexPWM_WR0,FlexPWM_WR1,FlexPWM_WR2,FlexPWM_WR3,FlexPWMA_CP0,FlexPWMA_CP1,FlexPWMA_CP2,FlexPWMA_CP3,FlexCAN0,FlexCAN1,SPI0 Receive,SPI0 Transmit,XBARA_OUT0,XBARA_OUT1,XBARA_OUT2,XBARA_OUT3,I2C0,,FTM0 Ch0,FTM0 Ch1,FTM0 Ch2,FTM0 Ch3,FTM0 Ch4,FTM0 Ch5,FTM0 Ch6,FTM0 Ch7,FTM1 Ch0,FTM1 Ch1,CMP3,,FTM3 Ch0,FTM3 Ch1,FTM3 Ch2,FTM3 Ch3,ADCA Scan Complete,ADCB Scan Complete,CMP0,CMP1,CMP2,DAC0,,PDB1,PDB0,Control module Port A,Control module Port B,Control module Port C,Control module Port D,Control module Port E,FTM3 Ch4,FTM3 Ch5,FTM3 Ch6,FTM3 Ch7,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled,DMAX MUX always enabled" endif width 0x0B tree.end tree "eDMA (Direct Memory Access Controller)" base ad:0x40008000 width 10. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing channel" newline endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not cancelled,Cancelled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Disabled,Enabled" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Disabled,Enabled" endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" endif newline bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Not occurred,Occurred" bitfld.long 0x00 16. " ECX ,Transfer cancelled" "Not cancelled,Cancelled" sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.long 0x00 8.--10. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or cancelled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" newline bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" newline bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " ERQ[7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " ERQ[3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EEI[7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EEI[3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" endif wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x00 0.--2. " CEEI ,Clear enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x01 0.--2. " SEEI ,Set enable error interrupt [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ only,ALL bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x02 0.--2. " CERQ ,Clear enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SERQ only only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x03 0.--2. " SERQ ,Set enable request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x03 0.--1. " SERQ ,Set enable request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x03 0.--4. " SERQ ,Set enable request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x03 0.--3. " SERQ ,Set enable request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x04 6. " CADN ,Clear all DONE bits" "CDNE only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x04 0.--2. " CDNE ,Clear DONE bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x04 0.--1. " CDNE ,Clear DONE bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") newline bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x04 0.--3. " CDNE ,Clear DONE bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x05 6. " SAST ,Set All START bits" "SSRT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x05 0.--2. " SSRT ,Set START bits [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x05 0.--1. " SSRT ,Set START bits [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x05 0.--4. " SSRT ,Set START bits [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x05 0.--3. " SSRT ,Set START bits [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x06 0.--2. " CERR ,Clear error indicator [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator [1:0]" "0,1,2,3" elif cpuis("MKV58F1M0V??24")||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CINT only,All bits" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.byte 0x07 0.--2. " CINT ,Clear interrupt request [2:0]" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") newline bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request [1:0]" "0,1,2,3" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) newline bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request [4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " INT[7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " INT[3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "Not requested,Requested" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "Not requested,Requested" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "Not requested,Requested" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "Not requested,Requested" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "Not requested,Requested" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "Not requested,Requested" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "Not requested,Requested" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "Not requested,Requested" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "Not requested,Requested" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "Not requested,Requested" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "Not requested,Requested" eventfld.long 0x00 20. " INT20 ,Interrupt request 20" "Not requested,Requested" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "Not requested,Requested" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "Not requested,Requested" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "Not requested,Requested" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "Not requested,Requested" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " INT[15] ,Interrupt request 15" "Not requested,Requested" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "Not requested,Requested" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "Not requested,Requested" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "Not requested,Requested" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "Not requested,Requested" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "Not requested,Requested" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "Not requested,Requested" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "Not requested,Requested" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "Not requested,Requested" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "Not requested,Requested" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "Not requested,Requested" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "Not requested,Requested" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "Not requested,Requested" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "Not requested,Requested" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "Not requested,Requested" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "Not requested,Requested" endif group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") eventfld.long 0x00 7. " ERR[7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") eventfld.long 0x00 3. " ERR[3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") eventfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" endif rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " HRS[31] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " HRS[7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " HRS[3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " HRS[15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" endif group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 7. " EDREQ[7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif tree.end width 10. tree "DMA Channel Priority Registers" sif (cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24")) group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 Current Group Priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" elif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--2. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,Highest" elif cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV31F128VLH10P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" elif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV42F128VLL16")||cpuis("MKV46F256VLH16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif !cpuis("MKV42*")&&!cpuis("MKV44*")&&!cpuis("MKV46*")&&!cpuis("MKW2?D*")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV31F512VLH12*")&&!cpuis("MKV31F512VLL12P") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 Current Group Priority" "0,1,2,3" newline endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif tree.end base ad:0x40009000 width 23. tree "Transfer Control Descriptor Registers" sif cpuis("MKV40F256VLL15")||cpuis("MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV10Z*")||cpuis("MKV30F*")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "TCD0_SADDR,TCD Source Address" group.word (0x0+0x04)++0x03 line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD0_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0_DADDR,TCD Destination Address" group.word (0x0+0x14)++0x01 line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x0+0x18)++0x03 line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x0+0x1C)++0x01 line.word 0x00 "TCD0_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "TCD0_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 1" group.long 0x20++0x03 line.long 0x00 "TCD1_SADDR,TCD Source Address" group.word (0x20+0x04)++0x03 line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD1_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1_DADDR,TCD Destination Address" group.word (0x20+0x14)++0x01 line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x20+0x18)++0x03 line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x20+0x1C)++0x01 line.word 0x00 "TCD1_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "TCD1_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 2" group.long 0x40++0x03 line.long 0x00 "TCD2_SADDR,TCD Source Address" group.word (0x40+0x04)++0x03 line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD2_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2_DADDR,TCD Destination Address" group.word (0x40+0x14)++0x01 line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x40+0x18)++0x03 line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x40+0x1C)++0x01 line.word 0x00 "TCD2_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "TCD2_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 3" group.long 0x60++0x03 line.long 0x00 "TCD3_SADDR,TCD Source Address" group.word (0x60+0x04)++0x03 line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD3_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3_DADDR,TCD Destination Address" group.word (0x60+0x14)++0x01 line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x60+0x18)++0x03 line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x60+0x1C)++0x01 line.word 0x00 "TCD3_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "TCD3_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 4" group.long 0x80++0x03 line.long 0x00 "TCD4_SADDR,TCD Source Address" group.word (0x80+0x04)++0x03 line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD4_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD4_DADDR,TCD Destination Address" group.word (0x80+0x14)++0x01 line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x80+0x18)++0x03 line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x80+0x1C)++0x01 line.word 0x00 "TCD4_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "TCD4_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 5" group.long 0xA0++0x03 line.long 0x00 "TCD5_SADDR,TCD Source Address" group.word (0xA0+0x04)++0x03 line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD5_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD5_DADDR,TCD Destination Address" group.word (0xA0+0x14)++0x01 line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xA0+0x18)++0x03 line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xA0+0x1C)++0x01 line.word 0x00 "TCD5_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "TCD5_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 6" group.long 0xC0++0x03 line.long 0x00 "TCD6_SADDR,TCD Source Address" group.word (0xC0+0x04)++0x03 line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD6_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD6_DADDR,TCD Destination Address" group.word (0xC0+0x14)++0x01 line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xC0+0x18)++0x03 line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xC0+0x1C)++0x01 line.word 0x00 "TCD6_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "TCD6_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 7" group.long 0xE0++0x03 line.long 0x00 "TCD7_SADDR,TCD Source Address" group.word (0xE0+0x04)++0x03 line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD7_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD7_DADDR,TCD Destination Address" group.word (0xE0+0x14)++0x01 line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0xE0+0x18)++0x03 line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0xE0+0x1C)++0x01 line.word 0x00 "TCD7_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "TCD7_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 8" group.long 0x100++0x03 line.long 0x00 "TCD8_SADDR,TCD Source Address" group.word (0x100+0x04)++0x03 line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD8_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x100+0x08))&0xC0000000)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x100+0x08)++0x03 line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x100+0x0C)++0x07 line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD8_DADDR,TCD Destination Address" group.word (0x100+0x14)++0x01 line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x100+0x16))&0x8000)==0x00) group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x100+0x16)++0x01 line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x100+0x18)++0x03 line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x100+0x1C)++0x01 line.word 0x00 "TCD8_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x100+0x1E))&0x8000)==0x00) group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x100+0x1E)++0x01 line.word 0x00 "TCD8_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 9" group.long 0x120++0x03 line.long 0x00 "TCD9_SADDR,TCD Source Address" group.word (0x120+0x04)++0x03 line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD9_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x120+0x08))&0xC0000000)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x120+0x08)++0x03 line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x120+0x0C)++0x07 line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD9_DADDR,TCD Destination Address" group.word (0x120+0x14)++0x01 line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x120+0x16))&0x8000)==0x00) group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x120+0x16)++0x01 line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x120+0x18)++0x03 line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x120+0x1C)++0x01 line.word 0x00 "TCD9_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x120+0x1E))&0x8000)==0x00) group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x120+0x1E)++0x01 line.word 0x00 "TCD9_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 10" group.long 0x140++0x03 line.long 0x00 "TCD10_SADDR,TCD Source Address" group.word (0x140+0x04)++0x03 line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x140+0x08))&0xC0000000)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x140+0x0C)++0x07 line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD10_DADDR,TCD Destination Address" group.word (0x140+0x14)++0x01 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x140+0x16))&0x8000)==0x00) group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x140+0x18)++0x03 line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x140+0x1E))&0x8000)==0x00) group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 11" group.long 0x160++0x03 line.long 0x00 "TCD11_SADDR,TCD Source Address" group.word (0x160+0x04)++0x03 line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x160+0x08))&0xC0000000)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x160+0x0C)++0x07 line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD11_DADDR,TCD Destination Address" group.word (0x160+0x14)++0x01 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x160+0x16))&0x8000)==0x00) group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x160+0x18)++0x03 line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x160+0x1E))&0x8000)==0x00) group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 12" group.long 0x180++0x03 line.long 0x00 "TCD12_SADDR,TCD Source Address" group.word (0x180+0x04)++0x03 line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x180+0x08))&0xC0000000)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x180+0x0C)++0x07 line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD12_DADDR,TCD Destination Address" group.word (0x180+0x14)++0x01 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x180+0x16))&0x8000)==0x00) group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x180+0x18)++0x03 line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x180+0x1E))&0x8000)==0x00) group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 13" group.long 0x1A0++0x03 line.long 0x00 "TCD13_SADDR,TCD Source Address" group.word (0x1A0+0x04)++0x03 line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1A0+0x08))&0xC0000000)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1A0+0x0C)++0x07 line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD13_DADDR,TCD Destination Address" group.word (0x1A0+0x14)++0x01 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1A0+0x16))&0x8000)==0x00) group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1A0+0x18)++0x03 line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00) group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 14" group.long 0x1C0++0x03 line.long 0x00 "TCD14_SADDR,TCD Source Address" group.word (0x1C0+0x04)++0x03 line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1C0+0x08))&0xC0000000)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1C0+0x0C)++0x07 line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD14_DADDR,TCD Destination Address" group.word (0x1C0+0x14)++0x01 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1C0+0x16))&0x8000)==0x00) group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1C0+0x18)++0x03 line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00) group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end tree "Channel 15" group.long 0x1E0++0x03 line.long 0x00 "TCD15_SADDR,TCD Source Address" group.word (0x1E0+0x04)++0x03 line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1E0+0x08))&0xC0000000)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,Sign extended offset applied to the source/Destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1E0+0x0C)++0x07 line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD15_DADDR,TCD Destination Address" group.word (0x1E0+0x14)++0x01 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset" if (((per.l(ad:0x40009000+0x1E0+0x16))&0x8000)==0x00) group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") newline bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") newline bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif ((cpuis("MKV58F1M0V??24"))||(cpuis("MKV58F512V??24"))||(cpuis("MKV56F1M0V??24"))||(cpuis("MKV58F512??24"))) newline bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif group.long (0x1E0+0x18)++0x03 line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" group.word (0x1E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,Stalls for 4 cycles,Stalls for 8 cycles" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 8.--10. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7" newline elif cpuis("MKV10Z*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline elif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" endif newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.l(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00) group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Current Minor Loop Link(Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.word 0x00 9.--11. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7" elif cpuis("MKV10Z*")||cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKV31F128VLH10P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" elif (cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24"))||cpuis("MKV58F512??24") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif tree.end endif tree.end width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Clock source select" "LPO_CLK[0],LPO_CLK[1],LPO_CLK[2],LPO_CLK[3]" endif sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,Allows the WDOG functional test mode to be disabled permanently" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested when the watchdog is in the byte test mode" "0,1,2,3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick,Byte" newline bitfld.word 0x00 10. " TESTWDOG ,Puts the watchdog in the functional test mode" "Disabled,Enabled" bitfld.word 0x00 7. " WAITEN ,Enables or disables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables or disables WDOG in stop mode" "Disabled,Enabled" newline bitfld.word 0x00 5. " DBGEN ,Enables or disables WDOG in debug mode" "Disabled,Enabled" bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" newline bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables or disables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F128VLH10P") eventfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" else bitfld.word 0x02 15. " INT_FLG ,Interrupt flag" "No interrupt,Interrupt" endif line.word 0x04 "TOVALH,Watchdog Time-Out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-Out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree.open "XBAR (Inter-Peripheral Crossbar Switch)" tree "XBARA (Inter-Peripheral Crossbar Switch A)" base ad:0x40059000 width 7. group.word 0x0++0x01 line.word 0x00 "SEL0,Crossbar A Select Register 0" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL1 ,XBARA_OUT1 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL0 ,XBARA_OUT0 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL1 ,XBARA_OUT1 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL0 ,XBARA_OUT0 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x2++0x01 line.word 0x00 "SEL1,Crossbar A Select Register 1" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL3 ,XBARA_OUT3 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL2 ,XBARA_OUT2 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL3 ,XBARA_OUT3 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL2 ,XBARA_OUT2 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x4++0x01 line.word 0x00 "SEL2,Crossbar A Select Register 2" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL5 ,XBARA_OUT5 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL4 ,XBARA_OUT4 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL5 ,XBARA_OUT5 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL4 ,XBARA_OUT4 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x6++0x01 line.word 0x00 "SEL3,Crossbar A Select Register 3" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL7 ,XBARA_OUT7 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL6 ,XBARA_OUT6 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL7 ,XBARA_OUT7 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL6 ,XBARA_OUT6 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x8++0x01 line.word 0x00 "SEL4,Crossbar A Select Register 4" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL9 ,XBARA_OUT9 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL8 ,XBARA_OUT8 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL9 ,XBARA_OUT9 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL8 ,XBARA_OUT8 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0xA++0x01 line.word 0x00 "SEL5,Crossbar A Select Register 5" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL11 ,XBARA_OUT11 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL10 ,XBARA_OUT10 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL11 ,XBARA_OUT11 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL10 ,XBARA_OUT10 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0xC++0x01 line.word 0x00 "SEL6,Crossbar A Select Register 6" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL13 ,XBARA_OUT13 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL12 ,XBARA_OUT12 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL13 ,XBARA_OUT13 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL12 ,XBARA_OUT12 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0xE++0x01 line.word 0x00 "SEL7,Crossbar A Select Register 7" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL15 ,XBARA_OUT15 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL14 ,XBARA_OUT14 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL15 ,XBARA_OUT15 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL14 ,XBARA_OUT14 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x10++0x01 line.word 0x00 "SEL8,Crossbar A Select Register 8" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL17 ,XBARA_OUT17 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL16 ,XBARA_OUT16 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL17 ,XBARA_OUT17 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL16 ,XBARA_OUT16 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x12++0x01 line.word 0x00 "SEL9,Crossbar A Select Register 9" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL19 ,XBARA_OUT19 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL18 ,XBARA_OUT18 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL19 ,XBARA_OUT19 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL18 ,XBARA_OUT18 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x14++0x01 line.word 0x00 "SEL10,Crossbar A Select Register 10" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL21 ,XBARA_OUT21 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL20 ,XBARA_OUT20 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL21 ,XBARA_OUT21 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL20 ,XBARA_OUT20 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x16++0x01 line.word 0x00 "SEL11,Crossbar A Select Register 11" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL23 ,XBARA_OUT23 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL22 ,XBARA_OUT22 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL23 ,XBARA_OUT23 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL22 ,XBARA_OUT22 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x18++0x01 line.word 0x00 "SEL12,Crossbar A Select Register 12" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL25 ,XBARA_OUT25 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL24 ,XBARA_OUT24 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL25 ,XBARA_OUT25 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL24 ,XBARA_OUT24 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x1A++0x01 line.word 0x00 "SEL13,Crossbar A Select Register 13" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL27 ,XBARA_OUT27 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL26 ,XBARA_OUT26 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL27 ,XBARA_OUT27 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL26 ,XBARA_OUT26 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x1C++0x01 line.word 0x00 "SEL14,Crossbar A Select Register 14" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL29 ,XBARA_OUT29 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL29 ,XBARA_OUT29 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL28 ,XBARA_OUT28 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x1E++0x01 line.word 0x00 "SEL15,Crossbar A Select Register 15" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL31 ,XBARA_OUT31 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL31 ,XBARA_OUT31 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL30 ,XBARA_OUT30 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x20++0x01 line.word 0x00 "SEL16,Crossbar A Select Register 16" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL33 ,XBARA_OUT33 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL33 ,XBARA_OUT33 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL32 ,XBARA_OUT32 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x22++0x01 line.word 0x00 "SEL17,Crossbar A Select Register 17" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL35 ,XBARA_OUT35 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL35 ,XBARA_OUT35 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL34 ,XBARA_OUT34 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x24++0x01 line.word 0x00 "SEL18,Crossbar A Select Register 18" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL37 ,XBARA_OUT37 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL36 ,XBARA_OUT36 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL37 ,XBARA_OUT37 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL36 ,XBARA_OUT36 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x26++0x01 line.word 0x00 "SEL19,Crossbar A Select Register 19" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL39 ,XBARA_OUT39 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL38 ,XBARA_OUT38 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL39 ,XBARA_OUT39 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL38 ,XBARA_OUT38 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x28++0x01 line.word 0x00 "SEL20,Crossbar A Select Register 20" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL41 ,XBARA_OUT41 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL40 ,XBARA_OUT40 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL41 ,XBARA_OUT41 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL40 ,XBARA_OUT40 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x2A++0x01 line.word 0x00 "SEL21,Crossbar A Select Register 21" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL43 ,XBARA_OUT43 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL42 ,XBARA_OUT42 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL43 ,XBARA_OUT43 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL42 ,XBARA_OUT42 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x2C++0x01 line.word 0x00 "SEL22,Crossbar A Select Register 22" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL45 ,XBARA_OUT45 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL44 ,XBARA_OUT44 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL45 ,XBARA_OUT45 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL44 ,XBARA_OUT44 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x2E++0x01 line.word 0x00 "SEL23,Crossbar A Select Register 23" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL47 ,XBARA_OUT47 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL46 ,XBARA_OUT46 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL47 ,XBARA_OUT47 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL46 ,XBARA_OUT46 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x30++0x01 line.word 0x00 "SEL24,Crossbar A Select Register 24" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL49 ,XBARA_OUT49 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL48 ,XBARA_OUT48 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL49 ,XBARA_OUT49 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL48 ,XBARA_OUT48 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x32++0x01 line.word 0x00 "SEL25,Crossbar A Select Register 25" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL51 ,XBARA_OUT51 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL50 ,XBARA_OUT50 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL51 ,XBARA_OUT51 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL50 ,XBARA_OUT50 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x34++0x01 line.word 0x00 "SEL26,Crossbar A Select Register 26" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL53 ,XBARA_OUT53 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL52 ,XBARA_OUT52 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL53 ,XBARA_OUT53 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL52 ,XBARA_OUT52 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x36++0x01 line.word 0x00 "SEL27,Crossbar A Select Register 27" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL55 ,XBARA_OUT55 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL54 ,XBARA_OUT54 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL55 ,XBARA_OUT55 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL54 ,XBARA_OUT54 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x38++0x01 line.word 0x00 "SEL28,Crossbar A Select Register 28" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 8.--13. " SEL57 ,XBARA_OUT57 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." bitfld.word 0x00 0.--5. " SEL56 ,XBARA_OUT56 input selection" "DMAMUX18,DMAMUX19,DMAMUX20,DMAMUX21,XB_OUT4,XB_OUT5,XB_OUT6,XB_OUT7,XB_OUT8,XB_OUT9,XB_OUT10,XB_OUT11,ADCA_TRIG,ADCB_TRIG,,DAC0_12B_SYNC,CMP0,CMP1,CMP2,CMP3,PWMA0_EXTA,PWMA1_EXTA,PWMA2_EXTA,PWMA3_EXTA,PWMA0_EXT_SYNC,PWMA1_EXT_SYNC,PWMA2_EXT_SYNC,PWMA3_EXT_SYNC,PWMA_EXT_CLK,PWMA_FAULT0,PWMA_FAULT1,PWMA_FAULT2,PWMA_FAULT3,PWMA_FORCE,FTM0_TRIG2,FTM1_TRIG2,,FTM3_TRIG2,PDB0_IN_CH_1100,,,PDB1_IN_CH_1100,FTM1,,ENC_PHA,ENC_PHB,ENC_INDEX,ENC_HOME,ENC_CAP/Trigger,FTM0_FAULT3,FTM1_FAULT1,,FTM3_FAULT3,,,,,,EWM_IN,?..." else bitfld.word 0x00 8.--12. " SEL57 ,XBARA_OUT57 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" bitfld.word 0x00 0.--4. " SEL56 ,XBARA_OUT56 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif group.word 0x3A++0x01 line.word 0x00 "SEL29,Crossbar A Select Register 29" sif cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.word 0x00 0.--5. " SEL58 ,XBARA_OUT58 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INIT,FTM3_CH_allTRIG,FTM3_INIT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT,,ADCA scan comp.,,ADCB scan comp,FTM1_allTRIG,FTM1_INIT,DMA CH0_done,DMA CH1_done,DMA CH6_done,DMA CH7_done,PIT CH0,PIT CH1,,ENC_CMP/POS_MATCH,AND_OR_INVERT_0,AND_OR_INVERT_1,AND_OR_INVERT_2,AND_OR_INVERT_3,PIT CH2,PIT CH3,?..." else bitfld.word 0x00 0.--4. " SEL58 ,XBARA_OUT58 input selection" "VSS,VDD,XB_IN2,XB_IN3,XB_IN4,XB_IN5,XB_IN6,XB_IN7,XB_IN8,XB_IN9,XB_IN10,XB_IN11,CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0,PWMA0_TRG1,PWMA1_TRG0,PWMA1_TRG1,PWMA2_TRG0,PWMA2_TRG1,PWMA3_TRG0,PWMA3_TRG1,,PDB0_OUT,,PDB1_OUT" endif newline group.word 0x3C++0x03 line.word 0x00 "CTRL0,Crossbar A Control Register 0" eventfld.word 0x00 12. " STS1 ,Edge detection status for XBAR_OUT1" "Not detected,Detected" bitfld.word 0x00 10.--11. " EDGE1 ,Active edge for edge detection on XBAR_OUT1" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x00 9. " IEN1 ,Interrupt enable for XBAR_OUT1" "Disabled,Enabled" bitfld.word 0x00 8. " DEN1 ,DMA enable for XBAR_OUT1" "Disabled,Enabled" newline eventfld.word 0x00 4. " STS0 ,Edge detection status for XBAR_OUT0" "Not detected,Detected" bitfld.word 0x00 2.--3. " EDGE0 ,Active edge for edge detection on XBAR_OUT0" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x00 1. " IEN0 ,Interrupt enable for XBAR_OUT0" "Disabled,Enabled" bitfld.word 0x00 0. " DEN0 ,DMA enable for XBAR_OUT0" "Disabled,Enabled" line.word 0x02 "CTRL1,Crossbar A Control Register 1" eventfld.word 0x02 12. " STS3 ,Edge detection status for XBAR_OUT3" "Not detected,Detected" bitfld.word 0x02 10.--11. " EDGE3 ,Active edge for edge detection on XBAR_OUT3" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x02 9. " IEN3 ,Interrupt enable for XBAR_OUT3" "Disabled,Enabled" bitfld.word 0x02 8. " DEN3 ,DMA enable for XBAR_OUT3" "Disabled,Enabled" newline eventfld.word 0x02 4. " STS2 ,Edge detection status for XBAR_OUT2" "Not detected,Detected" bitfld.word 0x02 2.--3. " EDGE2 ,Active edge for edge detection on XBAR_OUT2" "Never,Rising edge,Falling edge,Both edges" bitfld.word 0x02 1. " IEN2 ,Interrupt enable for XBAR_OUT2" "Disabled,Enabled" bitfld.word 0x02 0. " DEN2 ,DMA enable for XBAR_OUT2" "Disabled,Enabled" width 0x0B tree.end tree "XBARB (Inter-Peripheral Crossbar Switch B)" base ad:0x4005A000 width 7. group.word 0x00++0x0F line.word 0x00 "SEL0,Crossbar B Select Register 0" bitfld.word 0x00 8.--12. " SEL1 ,XBARB_OUT1 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x00 0.--4. " SEL0 ,XBARB_OUT0 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x02 "SEL1,Crossbar B Select Register 1" bitfld.word 0x02 8.--12. " SEL3 ,XBARB_OUT3 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x02 0.--4. " SEL2 ,XBARB_OUT2 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x04 "SEL2,Crossbar B Select Register 2" bitfld.word 0x04 8.--12. " SEL5 ,XBARB_OUT5 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x04 0.--4. " SEL4 ,XBARB_OUT4 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x06 "SEL3,Crossbar B Select Register 3" bitfld.word 0x06 8.--12. " SEL7 ,XBARB_OUT7 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x06 0.--4. " SEL6 ,XBARB_OUT6 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x08 "SEL4,Crossbar B Select Register 4" bitfld.word 0x08 8.--12. " SEL9 ,XBARB_OUT9 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x08 0.--4. " SEL8 ,XBARB_OUT8 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x0A "SEL5,Crossbar B Select Register 5" bitfld.word 0x0A 8.--12. " SEL11 ,XBARB_OUT11 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x0A 0.--4. " SEL10 ,XBARB_OUT10 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x0C "SEL6,Crossbar B Select Register 6" bitfld.word 0x0C 8.--12. " SEL13 ,XBARB_OUT13 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x0C 0.--4. " SEL12 ,XBARB_OUT12 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." line.word 0x0E "SEL7,Crossbar B Select Register 7" bitfld.word 0x0E 8.--12. " SEL15 ,XBARB_OUT15 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." bitfld.word 0x0E 0.--4. " SEL14 ,XBARB_OUT14 input selection" "CMP0_OUT,CMP1_OUT,CMP2_OUT,CMP3_OUT,FTM0_CH_allTRIG,FTM0_INT,FTM3_CH_allTRIG,FTM3_INT,PWMA0_TRG0/PWMA0_TRG1,PWMA1_TRG0/PWMA1_TRG1,PWMA2_TRG0/PWMA2_TRG1,PWMA3_TRG0/PWMA3_TRG1,PDB0_OUT,ADCA Scan complete,XB_IN2,XB_IN3,FTM1_allTRIG,FTM1_INT,DMA ch0_done,DMA ch1_done,XB_IN10,XB_IN11,DMA ch6_done,DMA ch7_done,PIT ch0,PIT ch1,PDB1_OUT,ADCB Scan complete,?..." width 0x0B tree.end tree.end tree "AOI (Crossbar AND/OR/INVERT)" base ad:0x4005B000 width 10. group.word 0x00++0x0F line.word 0x00 "BFCRT010,Boolean Function Term 0 And 1 Configuration Register For EVENT0" bitfld.word 0x00 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x00 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x00 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x02 "BFCRT230,Boolean Function Term 2 And 3 Configuration Register For EVENT0" bitfld.word 0x02 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x02 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x02 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x04 "BFCRT011,Boolean Function Term 0 And 1 Configuration Register For EVENT1" bitfld.word 0x04 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x04 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x04 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x06 "BFCRT231,Boolean Function Term 2 And 3 Configuration Register For EVENT1" bitfld.word 0x06 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x06 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x06 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x08 "BFCRT012,Boolean Function Term 0 And 1 Configuration Register For EVENT2" bitfld.word 0x08 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x08 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x08 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0A "BFCRT232,Boolean Function Term 2 And 3 Configuration Register For EVENT2" bitfld.word 0x0A 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0A 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0A 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0C "BFCRT013,Boolean Function Term 0 And 1 Configuration Register For EVENT3" bitfld.word 0x0C 14.--15. " PT0_AC ,Product term 0 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 12.--13. " PT0_BC ,Product term 0 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 10.--11. " PT0_CC ,Product term 0 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 8.--9. " PT0_DC ,Product term 0 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0C 6.--7. " PT1_AC ,Product term 1 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 4.--5. " PT1_BC ,Product term 1 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 2.--3. " PT1_CC ,Product term 1 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0C 0.--1. " PT1_DC ,Product term 1 - D input configuration" "Force 0,Pass,Complement,Force 1" line.word 0x0E "BFCRT233,Boolean Function Term 2 And 3 Configuration Register For EVENT3" bitfld.word 0x0E 14.--15. " PT2_AC ,Product term 2 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 12.--13. " PT2_BC ,Product term 2 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 10.--11. " PT2_CC ,Product term 2 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 8.--9. " PT2_DC ,Product term 2 - D input configuration" "Force 0,Pass,Complement,Force 1" newline bitfld.word 0x0E 6.--7. " PT3_AC ,Product term 3 - A input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 4.--5. " PT3_BC ,Product term 3 - B input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 2.--3. " PT3_CC ,Product term 3 - C input configuration" "Force 0,Pass,Complement,Force 1" bitfld.word 0x0E 0.--1. " PT3_DC ,Product term 3 - D input configuration" "Force 0,Pass,Complement,Force 1" width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40065000 width 5. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x02++0x00 line.byte 0x00 "DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. sif (cpuis("MKV10Z*"))||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif elif cpuis("MKV31F256VLH12R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12?")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)==0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" elif (((per.b(ad:0x40064000+0x01))&0x30)!=0x00)&&(((per.b(ad:0x40064000+0x05))&0x40)==0x00) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out PLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif else if (((per.b(ad:0x40064000+0x01))&0x30)==0x00||((per.b(ad:0x40064000+0x0C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL,Internal ref clk,External ref clk,?..." bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" newline bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" else bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increase,Decrease" bitfld.byte 0x00 4.--5. " RANGE0 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" newline bitfld.byte 0x00 3. " HGO0 ,High gain oscillator select" "Low-power,High-gain" bitfld.byte 0x00 2. " EREFS0 ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "Enabled,Disabled" newline bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" endif line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x03))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20-25 mHz,24 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "40-50 mHz,48 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60-75 mHz,72 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80-100 mHz,96 mHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" newline bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Increase,Decrease" endif sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV10Z*") group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" elif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN0 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN0 ,PLL stop enable" "Disabled,Enabled" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") newline bitfld.byte 0x00 0.--4. " PRDIV0 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." newline endif newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV0 ,VCO 0 divider" "24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55" else group.byte 0x04++0x01 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" newline line.byte 0x01 "C6,MCG Control 6 Register" bitfld.byte 0x01 7. " LOLIE0 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x01 5. " CME0 ,Clock monitor enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--4. " VDIV ,VCO divider" "16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif cpuis("MKV10Z*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" else bitfld.byte 0x00 7. " LOLS0 ,Loss of lock status" "Not locked,Locked" bitfld.byte 0x00 6. " LOCK0 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Output FLL,Internal ref,External ref,Output PLL" bitfld.byte 0x00 1. " OSCINIT0 ,OSC initialization" "Not completed,Completed" newline bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" endif group.byte 0x08++0x00 sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" eventfld.byte 0x00 0. " LOCS0 ,OSC0 loss of clock status" "Not occurred,Occurred" else line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4mHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" rbitfld.byte 0x00 0. " LOCS ,Loss of clock status" "Not occurred,Occurred" endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLL12P") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32khz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" newline hgroup.byte 0x11++0x00 hide.long 0x00 "C12,MCG Control 12 Register" hgroup.byte 0x12++0x00 hide.long 0x00 "S2,MCG Status 2 Register" hgroup.byte 0x13++0x00 hide.long 0x00 "T3,MCG Test 3 Register" elif (!cpuis("MKV10Z*"))&&(!cpuis("MKV5*"))&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16R") group.byte 0x0C++0x01 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32 kHz RTC,OSCCLK1,?..." line.byte 0x01 "C8,MCG Control 8 Register" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else rbitfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P") bitfld.byte 0x01 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x01 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" eventfld.byte 0x01 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif cpuis("MK65FN2M0CAF18")||cpuis("MK65FN2M0VMF18")||cpuis("MK65FX1M0CAF18")||cpuis("MK65FX1M0VMF18")||cpuis("MK66FN2M0VLQ18")||cpuis("MK66FN2M0VMD18")||cpuis("MK66FX1M0VLQ18")||cpuis("MK66FX1M0VMD18") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Disabled,Enabled" rbitfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" endif else sif cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" elif !cpuis("MKV10Z*")&&!cpuis("MKV11Z*") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline rbitfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif endif width 0x0B tree.end tree "FMC (Flash Memory Controller)" base ad:0x4001F000 width 8. group.long 0x00++0x07 line.long 0x00 "PFAPR,Flash Access Protection Register" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MKV31F*")||cpuis("MKV30F*") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" newline bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" else bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" newline bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" endif line.long 0x04 "PFB0CR,Flash Bank 0 Control Register" rbitfld.long 0x04 28.--31. " B0RWSC ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 27. " CLCK_WAY3 ,Cache lock way 3" "Not locked,Locked" newline bitfld.long 0x04 26. " CLCK_WAY2 ,Cache lock way 2" "Not locked,Locked" bitfld.long 0x04 25. " CLCK_WAY1 ,Cache lock way 1" "Not locked,Locked" newline bitfld.long 0x04 24. " CLCK_WAY0 ,Cache lock way 0" "Not locked,Locked" bitfld.long 0x04 23. " CINV_WAY3 ,Cache invalidate way 3" "No effect,Invalidate" newline bitfld.long 0x04 22. " CINV_WAY2 ,Cache invalidate way 2" "No effect,Invalidate" bitfld.long 0x04 21. " CINV_WAY1 ,Cache invalidate way 1" "No effect,Invalidate" newline bitfld.long 0x04 20. " CINV_WAY0 ,Cache invalidate way 0" "No effect,Invalidate" bitfld.long 0x04 19. " S_B_INV ,Invalidate prefetch speculation buffer" "No effect,Invalidate" newline sif cpuis("MKV31F*")||cpuis("MKV30F*") rbitfld.long 0x04 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,?..." else rbitfld.long 0x04 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..." endif newline bitfld.long 0x04 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline bitfld.long 0x04 4. " B0DCE ,Bank 0 data cache enable" "Disabled,Enabled" bitfld.long 0x04 3. " B0ICE ,Bank 0 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled" bitfld.long 0x04 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " B0SEBE ,Bank 0 single entry buffer enable" "Disabled,Enabled" sif !cpuis("MKV30F128VLF10P")&&!cpuis("MKV30F64VLF10R")&&!cpuis("MKV30F64VLF10*")&&!cpuis("MKV31F128VLH10P")&&!cpuis("MKV31F256VLH12P")&&!cpuis("MKV31F256VLH12*")&&!cpuis("MKV42F128VLF16")&&!cpuis("MKV42F64VLF16")&&!cpuis("MKV42F64VLH16")&&!cpuis("MKV46F256VLH16*") group.long 0x08++0x03 line.long 0x00 "PFB1CR,Flash Bank 1 Control Register" rbitfld.long 0x00 28.--31. " B1RWSC ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" sif cpuis("MKV31F*")||cpuis("MKV30F*")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F512VLH12*") rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,?..." else rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..." endif newline bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B1SEBE ,Bank 1 single entry buffer enable" "Disabled,Enabled" endif width 13. tree "Cache Directory Storage Registers" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage Way 0 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage Way 0 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage Way 1 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage Way 1 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage Way 2 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage Way 2 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage Way 3 Set 0" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage Way 3 Set 1" hexmask.long.word 0x00 5.--19. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW0S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW0S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW0S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW0S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW0S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW0S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x120++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x124++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x128++0x03 line.long 0x00 "TAGVDW1S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x12C++0x03 line.long 0x00 "TAGVDW1S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x130++0x03 line.long 0x00 "TAGVDW1S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x134++0x03 line.long 0x00 "TAGVDW1S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x138++0x03 line.long 0x00 "TAGVDW1S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x13C++0x03 line.long 0x00 "TAGVDW1S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x140++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x144++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x148++0x03 line.long 0x00 "TAGVDW2S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x14C++0x03 line.long 0x00 "TAGVDW2S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x150++0x03 line.long 0x00 "TAGVDW2S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x154++0x03 line.long 0x00 "TAGVDW2S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x158++0x03 line.long 0x00 "TAGVDW2S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x15C++0x03 line.long 0x00 "TAGVDW2S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x160++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x164++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x168++0x03 line.long 0x00 "TAGVDW3S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x16C++0x03 line.long 0x00 "TAGVDW3S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x170++0x03 line.long 0x00 "TAGVDW3S4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x174++0x03 line.long 0x00 "TAGVDW3S5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x178++0x03 line.long 0x00 "TAGVDW3S6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x17C++0x03 line.long 0x00 "TAGVDW3S7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long 0x100++0x03 line.long 0x00 "TAGVDW0S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x104++0x03 line.long 0x00 "TAGVDW0S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x108++0x03 line.long 0x00 "TAGVDW0S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x10C++0x03 line.long 0x00 "TAGVDW0S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x110++0x03 line.long 0x00 "TAGVDW1S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x114++0x03 line.long 0x00 "TAGVDW1S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x118++0x03 line.long 0x00 "TAGVDW1S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x11C++0x03 line.long 0x00 "TAGVDW1S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x120++0x03 line.long 0x00 "TAGVDW2S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x124++0x03 line.long 0x00 "TAGVDW2S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x128++0x03 line.long 0x00 "TAGVDW2S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x12C++0x03 line.long 0x00 "TAGVDW2S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x130++0x03 line.long 0x00 "TAGVDW3S0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x134++0x03 line.long 0x00 "TAGVDW3S1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x138++0x03 line.long 0x00 "TAGVDW3S2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long 0x13C++0x03 line.long 0x00 "TAGVDW3S3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,Tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif tree.end tree "Cache Data Storage Registers" sif cpuis("MKV31F128VLH10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" elif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long (0x0+0x200)++0x0F line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)" group.long (0x10+0x200)++0x0F line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)" group.long (0x20+0x200)++0x0F line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)" group.long (0x30+0x200)++0x0F line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)" group.long (0x40+0x200)++0x0F line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)" group.long (0x50+0x200)++0x0F line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)" group.long (0x60+0x200)++0x0F line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)" group.long (0x70+0x200)++0x0F line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)" elif cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VFM10")||cpuis("MKV30F128VLH10")||cpuis("MKV30F64VFM10")||cpuis("MKV30F128VLF10")||cpuis("MKV30F64VLH10")||cpuis("MKV31F128VLH10")||cpuis("MKV31F128VLL10")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW0S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S4L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW0S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S5L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW0S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S6L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW0S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S7L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW1S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S4L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW1S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S5L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW1S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S6L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW1S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S7L,Cache Data Storage (Lower Word)" group.long 0x280++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x288++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x290++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x298++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x2A0++0x07 line.long 0x00 "DATAW2S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S4L,Cache Data Storage (Lower Word)" group.long 0x2A8++0x07 line.long 0x00 "DATAW2S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S5L,Cache Data Storage (Lower Word)" group.long 0x2B0++0x07 line.long 0x00 "DATAW2S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S6L,Cache Data Storage (Lower Word)" group.long 0x2B8++0x07 line.long 0x00 "DATAW2S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S7L,Cache Data Storage (Lower Word)" group.long 0x2C0++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x2C8++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x2D0++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x2D8++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" group.long 0x2E0++0x07 line.long 0x00 "DATAW3S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S4L,Cache Data Storage (Lower Word)" group.long 0x2E8++0x07 line.long 0x00 "DATAW3S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S5L,Cache Data Storage (Lower Word)" group.long 0x2F0++0x07 line.long 0x00 "DATAW3S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S6L,Cache Data Storage (Lower Word)" group.long 0x2F8++0x07 line.long 0x00 "DATAW3S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S7L,Cache Data Storage (Lower Word)" endif tree.end width 0x0B tree.end tree "FTFA (Flash Memory Module)" base ad:0x40020000 width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7") rgroup.byte 0x1C++0x03 line.byte 0x00 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Execute-only access control" "Yes,No" rgroup.byte 0x24++0x03 line.byte 0x00 "SACCL3,Supervisor-Only Access Regisster 3" bitfld.byte 0x00 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x00 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x01 "SACCL2,Supervisor-Only Access Regisster 2" bitfld.byte 0x01 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x01 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x02 "SACCL1,Supervisor-Only Access Regisster 1" bitfld.byte 0x02 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x02 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x03 "SACCL0,Supervisor-Only Access Regisster 0" bitfld.byte 0x03 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x03 0. " [24] ,Supervisor-only access control" "Yes,No" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-Only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-Only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-Only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-Only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-Only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-Only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-Only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-Only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" newline bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-Only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-Only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-Only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-Only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-Only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-Only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-Only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-Only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" newline bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" endif sif !cpuis("MKV10Z32VLC7*")&&!cpuis("MKV10Z32VFM7*") rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif width 0x0B tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08))&0x1000000)==0x00) group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" else group.long 0x00++0x0B line.long 0x00 "DATA,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" line.long 0x04 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,High polynominal half-word" newline hexmask.long.word 0x04 0.--15. 1. " LOW ,Low polynominal half-word" line.long 0x08 "CTRL,CRC Control Register" bitfld.long 0x08 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x08 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x08 26. " FXOR ,Complement read of CRC data register" "No XOR,Invert|complement" bitfld.long 0x08 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x08 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" endif width 0x0B tree.end tree "ADC (12-bit Cyclic Analog-to-Digital Converter)" base ad:0x4005C000 width 11. group.word 0x00++0x11 line.word 0x00 "CTRL1,Control Register 1" bitfld.word 0x00 15. " DMAEN0 ,DMA enable" "Disabled,Enabled" bitfld.word 0x00 14. " STOP0 ,Stop" "Normal,Stopped" bitfld.word 0x00 13. " START0 ,Start conversion" "No effect,Started" newline bitfld.word 0x00 12. " SYNC0 ,Sync0 enable" "Disabled,Enabled" bitfld.word 0x00 11. " EOSIE0 ,End of scan interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " ZCIE ,Zero crossing interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 9. " LLMTIE ,Low Limit interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " HLMTIE ,High limit interrupt enable" "Disabled,Enabled" bitfld.word 0x00 7. " CHNCFG_L3 ,Channel configure low bits" "ANB2/3-Single,ANB2/3-Differential" newline bitfld.word 0x00 6. " CHNCFG_L2 ,Channel configure low bits" "ANB0/1-Single,ANB0/1-Differential" bitfld.word 0x00 5. " CHNCFG_L1 ,Channel configure low bits" "ANA2/3-Single,ANA2/3-Differential" bitfld.word 0x00 4. " CHNCFG_L0 ,Channel configure low bits" "ANA0/1-Single,ANA0/1-Differential" newline bitfld.word 0x00 0.--2. " SMODE ,ADC scan mode control" "Once sequential,Once parallel,Loop sequential,Loop parallel,Triggered sequential,Triggered parallel,?..." line.word 0x02 "CTRL2,Control Register 2" bitfld.word 0x02 15. " DMAEN1 ,DMA enable" "Disabled,Enabled" bitfld.word 0x02 14. " STOP1 ,Stop" "Normal,Stopped" bitfld.word 0x02 13. " START1 ,Start conversion" "No effect,Started" newline bitfld.word 0x02 12. " SYNC1 ,Sync1 enable" "Disabled,Enabled" bitfld.word 0x02 11. " EOSIE1 ,End of scan interrupt enable" "Disabled,Enabled" bitfld.word 0x02 10. " CHNCFG_H3 ,Channel configure high bits" "ANB6/7-Single,ANB6/7-Differential" newline bitfld.word 0x02 9. " CHNCFG_H2 ,Channel configure high bits" "ANB4/5-Single,ANB4/5-Differential" bitfld.word 0x02 8. " CHNCFG_H1 ,Channel configure high bits" "ANA6/7-Single,ANA6/7-Differential" bitfld.word 0x02 7. " CHNCFG_H0 ,Channel configure high bits" "ANA4/5-Single,ANA4/5-Differential" newline bitfld.word 0x02 6. " SIMULT ,Simultaneous mode" "Independently,Simultaneously" bitfld.word 0x02 0.--5. " DIV0 ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,//58,/59,/60,/61,/62,/63,/64" line.word 0x04 "ZXCTRL1,Zero Crossing Control 1 Register" bitfld.word 0x04 14.--15. " ZCE[7] ,Zero crossing enable 7" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 12.--13. " [6] ,Zero crossing enable 6" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 10.--11. " [5] ,Zero crossing enable 5" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" newline bitfld.word 0x04 8.--9. " [4] ,Zero crossing enable 4" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 6.--7. " [3] ,Zero crossing enable 3" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 4.--5. " [2] ,Zero crossing enable 2" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" newline bitfld.word 0x04 2.--3. " [1] ,Zero crossing enable 1" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x04 0.--1. " [0] ,Zero crossing enable 0" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" line.word 0x06 "ZXCTRL2,Zero Crossing Control 2 Register" bitfld.word 0x06 14.--15. " ZCE[15] ,Zero crossing enable 15" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 12.--13. " [14] ,Zero crossing enable 14" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 10.--11. " [13] ,Zero crossing enable 13" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" newline bitfld.word 0x06 8.--9. " [12] ,Zero crossing enable 12" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 6.--7. " [11] ,Zero crossing enable 11" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 4.--5. " [10] ,Zero crossing enable 10" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" newline bitfld.word 0x06 2.--3. " [9] ,Zero crossing enable 9" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" bitfld.word 0x06 0.--1. " [8] ,Zero crossing enable 8" "Disabled,PositiveToNegative,NegativeToPositive,AnyChange" newline line.word 0x08 "CLIST1,Channel List Register 1" bitfld.word 0x08 12.--15. " SAMPLE3 ,Sample field 3" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x08 8.--11. " SAMPLE2 ,Sample field 2" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" newline bitfld.word 0x08 4.--7. " SAMPLE1 ,Sample field 1" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x08 0.--3. " SAMPLE0 ,Sample field 0" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" line.word 0x0A "CLIST2,Channel List Register 2" bitfld.word 0x0A 12.--15. " SAMPLE7 ,Sample field 7" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0A 8.--11. " SAMPLE6 ,Sample field 6" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" newline bitfld.word 0x0A 4.--7. " SAMPLE5 ,Sample field 5" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0A 0.--3. " SAMPLE4 ,Sample field 4" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" line.word 0x0C "CLIST3,Channel List Register 3" bitfld.word 0x0C 12.--15. " SAMPLE11 ,Sample field 11" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0C 8.--11. " SAMPLE10 ,Sample field 10" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" newline bitfld.word 0x0C 4.--7. " SAMPLE9 ,Sample field 9" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0C 0.--3. " SAMPLE8 ,Sample field 8" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" line.word 0x0E "CLIST4,Channel List Register 4" bitfld.word 0x0E 12.--15. " SAMPLE15 ,Sample field 15" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0E 8.--11. " SAMPLE14 ,Sample field 14" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" newline bitfld.word 0x0E 4.--7. " SAMPLE13 ,Sample field 13" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" bitfld.word 0x0E 0.--3. " SAMPLE12 ,Sample field 12" "SingleEnded:ANA0 Differential:ANA0+/ANA1-,SingleEnded:ANA1 Differential:ANA0+/ANA1-,SingleEnded:ANA2 Differential:ANA2+/ANA3-,SingleEnded:ANA3 Differential:ANA2+/ANA3-,SingleEnded:ANA4 Differential:ANA4+/ANA5-,SingleEnded:ANA5 Differential:ANA4+/ANA5-,SingleEnded:ANA6 Differential:ANA6+/ANA7-,SingleEnded:ANA7 Differential:ANA6+/ANA7-,SingleEnded:ANB0 Differential:ANB0+/ANB1-,SingleEnded:ANB1 Differential:ANB0+/ANB1-,SingleEnded:ANB2 Differential:ANB2+/ANB3-,SingleEnded:ANB3 Differential:ANB2+/ANB3-,SingleEnded:ANB4 Differential:ANB4+/ANB5-,SingleEnded:ANB5 Differential:ANB4+/ANB5-,SingleEnded:ANB6 Differential:ANB6+/ANB7-,SingleEnded:ANB7 Differential:ANB6+/ANB7-" newline line.word 0x10 "SDIS,Sample Disable Register" bitfld.word 0x10 15. " DS[15] ,Disable sample bit 15" "Enabled,Disabled" bitfld.word 0x10 14. " [14] ,Disable sample bit 14" "Enabled,Disabled" bitfld.word 0x10 13. " [13] ,Disable sample bit 13" "Enabled,Disabled" newline bitfld.word 0x10 12. " [12] ,Disable sample bit 12" "Enabled,Disabled" bitfld.word 0x10 11. " [11] ,Disable sample bit 11" "Enabled,Disabled" bitfld.word 0x10 10. " [10] ,Disable sample bit 10" "Enabled,Disabled" newline bitfld.word 0x10 9. " [9] ,Disable sample bit 9" "Enabled,Disabled" bitfld.word 0x10 8. " [8] ,Disable sample bit 8" "Enabled,Disabled" bitfld.word 0x10 7. " [7] ,Disable sample bit 7" "Enabled,Disabled" newline bitfld.word 0x10 6. " [6] ,Disable sample bit 6" "Enabled,Disabled" bitfld.word 0x10 5. " [5] ,Disable sample bit 5" "Enabled,Disabled" bitfld.word 0x10 4. " [4] ,Disable sample bit 4" "Enabled,Disabled" newline bitfld.word 0x10 3. " [3] ,Disable sample bit 3" "Enabled,Disabled" bitfld.word 0x10 2. " [2] ,Disable sample bit 2" "Enabled,Disabled" bitfld.word 0x10 1. " [1] ,Disable sample bit 1" "Enabled,Disabled" newline bitfld.word 0x10 0. " [0] ,Disable sample bit 0" "Enabled,Disabled" group.word 0x12++0x01 line.word 0x00 "STAT,Status Register" rbitfld.word 0x00 15. " CIP0 ,Conversion in progress" "Idle,Active" rbitfld.word 0x00 14. " CIP1 ,Conversion in progress" "Idle,Active" eventfld.word 0x00 12. " EOSI1 ,End of scan interrupt" "Not completed,Completed" newline eventfld.word 0x00 11. " EOSI0 ,End of scan interrupt" "Not completed,Completed" rbitfld.word 0x00 10. " ZCI ,Zero crossing interrupt" "Not requested,Requested" rbitfld.word 0x00 9. " LLMTI ,Low limit interrupt" "Not requested,Requested" newline rbitfld.word 0x00 8. " HLMTI ,High limit interrupt" "Not requested,Requested" rgroup.word 0x14++0x01 line.word 0x00 "RDY,Ready Register" bitfld.word 0x00 15. " RDY[15] ,Ready sample 15" "Not ready,Ready" bitfld.word 0x00 14. " [14] ,Ready sample 14" "Not ready,Ready" bitfld.word 0x00 13. " [13] ,Ready sample 13" "Not ready,Ready" newline bitfld.word 0x00 12. " [12] ,Ready sample 12" "Not ready,Ready" bitfld.word 0x00 11. " [11] ,Ready sample 11" "Not ready,Ready" bitfld.word 0x00 10. " [10] ,Ready sample 10" "Not ready,Ready" newline bitfld.word 0x00 9. " [9] ,Ready sample 9" "Not ready,Ready" bitfld.word 0x00 8. " [8] ,Ready sample 8" "Not ready,Ready" bitfld.word 0x00 7. " [7] ,Ready sample 7" "Not ready,Ready" newline bitfld.word 0x00 6. " [6] ,Ready sample 6" "Not ready,Ready" bitfld.word 0x00 5. " [5] ,Ready sample 5" "Not ready,Ready" bitfld.word 0x00 4. " [4] ,Ready sample 4" "Not ready,Ready" newline bitfld.word 0x00 3. " [3] ,Ready sample 3" "Not ready,Ready" bitfld.word 0x00 2. " [2] ,Ready sample 2" "Not ready,Ready" bitfld.word 0x00 1. " [1] ,Ready sample 1" "Not ready,Ready" newline bitfld.word 0x00 0. " [0] ,Ready sample 0" "Not ready,Ready" group.word 0x16++0x05 line.word 0x00 "LOLIMSTAT,Low Limit Status Register" eventfld.word 0x00 15. " LLS[15] ,Low limit status bits 15" "Not lower,Lower" eventfld.word 0x00 14. " [14] ,Low limit status bits 14" "Not lower,Lower" eventfld.word 0x00 13. " [13] ,Low limit status bits 13" "Not lower,Lower" newline eventfld.word 0x00 12. " [12] ,Low limit status bits 12" "Not lower,Lower" eventfld.word 0x00 11. " [11] ,Low limit status bits 11" "Not lower,Lower" eventfld.word 0x00 10. " [10] ,Low limit status bits 10" "Not lower,Lower" newline eventfld.word 0x00 9. " [9] ,Low limit status bits 9" "Not lower,Lower" eventfld.word 0x00 8. " [8] ,Low limit status bits 8" "Not lower,Lower" eventfld.word 0x00 7. " [7] ,Low limit status bits 7" "Not lower,Lower" newline eventfld.word 0x00 6. " [6] ,Low limit status bits 6" "Not lower,Lower" eventfld.word 0x00 5. " [5] ,Low limit status bits 5" "Not lower,Lower" eventfld.word 0x00 4. " [4] ,Low limit status bits 4" "Not lower,Lower" newline eventfld.word 0x00 3. " [3] ,Low limit status bits 3" "Not lower,Lower" eventfld.word 0x00 2. " [2] ,Low limit status bits 2" "Not lower,Lower" eventfld.word 0x00 1. " [1] ,Low limit status bits 1" "Not lower,Lower" newline eventfld.word 0x00 0. " [0] ,Low limit status bits 0" "Not lower,Lower" line.word 0x02 "HILIMSTAT,High Limit Status Register" eventfld.word 0x02 15. " HLS[15] ,High limit status bits 15" "Not higher,Higher" eventfld.word 0x02 14. " [14] ,High limit status bits 14" "Not higher,Higher" eventfld.word 0x02 13. " [13] ,High limit status bits 13" "Not higher,Higher" newline eventfld.word 0x02 12. " [12] ,High limit status bits 12" "Not higher,Higher" eventfld.word 0x02 11. " [11] ,High limit status bits 11" "Not higher,Higher" eventfld.word 0x02 10. " [10] ,High limit status bits 10" "Not higher,Higher" newline eventfld.word 0x02 9. " [9] ,High limit status bits 9" "Not higher,Higher" eventfld.word 0x02 8. " [8] ,High limit status bits 8" "Not higher,Higher" eventfld.word 0x02 7. " [7] ,High limit status bits 7" "Not higher,Higher" newline eventfld.word 0x02 6. " [6] ,High limit status bits 6" "Not higher,Higher" eventfld.word 0x02 5. " [5] ,High limit status bits 5" "Not higher,Higher" eventfld.word 0x02 4. " [4] ,High limit status bits 4" "Not higher,Higher" newline eventfld.word 0x02 3. " [3] ,High limit status bits 3" "Not higher,Higher" eventfld.word 0x02 2. " [2] ,High limit status bits 2" "Not higher,Higher" eventfld.word 0x02 1. " [1] ,High limit status bits 1" "Not higher,Higher" newline eventfld.word 0x02 0. " [0] ,High limit status bits 0" "Not higher,Higher" line.word 0x04 "ZXSTAT,Zero crossing status Register" eventfld.word 0x04 15. " ZCS[15] ,Zero crossing status 15" "Not crossed,Crossed" eventfld.word 0x04 14. " [14] ,Zero crossing status 14" "Not crossed,Crossed" eventfld.word 0x04 13. " [13] ,Zero crossing status 13" "Not crossed,Crossed" newline eventfld.word 0x04 12. " [12] ,Zero crossing status 12" "Not crossed,Crossed" eventfld.word 0x04 11. " [11] ,Zero crossing status 11" "Not crossed,Crossed" eventfld.word 0x04 10. " [10] ,Zero crossing status 10" "Not crossed,Crossed" newline eventfld.word 0x04 9. " [9] ,Zero crossing status 9" "Not crossed,Crossed" eventfld.word 0x04 8. " [8] ,Zero crossing status 8" "Not crossed,Crossed" eventfld.word 0x04 7. " [7] ,Zero crossing status 7" "Not crossed,Crossed" newline eventfld.word 0x04 6. " [6] ,Zero crossing status 6" "Not crossed,Crossed" eventfld.word 0x04 5. " [5] ,Zero crossing status 5" "Not crossed,Crossed" eventfld.word 0x04 4. " [4] ,Zero crossing status 4" "Not crossed,Crossed" newline eventfld.word 0x04 3. " [3] ,Zero crossing status 3" "Not crossed,Crossed" eventfld.word 0x04 2. " [2] ,Zero crossing status 2" "Not crossed,Crossed" eventfld.word 0x04 1. " [1] ,Zero crossing status 1" "Not crossed,Crossed" newline eventfld.word 0x04 0. " [0] ,Zero crossing status 0" "Not crossed,Crossed" group.word 0x1C++0x01 line.word 0x00 "RSLT0,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x1E++0x01 line.word 0x00 "RSLT1,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x20++0x01 line.word 0x00 "RSLT2,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x22++0x01 line.word 0x00 "RSLT3,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x24++0x01 line.word 0x00 "RSLT4,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x26++0x01 line.word 0x00 "RSLT5,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x28++0x01 line.word 0x00 "RSLT6,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2A++0x01 line.word 0x00 "RSLT7,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2C++0x01 line.word 0x00 "RSLT8,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x2E++0x01 line.word 0x00 "RSLT9,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x30++0x01 line.word 0x00 "RSLT10,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x32++0x01 line.word 0x00 "RSLT11,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x34++0x01 line.word 0x00 "RSLT12,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x36++0x01 line.word 0x00 "RSLT13,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x38++0x01 line.word 0x00 "RSLT14,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3A++0x01 line.word 0x00 "RSLT15,Result Registers with sign extension" rbitfld.word 0x00 15. " SEXT ,Sign extend" "Signed,Unsigned" hexmask.word 0x00 3.--14. 1. " RSLT ,Digital result of the conversion" group.word 0x3C++0x01 line.word 0x00 "LOLIM0,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x3E++0x01 line.word 0x00 "LOLIM1,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x40++0x01 line.word 0x00 "LOLIM2,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x42++0x01 line.word 0x00 "LOLIM3,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x44++0x01 line.word 0x00 "LOLIM4,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x46++0x01 line.word 0x00 "LOLIM5,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x48++0x01 line.word 0x00 "LOLIM6,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4A++0x01 line.word 0x00 "LOLIM7,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4C++0x01 line.word 0x00 "LOLIM8,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x4E++0x01 line.word 0x00 "LOLIM9,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x50++0x01 line.word 0x00 "LOLIM10,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x52++0x01 line.word 0x00 "LOLIM11,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x54++0x01 line.word 0x00 "LOLIM12,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x56++0x01 line.word 0x00 "LOLIM13,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x58++0x01 line.word 0x00 "LOLIM14,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5A++0x01 line.word 0x00 "LOLIM15,Low Limit Registers" hexmask.word 0x00 3.--14. 1. " LLMT ,Low limit bits" group.word 0x5C++0x01 line.word 0x00 "HILIM0,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x5E++0x01 line.word 0x00 "HILIM1,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x60++0x01 line.word 0x00 "HILIM2,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x62++0x01 line.word 0x00 "HILIM3,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x64++0x01 line.word 0x00 "HILIM4,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x66++0x01 line.word 0x00 "HILIM5,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x68++0x01 line.word 0x00 "HILIM6,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6A++0x01 line.word 0x00 "HILIM7,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6C++0x01 line.word 0x00 "HILIM8,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x6E++0x01 line.word 0x00 "HILIM9,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x70++0x01 line.word 0x00 "HILIM10,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x72++0x01 line.word 0x00 "HILIM11,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x74++0x01 line.word 0x00 "HILIM12,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x76++0x01 line.word 0x00 "HILIM13,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x78++0x01 line.word 0x00 "HILIM14,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7A++0x01 line.word 0x00 "HILIM15,High Limit Registers" hexmask.word 0x00 3.--14. 1. " HLMT ,High limit bits" group.word 0x7C++0x01 line.word 0x00 "OFFST0,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x7E++0x01 line.word 0x00 "OFFST1,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x80++0x01 line.word 0x00 "OFFST2,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x82++0x01 line.word 0x00 "OFFST3,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x84++0x01 line.word 0x00 "OFFST4,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x86++0x01 line.word 0x00 "OFFST5,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x88++0x01 line.word 0x00 "OFFST6,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x8A++0x01 line.word 0x00 "OFFST7,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x8C++0x01 line.word 0x00 "OFFST8,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x8E++0x01 line.word 0x00 "OFFST9,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x90++0x01 line.word 0x00 "OFFST10,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x92++0x01 line.word 0x00 "OFFST11,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x94++0x01 line.word 0x00 "OFFST12,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x96++0x01 line.word 0x00 "OFFST13,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x98++0x01 line.word 0x00 "OFFST14,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x9A++0x01 line.word 0x00 "OFFST15,Offset Registers" hexmask.word 0x00 3.--14. 1. " OFFSET ,ADC offset bits" group.word 0x9C++0x0F line.word 0x00 "PWR,Power Control Register" bitfld.word 0x00 15. " ASB ,Auto standby" "Disabled,Enabled" rbitfld.word 0x00 11. " PSTS1 ,ADC converter B power status" "Powered Up,Powered Down" rbitfld.word 0x00 10. " PSTS0 ,ADC converter A power status" "Powered Up,Powered Down" newline bitfld.word 0x00 4.--9. " PUDELAY ,Power up delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 3. " APD ,Auto powerdown" "Not active,Active" bitfld.word 0x00 1. " PD1 ,Manual power down for converter B" "Powered Up,Powered Down" newline bitfld.word 0x00 0. " PD0 ,Manual power down for converter A" "Powered Up,Powered Down" line.word 0x02 "CAL,Calibration Register" bitfld.word 0x02 15. " SEL_VREFH_B ,Select V REFH source" "VREFH pad,ADCB_CH2" bitfld.word 0x02 14. " SEL_VREFLO_B ,Select V REFLO source" "VREFH pad,ADCB_CH3" bitfld.word 0x02 13. " SEL_VREFH_A ,Select V REFH source" "VREFH pad,ADCA_CH2" newline bitfld.word 0x02 12. " SEL_VREFLO_A ,Select V REFLO source" "VREFH pad,ADCA_CH3" line.word 0x04 "GC1,Gain Control 1 Register" bitfld.word 0x04 14.--15. " GAIN[7] ,Gain control bit 7" "x1,x2,x4,?..." bitfld.word 0x04 12.--13. " [6] ,Gain control bit 6" "x1,x2,x4,?..." bitfld.word 0x04 10.--11. " [5] ,Gain control bit 5" "x1,x2,x4,?..." newline bitfld.word 0x04 8.--9. " [4] ,Gain control bit 4" "x1,x2,x4,?..." bitfld.word 0x04 6.--7. " [3] ,Gain control bit 3" "x1,x2,x4,?..." bitfld.word 0x04 4.--5. " [2] ,Gain control bit 2" "x1,x2,x4,?..." newline bitfld.word 0x04 2.--3. " [1] ,Gain control bit 1" "x1,x2,x4,?..." bitfld.word 0x04 0.--1. " [0] , Gain control bit 0" "x1,x2,x4,?..." line.word 0x06 "GC2,Gain Control 2 Register" bitfld.word 0x06 14.--15. " GAIN[15] ,Gain control bit 15" "x1,x2,x4,?..." bitfld.word 0x06 12.--13. " [14] ,Gain control bit 14" "x1,x2,x4,?..." bitfld.word 0x06 10.--11. " [13] ,Gain control bit 13" "x1,x2,x4,?..." newline bitfld.word 0x06 8.--9. " [12] ,Gain control bit 12" "x1,x2,x4,?..." bitfld.word 0x06 6.--7. " [11] ,Gain control bit 11" "x1,x2,x4,?..." bitfld.word 0x06 4.--5. " [10] ,Gain control bit 10" "x1,x2,x4,?..." newline bitfld.word 0x06 2.--3. " [9] ,Gain control bit 9" "x1,x2,x4,?..." bitfld.word 0x06 0.--1. " [8] , Gain control bit 8" "x1,x2,x4,?..." line.word 0x08 "SCTRL,Scan Control Register" bitfld.word 0x08 15. " SC[15] ,Scan control bit 15" "Immediate,Delayed" bitfld.word 0x08 14. " [14] ,Scan control bit 14" "Immediate,Delayed" bitfld.word 0x08 13. " [13] ,Scan control bit 13" "Immediate,Delayed" newline bitfld.word 0x08 12. " [12] ,Scan control bit 12" "Immediate,Delayed" bitfld.word 0x08 11. " [11] ,Scan control bit 11" "Immediate,Delayed" bitfld.word 0x08 10. " [10] ,Scan control bit 10" "Immediate,Delayed" newline bitfld.word 0x08 9. " [9] ,Scan control bit 9" "Immediate,Delayed" bitfld.word 0x08 8. " [8] ,Scan control bit 8" "Immediate,Delayed" bitfld.word 0x08 7. " [7] ,Scan control bit 7" "Immediate,Delayed" newline bitfld.word 0x08 6. " [6] ,Scan control bit 6" "Immediate,Delayed" bitfld.word 0x08 5. " [5] ,Scan control bit 5" "Immediate,Delayed" bitfld.word 0x08 4. " [4] ,Scan control bit 4" "Immediate,Delayed" newline bitfld.word 0x08 3. " [3] ,Scan control bit 3" "Immediate,Delayed" bitfld.word 0x08 2. " [2] ,Scan control bit 2" "Immediate,Delayed" bitfld.word 0x08 1. " [1] ,Scan control bit 1" "Immediate,Delayed" newline bitfld.word 0x08 0. " [0] ,Scan control bit 0" "Immediate,Delayed" line.word 0x0A "PWR2,Power Control Register" bitfld.word 0x0A 8.--13. " DIV1 ,Clock divisor select" "/2,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" bitfld.word 0x0A 2.--3. " SPEEDB ,ADCB speed control bits" "6.25MHz-6mA,12.5MHz-10.8mA,18.75MHz-18mA,25MHz-25.2mA" bitfld.word 0x0A 0.--1. " SPEEDA ,ADCA speed control bits" "6.25MHz-6mA,12.5MHz-10.8mA,18.75MHz-18mA,25MHz-25.2mA" line.word 0x0C "CTRL3,Control Register 3" bitfld.word 0x0C 6. " DMASRC ,DMA trigger source" "End of scan interrupt,RDY bits" bitfld.word 0x0C 3.--5. " SCNT1 ,Sample window count 1" "2,3,4,5,6,7,8,9" bitfld.word 0x0C 0.--2. " SCNT0 ,Sample window count 0" "2,3,4,5,6,7,8,9" line.word 0x0E "SCHLTEN,Scan Halted Interrupt Enable Register" bitfld.word 0x0E 15. " SCHLTEN[15] ,Scan halted interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x0E 14. " [14] ,Scan halted interrupt enable bit 14" "Disabled,Enabled" bitfld.word 0x0E 13. " [13] ,Scan halted interrupt enable bit 13" "Disabled,Enabled" newline bitfld.word 0x0E 12. " [12] ,Scan halted interrupt enable bit 12" "Disabled,Enabled" bitfld.word 0x0E 11. " [11] ,Scan halted interrupt enable bit 11" "Disabled,Enabled" bitfld.word 0x0E 10. " [10] ,Scan halted interrupt enable bit 10" "Disabled,Enabled" newline bitfld.word 0x0E 9. " [9] ,Scan halted interrupt enable bit 9" "Disabled,Enabled" bitfld.word 0x0E 8. " [8] ,Scan halted interrupt enable bit 8" "Disabled,Enabled" bitfld.word 0x0E 7. " [7] ,Scan halted interrupt enable bit 7" "Disabled,Enabled" newline bitfld.word 0x0E 6. " [6] ,Scan halted interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x0E 5. " [5] ,Scan halted interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x0E 4. " [4] ,Scan halted interrupt enable bit 4" "Disabled,Enabled" newline bitfld.word 0x0E 3. " [3] ,Scan halted interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x0E 2. " [2] ,Scan halted interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x0E 1. " [1] ,Scan halted interrupt enable bit 1" "Disabled,Enabled" newline bitfld.word 0x0E 0. " [0] ,Scan halted interrupt enable bit 0" "Disabled,Enabled" width 0x0B tree.end tree.open "CMP (Comparator)" tree "CMP_0" base ad:0x40073000 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF Output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,,VREF OUT/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP_1" base ad:0x40073008 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,IN3,,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP_2" base ad:0x40073010 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,IN2,,IN4,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,IN2,,IN4,,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree "CMP_3" base ad:0x40073018 width 15. group.byte 0x00++0x05 line.byte 0x00 "CR0,Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Not selected,Selected" bitfld.byte 0x01 6. " WE ,Windowing enable" "Not selected,Selected" sif cpuis("MKV10Z*")||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VFM7*")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*")||cpuis("MKV11Z64VLH7") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" newline bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" else newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" newline bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" endif line.byte 0x02 "FPR,Filter Period Register" line.byte 0x03 "SCR,Status And Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" newline eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "0,1" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.byte 0x05 "MUXCR,MUX Control Register" sif (cpuis("MKV10Z*"))||cpuis("MKV31F256VLH12")||cpuis("MKV31F256VLL12")||cpuis("MKV31F512VLH12")||cpuis("MKV31F512VLL12")||cpuis("MKV30F*")||cpuis("MKV5*")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV31F*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7P") sif cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,,Bandgap,6-bit DAC0" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") elif cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7") elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") elif cpuis("MKV10Z*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0,IN4,IN5,Bandgap,6-bit DAC0" elif cpuis("MKV5?F???VLL24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." elif cpuis("MKV5?F???VLQ24")||cpuis("MKV5?F???VMD24") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,,IN4,IN5,?..." newline elif cpuis("MKV46F256VLH16*")||cpuis("MKV42F64VLH16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",,,,IN4,IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/IN5,Bandgap,6-bit DAC0" newline elif cpuis("MKV31F512VLL12P") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF OUT/IN5,Bandgap,6-bit DAC1" newline elif cpuis("MKV31F256VLL12") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline elif cpuis("MKV30F*") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,,12-bit DAC0/IN3,,VREF output/in5,Bandgap,6-bit DAC0" newline else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,CMP_REF,,Internal 6-bit DAC" newline endif else bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,Internal 12-bit DAC,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,CMP_REF,,Internal 6-bit DAC" endif width 0x0B tree.end tree.end tree "DAC (Digital-to-Analog Converter)" base ad:0x4003F000 width 16. group.byte 0x0++0x01 line.byte 0x00 "DAC0_DAT0L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAC0_DAT1L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAC0_DAT2L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAC0_DAT3L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAC0_DAT4L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAC0_DAT5L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAC0_DAT6L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAC0_DAT7L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAC0_DAT8L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAC0_DAT9L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAC0_DAT10L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAC0_DAT11L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAC0_DAT12L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAC0_DAT13L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAC0_DAT14L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAC0_DAT15L,DAC Data Low Register" line.byte 0x01 "DAC0_DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x20++0x01 line.byte 0x00 "DAC0_SR,DAC Status Register" sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" elif cpuis("MKV10Z*") bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" else bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer watermark flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer top position flag" "Non-zero,Zero" newline bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag" "Not equal DACBFUP,Equal DACBFUP" endif line.byte 0x01 "DAC0_C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "DACREF_1,DACREF_2" newline bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-power,Low-power" newline sif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" elif cpuis("MKV10Z*") newline bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" else bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" endif sif cpuis("MKV30F*")||cpuis("MKV31F*")||cpuis("MKV5*")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") if (((per.b(ad:0x4003F000+0x22))&0x06)==0x06) group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " READ_POINTER ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " WRITE_POINTER ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VLC7R") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 2. " DACBFMD ,DAC buffer work mode select" "Normal,One-Time scan" newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" elif cpuis("MKV10Z*")||cpuis("MKV11Z*") group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." newline bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x01 0. " DACBFUP ,DAC buffer upper limit" "0,1" else group.byte 0x22++0x01 line.byte 0x00 "DAC0_C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" newline bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" line.byte 0x01 "DAC0_C2,DAC Control Register 2" bitfld.byte 0x01 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x01 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.open "PWMA (Pulse Width Modulator A)" tree "SUBMODULE_0" base ad:0x40033000 width 11. rgroup.word 0x00++0x01 line.word 0x00 "CNT,Counter Register" if (((per.w(ad:0x40033000+0x188))&0x01)==0x01) rgroup.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" else group.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" endif group.word 0x04++0x03 line.word 0x00 "CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" bitfld.word 0x00 6. " FORCE ,Force initialization" "No effect,Initialize" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" newline bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." line.word 0x02 "CTRL,Control Register" bitfld.word 0x02 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x02 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x02 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x02 9. " DT[1] ,PWMX input after deadtime 1" "Logic 0,Logic 1" rbitfld.word 0x02 8. " DT[0] ,PWMX input after deadtime 0" "Logic 0,Logic 1" newline bitfld.word 0x02 7. " COMPMODE ,Compare mode" "Equal,Equal or greater" bitfld.word 0x02 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.word 0x02 2. " LDMOD ,Load mode select" "Next Reload,Immediately" newline bitfld.word 0x02 1. " DBLX ,PWMX Double switching enable" "Disabled,Enabled" newline bitfld.word 0x02 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word 0x0A++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" hexmask.word.byte 0x02 11.--15. 1. " FRACVAL1 ,Fractional value 1 register" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" hexmask.word.byte 0x06 11.--15. 1. " FRACVAL2 ,Fractional value 2 register" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" hexmask.word.byte 0x0A 11.--15. 1. " FRACVAL3 ,Fractional value 3 register" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" hexmask.word.byte 0x0E 11.--15. 1. " FRACVAL4 ,Fractional value 4 register" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" hexmask.word.byte 0x12 11.--15. 1. " FRACVAL5 ,Fractional value 5 register" line.word 0x14 "VAL5,Value Register 5" group.word 0x20++0x0D line.word 0x00 "FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" bitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" newline bitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" line.word 0x02 "OCTRL,Output Control Register" rbitfld.word 0x02 15. " PWMA_IN ,PWM_A input" "Logic 0,Logic 1" rbitfld.word 0x02 14. " PWMB_IN ,PWM_B input" "Logic 0,Logic 1" newline rbitfld.word 0x02 13. " PWMX_IN ,PWM_X input" "Logic 0,Logic 1" newline bitfld.word 0x02 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" bitfld.word 0x02 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x02 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" newline bitfld.word 0x02 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x04 "STS,Status Register" rbitfld.word 0x04 14. " RUF ,Registers updated flag" "Not Updated,Updated" eventfld.word 0x04 13. " REF ,Reload error flag" "No error,Error" eventfld.word 0x04 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x04 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" newline eventfld.word 0x04 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x04 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x04 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" newline eventfld.word 0x04 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" eventfld.word 0x04 6. " CFX0 ,Capture flag X0" "Not occurred,Occurred" newline eventfld.word 0x04 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x04 4. " CMPF[4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x04 3. " CMPF[3] ,Compare flag VAL3" "Not occurred,Occurred" eventfld.word 0x04 2. " CMPF[2] ,Compare flag VAL2" "Not occurred,Occurred" newline eventfld.word 0x04 1. " CMPF[1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x04 0. " CMPF[0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x06 "INTEN,Interrupt Enable Register" bitfld.word 0x06 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x06 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x06 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 5. " CMPIE5 ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x06 4. " CMPIE4 ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x06 3. " CMPIE3 ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x06 2. " CMPIE2 ,Compare interrupt enable 2" "Disabled,Enabled" newline bitfld.word 0x06 1. " CMPIE1 ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x06 0. " CMPIE0 ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x08 "DMAEN,DMA Enable Register" bitfld.word 0x08 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x08 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x08 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x08 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x0A "TCTRL,Output Trigger Control Register" bitfld.word 0x0A 15. " PWAOT0 ,Output trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x0A 14. " PWBOT1 ,Output trigger 1 source select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x0A 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" bitfld.word 0x0A 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" newline bitfld.word 0x0A 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x0A 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x0A 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" bitfld.word 0x0A 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0C "DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0C 11. " DIS0X_3 ,PWM_X fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" if (((per.l(ad:0x40033000+0x20)&0x04))==0x00) group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. " DTCNT0 ,Deadtime count register 0" else group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 5.--15. 1. " DTCNT0_U ,Deadtime count register 0" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x40033000+0x20)&0x10))==0x00) group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. " DTCNT1 ,Deadtime count register 1" else group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 5.--15. 1. " DTCNT1 ,Deadtime count register 1" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x34++0x0B line.word 0x00 "CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x00 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x00 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x00 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " INP_SELA ,Input select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x00 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x00 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x00 1. " ONESHOTA ,One shot mode A" "Free run,One shot" newline bitfld.word 0x00 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x02 "CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTA ,Edge counter A" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x04 "CAPTCTRLB,Capture Control B Register" rbitfld.word 0x04 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" newline bitfld.word 0x04 6. " INP_SELB ,Input select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x04 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTB ,One shot mode B" "Free run,One shot" newline bitfld.word 0x04 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x06 "CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x08 "CAPTCTRLX,Capture Control X Register" rbitfld.word 0x08 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" newline bitfld.word 0x08 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x08 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" newline bitfld.word 0x08 1. " ONESHOTX ,One shot mode X" "Free run,One shot" bitfld.word 0x08 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0A "CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word 0x40++0x03 line.word 0x00 "CVAL0,Capture Value 0 Register" line.word 0x02 "CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x44++0x03 line.word 0x00 "CVAL1,Capture Value 1 Register" line.word 0x02 "CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x02 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x48++0x03 line.word 0x00 "CVAL2,Capture Value 2 Register" line.word 0x02 "CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x02 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x4C++0x03 line.word 0x00 "CVAL3,Capture Value 3 Register" line.word 0x02 "CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x02 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x50++0x03 line.word 0x00 "CVAL4,Capture Value 4 Register" line.word 0x02 "CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x02 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x54++0x03 line.word 0x00 "CVAL5,Capture Value 5 Register" line.word 0x02 "CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x02 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "SUBMODULE_1" base ad:0x40033060 width 11. rgroup.word 0x00++0x01 line.word 0x00 "CNT,Counter Register" if (((per.w(ad:0x40033060+0x188))&0x02)==0x02) rgroup.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" else group.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" endif group.word 0x04++0x03 line.word 0x00 "CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" bitfld.word 0x00 6. " FORCE ,Force initialization" "No effect,Initialize" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" newline bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." line.word 0x02 "CTRL,Control Register" bitfld.word 0x02 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x02 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x02 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x02 9. " DT[1] ,PWMX input after deadtime 1" "Logic 0,Logic 1" rbitfld.word 0x02 8. " DT[0] ,PWMX input after deadtime 0" "Logic 0,Logic 1" newline bitfld.word 0x02 7. " COMPMODE ,Compare mode" "Equal,Equal or greater" bitfld.word 0x02 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.word 0x02 2. " LDMOD ,Load mode select" "Next Reload,Immediately" newline bitfld.word 0x02 1. " DBLX ,PWMX Double switching enable" "Disabled,Enabled" newline bitfld.word 0x02 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word 0x0A++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" hexmask.word.byte 0x02 11.--15. 1. " FRACVAL1 ,Fractional value 1 register" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" hexmask.word.byte 0x06 11.--15. 1. " FRACVAL2 ,Fractional value 2 register" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" hexmask.word.byte 0x0A 11.--15. 1. " FRACVAL3 ,Fractional value 3 register" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" hexmask.word.byte 0x0E 11.--15. 1. " FRACVAL4 ,Fractional value 4 register" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" hexmask.word.byte 0x12 11.--15. 1. " FRACVAL5 ,Fractional value 5 register" line.word 0x14 "VAL5,Value Register 5" group.word 0x20++0x0D line.word 0x00 "FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" bitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" newline bitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" line.word 0x02 "OCTRL,Output Control Register" rbitfld.word 0x02 15. " PWMA_IN ,PWM_A input" "Logic 0,Logic 1" rbitfld.word 0x02 14. " PWMB_IN ,PWM_B input" "Logic 0,Logic 1" newline rbitfld.word 0x02 13. " PWMX_IN ,PWM_X input" "Logic 0,Logic 1" newline bitfld.word 0x02 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" bitfld.word 0x02 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x02 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" newline bitfld.word 0x02 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x04 "STS,Status Register" rbitfld.word 0x04 14. " RUF ,Registers updated flag" "Not Updated,Updated" eventfld.word 0x04 13. " REF ,Reload error flag" "No error,Error" eventfld.word 0x04 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x04 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" newline eventfld.word 0x04 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x04 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x04 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" newline eventfld.word 0x04 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" eventfld.word 0x04 6. " CFX0 ,Capture flag X0" "Not occurred,Occurred" newline eventfld.word 0x04 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x04 4. " CMPF[4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x04 3. " CMPF[3] ,Compare flag VAL3" "Not occurred,Occurred" eventfld.word 0x04 2. " CMPF[2] ,Compare flag VAL2" "Not occurred,Occurred" newline eventfld.word 0x04 1. " CMPF[1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x04 0. " CMPF[0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x06 "INTEN,Interrupt Enable Register" bitfld.word 0x06 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x06 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x06 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 5. " CMPIE5 ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x06 4. " CMPIE4 ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x06 3. " CMPIE3 ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x06 2. " CMPIE2 ,Compare interrupt enable 2" "Disabled,Enabled" newline bitfld.word 0x06 1. " CMPIE1 ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x06 0. " CMPIE0 ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x08 "DMAEN,DMA Enable Register" bitfld.word 0x08 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x08 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x08 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x08 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x0A "TCTRL,Output Trigger Control Register" bitfld.word 0x0A 15. " PWAOT0 ,Output trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x0A 14. " PWBOT1 ,Output trigger 1 source select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x0A 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" bitfld.word 0x0A 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" newline bitfld.word 0x0A 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x0A 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x0A 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" bitfld.word 0x0A 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0C "DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0C 11. " DIS0X_3 ,PWM_X fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" if (((per.l(ad:0x40033060+0x20)&0x04))==0x00) group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. " DTCNT0 ,Deadtime count register 0" else group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 5.--15. 1. " DTCNT0_U ,Deadtime count register 0" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x40033060+0x20)&0x10))==0x00) group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. " DTCNT1 ,Deadtime count register 1" else group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 5.--15. 1. " DTCNT1 ,Deadtime count register 1" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x34++0x0B line.word 0x00 "CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x00 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x00 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x00 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " INP_SELA ,Input select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x00 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x00 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x00 1. " ONESHOTA ,One shot mode A" "Free run,One shot" newline bitfld.word 0x00 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x02 "CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTA ,Edge counter A" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x04 "CAPTCTRLB,Capture Control B Register" rbitfld.word 0x04 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" newline bitfld.word 0x04 6. " INP_SELB ,Input select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x04 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTB ,One shot mode B" "Free run,One shot" newline bitfld.word 0x04 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x06 "CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x08 "CAPTCTRLX,Capture Control X Register" rbitfld.word 0x08 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" newline bitfld.word 0x08 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x08 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" newline bitfld.word 0x08 1. " ONESHOTX ,One shot mode X" "Free run,One shot" bitfld.word 0x08 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0A "CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word 0x40++0x03 line.word 0x00 "CVAL0,Capture Value 0 Register" line.word 0x02 "CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x44++0x03 line.word 0x00 "CVAL1,Capture Value 1 Register" line.word 0x02 "CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x02 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x48++0x03 line.word 0x00 "CVAL2,Capture Value 2 Register" line.word 0x02 "CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x02 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x4C++0x03 line.word 0x00 "CVAL3,Capture Value 3 Register" line.word 0x02 "CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x02 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x50++0x03 line.word 0x00 "CVAL4,Capture Value 4 Register" line.word 0x02 "CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x02 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x54++0x03 line.word 0x00 "CVAL5,Capture Value 5 Register" line.word 0x02 "CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x02 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "SUBMODULE_2" base ad:0x400330C0 width 11. rgroup.word 0x00++0x01 line.word 0x00 "CNT,Counter Register" if (((per.w(ad:0x400330C0+0x188))&0x04)==0x04) rgroup.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" else group.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" endif group.word 0x04++0x03 line.word 0x00 "CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" bitfld.word 0x00 6. " FORCE ,Force initialization" "No effect,Initialize" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" newline bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." line.word 0x02 "CTRL,Control Register" bitfld.word 0x02 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x02 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x02 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x02 9. " DT[1] ,PWMX input after deadtime 1" "Logic 0,Logic 1" rbitfld.word 0x02 8. " DT[0] ,PWMX input after deadtime 0" "Logic 0,Logic 1" newline bitfld.word 0x02 7. " COMPMODE ,Compare mode" "Equal,Equal or greater" bitfld.word 0x02 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.word 0x02 2. " LDMOD ,Load mode select" "Next Reload,Immediately" newline bitfld.word 0x02 1. " DBLX ,PWMX Double switching enable" "Disabled,Enabled" newline bitfld.word 0x02 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word 0x0A++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" hexmask.word.byte 0x02 11.--15. 1. " FRACVAL1 ,Fractional value 1 register" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" hexmask.word.byte 0x06 11.--15. 1. " FRACVAL2 ,Fractional value 2 register" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" hexmask.word.byte 0x0A 11.--15. 1. " FRACVAL3 ,Fractional value 3 register" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" hexmask.word.byte 0x0E 11.--15. 1. " FRACVAL4 ,Fractional value 4 register" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" hexmask.word.byte 0x12 11.--15. 1. " FRACVAL5 ,Fractional value 5 register" line.word 0x14 "VAL5,Value Register 5" group.word 0x20++0x0D line.word 0x00 "FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" bitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" newline bitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" line.word 0x02 "OCTRL,Output Control Register" rbitfld.word 0x02 15. " PWMA_IN ,PWM_A input" "Logic 0,Logic 1" rbitfld.word 0x02 14. " PWMB_IN ,PWM_B input" "Logic 0,Logic 1" newline rbitfld.word 0x02 13. " PWMX_IN ,PWM_X input" "Logic 0,Logic 1" newline bitfld.word 0x02 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" bitfld.word 0x02 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x02 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" newline bitfld.word 0x02 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x04 "STS,Status Register" rbitfld.word 0x04 14. " RUF ,Registers updated flag" "Not Updated,Updated" eventfld.word 0x04 13. " REF ,Reload error flag" "No error,Error" eventfld.word 0x04 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x04 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" newline eventfld.word 0x04 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x04 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x04 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" newline eventfld.word 0x04 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" eventfld.word 0x04 6. " CFX0 ,Capture flag X0" "Not occurred,Occurred" newline eventfld.word 0x04 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x04 4. " CMPF[4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x04 3. " CMPF[3] ,Compare flag VAL3" "Not occurred,Occurred" eventfld.word 0x04 2. " CMPF[2] ,Compare flag VAL2" "Not occurred,Occurred" newline eventfld.word 0x04 1. " CMPF[1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x04 0. " CMPF[0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x06 "INTEN,Interrupt Enable Register" bitfld.word 0x06 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x06 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x06 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 5. " CMPIE5 ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x06 4. " CMPIE4 ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x06 3. " CMPIE3 ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x06 2. " CMPIE2 ,Compare interrupt enable 2" "Disabled,Enabled" newline bitfld.word 0x06 1. " CMPIE1 ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x06 0. " CMPIE0 ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x08 "DMAEN,DMA Enable Register" bitfld.word 0x08 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x08 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x08 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x08 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x0A "TCTRL,Output Trigger Control Register" bitfld.word 0x0A 15. " PWAOT0 ,Output trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x0A 14. " PWBOT1 ,Output trigger 1 source select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x0A 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" bitfld.word 0x0A 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" newline bitfld.word 0x0A 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x0A 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x0A 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" bitfld.word 0x0A 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0C "DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0C 11. " DIS0X_3 ,PWM_X fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" if (((per.l(ad:0x400330C0+0x20)&0x04))==0x00) group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. " DTCNT0 ,Deadtime count register 0" else group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 5.--15. 1. " DTCNT0_U ,Deadtime count register 0" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x400330C0+0x20)&0x10))==0x00) group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. " DTCNT1 ,Deadtime count register 1" else group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 5.--15. 1. " DTCNT1 ,Deadtime count register 1" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x34++0x0B line.word 0x00 "CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x00 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x00 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x00 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " INP_SELA ,Input select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x00 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x00 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x00 1. " ONESHOTA ,One shot mode A" "Free run,One shot" newline bitfld.word 0x00 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x02 "CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTA ,Edge counter A" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x04 "CAPTCTRLB,Capture Control B Register" rbitfld.word 0x04 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" newline bitfld.word 0x04 6. " INP_SELB ,Input select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x04 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTB ,One shot mode B" "Free run,One shot" newline bitfld.word 0x04 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x06 "CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x08 "CAPTCTRLX,Capture Control X Register" rbitfld.word 0x08 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" newline bitfld.word 0x08 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x08 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" newline bitfld.word 0x08 1. " ONESHOTX ,One shot mode X" "Free run,One shot" bitfld.word 0x08 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0A "CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word 0x40++0x03 line.word 0x00 "CVAL0,Capture Value 0 Register" line.word 0x02 "CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x44++0x03 line.word 0x00 "CVAL1,Capture Value 1 Register" line.word 0x02 "CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x02 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x48++0x03 line.word 0x00 "CVAL2,Capture Value 2 Register" line.word 0x02 "CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x02 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x4C++0x03 line.word 0x00 "CVAL3,Capture Value 3 Register" line.word 0x02 "CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x02 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x50++0x03 line.word 0x00 "CVAL4,Capture Value 4 Register" line.word 0x02 "CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x02 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x54++0x03 line.word 0x00 "CVAL5,Capture Value 5 Register" line.word 0x02 "CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x02 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "SUBMODULE_3" base ad:0x40033120 width 11. rgroup.word 0x00++0x01 line.word 0x00 "CNT,Counter Register" if (((per.w(ad:0x40033120+0x188))&0x08)==0x08) rgroup.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" else group.word 0x02++0x01 line.word 0x00 "INIT,Initial Count Register" endif group.word 0x04++0x03 line.word 0x00 "CTRL2,Control 2 Register" bitfld.word 0x00 15. " DBGEN ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 14. " WAITEN ,WAIT enable" "Disabled,Enabled" bitfld.word 0x00 13. " INDEP ,Independent or complementary pair operation" "Complementary,Independent" bitfld.word 0x00 12. " PWM23_INIT ,PWM23 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 11. " PWM45_INIT ,PWM45 initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 10. " PWMX_INIT ,PWM_X initial value" "Logic 0,Logic 1" newline bitfld.word 0x00 8.--9. " INIT_SEL ,Initialization control select" "Local Sync,Master Reload,Master Sync,EXT_SYNC" bitfld.word 0x00 7. " FRCEN ,Force initialization enable" "Disabled,Enabled" bitfld.word 0x00 6. " FORCE ,Force initialization" "No effect,Initialize" bitfld.word 0x00 3.--5. " FORCE_SEL ,Source of the FORCE OUTPUT signal for this submodule" "Local force signal,Master force signal,Local reload signal,Master reload signal,Local sync signal,Master sync signal,External force signal,External sync signal" newline bitfld.word 0x00 2. " RELOAD_SEL ,Reload source select" "Local,Master" bitfld.word 0x00 0.--1. " CLK_SEL ,Clock source select" "IPBus,EXT_CLK,AUX_CLK,?..." line.word 0x02 "CTRL,Control Register" bitfld.word 0x02 12.--15. " LDFQ ,Select load every PWM opportunity" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x02 11. " HALF ,Half cycle reload" "Disabled,Enabled" bitfld.word 0x02 10. " FULL ,Full cycle reload" "Disabled,Enabled" rbitfld.word 0x02 9. " DT[1] ,PWMX input after deadtime 1" "Logic 0,Logic 1" rbitfld.word 0x02 8. " DT[0] ,PWMX input after deadtime 0" "Logic 0,Logic 1" newline bitfld.word 0x02 7. " COMPMODE ,Compare mode" "Equal,Equal or greater" bitfld.word 0x02 4.--6. " PRSC ,Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" newline bitfld.word 0x02 2. " LDMOD ,Load mode select" "Next Reload,Immediately" newline bitfld.word 0x02 1. " DBLX ,PWMX Double switching enable" "Disabled,Enabled" newline bitfld.word 0x02 0. " DBLEN ,Double switching enable" "Disabled,Enabled" group.word 0x0A++0x15 line.word 0x00 "VAL0,Value Register 0" line.word 0x02 "FRACVAL1,Fractional Value Register 1" hexmask.word.byte 0x02 11.--15. 1. " FRACVAL1 ,Fractional value 1 register" line.word 0x04 "VAL1,Value Register 1" line.word 0x06 "FRACVAL2,Fractional Value Register 2" hexmask.word.byte 0x06 11.--15. 1. " FRACVAL2 ,Fractional value 2 register" line.word 0x08 "VAL2,Value Register 2" line.word 0x0A "FRACVAL3,Fractional Value Register 3" hexmask.word.byte 0x0A 11.--15. 1. " FRACVAL3 ,Fractional value 3 register" line.word 0x0C "VAL3,Value Register 3" line.word 0x0E "FRACVAL4,Fractional Value Register 4" hexmask.word.byte 0x0E 11.--15. 1. " FRACVAL4 ,Fractional value 4 register" line.word 0x10 "VAL4,Value Register 4" line.word 0x12 "FRACVAL5,Fractional Value Register 5" hexmask.word.byte 0x12 11.--15. 1. " FRACVAL5 ,Fractional value 5 register" line.word 0x14 "VAL5,Value Register 5" group.word 0x20++0x0D line.word 0x00 "FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. " TEST ,Test status bit" "0,1" bitfld.word 0x00 8. " FRAC_PU ,Fractional delay circuit power up" "Powered down,Powered up" bitfld.word 0x00 4. " FRAC45_EN ,Fractional cycle placement enable for PWM_B" "Disabled,Enabled" bitfld.word 0x00 2. " FRAC23_EN ,Fractional cycle placement enable for PWM_A" "Disabled,Enabled" newline bitfld.word 0x00 1. " FRAC1_EN ,Fractional cycle PWM period enable" "Disabled,Enabled" line.word 0x02 "OCTRL,Output Control Register" rbitfld.word 0x02 15. " PWMA_IN ,PWM_A input" "Logic 0,Logic 1" rbitfld.word 0x02 14. " PWMB_IN ,PWM_B input" "Logic 0,Logic 1" newline rbitfld.word 0x02 13. " PWMX_IN ,PWM_X input" "Logic 0,Logic 1" newline bitfld.word 0x02 10. " POLA ,PWM_A output polarity" "Not inverted,Inverted" bitfld.word 0x02 9. " POLB ,PWM_B output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 8. " POLX ,PWM_X output polarity" "Not inverted,Inverted" newline bitfld.word 0x02 4.--5. " PWMAFS ,PWM_A fault state" "Forced to 0,Forced to 1,Tristated,Tristated" bitfld.word 0x02 2.--3. " PWMBFS ,PWM_B fault state" "Forced to 0,Forced to 1,Tristated,Tristated" newline bitfld.word 0x02 0.--1. " PWMXFS ,PWM_X fault state" "Forced to 0,Forced to 1,Tristated,Tristated" line.word 0x04 "STS,Status Register" rbitfld.word 0x04 14. " RUF ,Registers updated flag" "Not Updated,Updated" eventfld.word 0x04 13. " REF ,Reload error flag" "No error,Error" eventfld.word 0x04 12. " RF ,Reload flag" "Not reloaded,Reloaded" eventfld.word 0x04 11. " CFA1 ,Capture flag A1" "Not occurred,Occurred" newline eventfld.word 0x04 10. " CFA0 ,Capture flag A0" "Not occurred,Occurred" eventfld.word 0x04 9. " CFB1 ,Capture flag B1" "Not occurred,Occurred" eventfld.word 0x04 8. " CFB0 ,Capture flag B0" "Not occurred,Occurred" newline eventfld.word 0x04 7. " CFX1 ,Capture flag X1" "Not occurred,Occurred" eventfld.word 0x04 6. " CFX0 ,Capture flag X0" "Not occurred,Occurred" newline eventfld.word 0x04 5. " CMPF[5] ,Compare flag VAL5" "Not occurred,Occurred" eventfld.word 0x04 4. " CMPF[4] ,Compare flag VAL4" "Not occurred,Occurred" eventfld.word 0x04 3. " CMPF[3] ,Compare flag VAL3" "Not occurred,Occurred" eventfld.word 0x04 2. " CMPF[2] ,Compare flag VAL2" "Not occurred,Occurred" newline eventfld.word 0x04 1. " CMPF[1] ,Compare flag VAL1" "Not occurred,Occurred" eventfld.word 0x04 0. " CMPF[0] ,Compare flag VAL0" "Not occurred,Occurred" line.word 0x06 "INTEN,Interrupt Enable Register" bitfld.word 0x06 13. " REIE ,Reload error interrupt enable" "Disabled,Enabled" bitfld.word 0x06 12. " RIE ,Reload interrupt enable" "Disabled,Enabled" bitfld.word 0x06 11. " CA1IE ,Capture A1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 10. " CA0IE ,Capture A0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 9. " CB1IE ,Capture B1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 8. " CB0IE ,Capture B0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 7. " CX1IE ,Capture X1 interrupt enable" "Disabled,Enabled" bitfld.word 0x06 6. " CX0IE ,Capture X0 interrupt enable" "Disabled,Enabled" newline bitfld.word 0x06 5. " CMPIE5 ,Compare interrupt enable 5" "Disabled,Enabled" bitfld.word 0x06 4. " CMPIE4 ,Compare interrupt enable 4" "Disabled,Enabled" bitfld.word 0x06 3. " CMPIE3 ,Compare interrupt enable 3" "Disabled,Enabled" bitfld.word 0x06 2. " CMPIE2 ,Compare interrupt enable 2" "Disabled,Enabled" newline bitfld.word 0x06 1. " CMPIE1 ,Compare interrupt enable 1" "Disabled,Enabled" bitfld.word 0x06 0. " CMPIE0 ,Compare interrupt enable 0" "Disabled,Enabled" line.word 0x08 "DMAEN,DMA Enable Register" bitfld.word 0x08 9. " VALDE ,Value registers DMA enable" "Disabled,Enabled" bitfld.word 0x08 8. " FAND ,FIFO watermark AND control" "OR,AND" bitfld.word 0x08 6.--7. " CAPTDE ,Capture DMA enable source select" "Disabled,DMA Read,Local Sync,Local Reload" bitfld.word 0x08 5. " CA1DE ,Capture A1 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 4. " CA0DE ,Capture A0 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 3. " CB1DE ,Capture B1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 2. " CB0DE ,Capture B0 FIFO DMA enable" "Disabled,Enabled" newline bitfld.word 0x08 1. " CX1DE ,Capture X1 FIFO DMA enable" "Disabled,Enabled" bitfld.word 0x08 0. " CX0DE ,Capture X0 FIFO DMA enable" "Disabled,Enabled" line.word 0x0A "TCTRL,Output Trigger Control Register" bitfld.word 0x0A 15. " PWAOT0 ,Output trigger 0 source select" "PWM_OUT_TRIG0,PWMA output" bitfld.word 0x0A 14. " PWBOT1 ,Output trigger 1 source select" "PWM_OUT_TRIG1,PWMB output" bitfld.word 0x0A 5. " OUT_TRIG_EN[5] ,Output trigger 5 enable" "Disabled,Enabled" bitfld.word 0x0A 4. " [4] ,Output trigger 4 enable" "Disabled,Enabled" newline bitfld.word 0x0A 3. " [3] ,Output trigger 3 enable" "Disabled,Enabled" bitfld.word 0x0A 2. " [2] ,Output trigger 2 enable" "Disabled,Enabled" bitfld.word 0x0A 1. " [1] ,Output trigger 1 enable" "Disabled,Enabled" bitfld.word 0x0A 0. " [0] ,Output trigger 0 enable" "Disabled,Enabled" line.word 0x0C "DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x0C 11. " DIS0X_3 ,PWM_X fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 10. " DIS0X_2 ,PWM_X fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 9. " DIS0X_1 ,PWM_X fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 8. " DIS0X_0 ,PWM_X fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 7. " DIS0B_3 ,PWM_B fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 6. " DIS0B_2 ,PWM_B fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 5. " DIS0B_1 ,PWM_B fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 4. " DIS0B_0 ,PWM_B fault disable mask 0 bit 0" "Not masked,Masked" newline bitfld.word 0x0C 3. " DIS0A_3 ,PWM_A fault disable mask 0 bit 3" "Not masked,Masked" bitfld.word 0x0C 2. " DIS0A_2 ,PWM_A fault disable mask 0 bit 2" "Not masked,Masked" bitfld.word 0x0C 1. " DIS0A_1 ,PWM_A fault disable mask 0 bit 1" "Not masked,Masked" bitfld.word 0x0C 0. " DIS0A_0 ,PWM_A fault disable mask 0 bit 0" "Not masked,Masked" if (((per.l(ad:0x40033120+0x20)&0x04))==0x00) group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. " DTCNT0 ,Deadtime count register 0" else group.word 0x30++0x01 line.word 0x00 "DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 5.--15. 1. " DTCNT0_U ,Deadtime count register 0" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if (((per.l(ad:0x40033120+0x20)&0x10))==0x00) group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. " DTCNT1 ,Deadtime count register 1" else group.word 0x32++0x01 line.word 0x00 "DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 5.--15. 1. " DTCNT1 ,Deadtime count register 1" bitfld.word 0x00 0.--4. " DTCNT0_L ,Number of fractional cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x34++0x0B line.word 0x00 "CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. " CA1CNT ,Capture A1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x00 10.--12. " CA0CNT ,Capture A0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x00 8.--9. " CFAWM ,Capture A FIFOs water mark" "1,2,3,4" bitfld.word 0x00 7. " EDGCNTA_EN ,Edge counter A enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " INP_SELA ,Input select A" "Raw PWM_A,Counter/Compare" bitfld.word 0x00 4.--5. " EDGA1 ,Edge A1" "Disabled,Falling,Rising,Any" bitfld.word 0x00 2.--3. " EDGA0 ,Edge A0" "Disabled,Falling,Rising,Any" bitfld.word 0x00 1. " ONESHOTA ,One shot mode A" "Free run,One shot" newline bitfld.word 0x00 0. " ARMA ,Arm A" "Disabled,Enabled" line.word 0x02 "CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTA ,Edge counter A" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPA ,Edge Compare A" line.word 0x04 "CAPTCTRLB,Capture Control B Register" rbitfld.word 0x04 13.--15. " CB1CNT ,Capture B1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x04 10.--12. " CB0CNT ,Capture B0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x04 8.--9. " CFBWM ,Capture B FIFOs water mark" "1,2,3,4" bitfld.word 0x04 7. " EDGCNTB_EN ,Edge counter B enable" "Disabled,Enabled" newline bitfld.word 0x04 6. " INP_SELB ,Input select B" "Raw PWM_B,Counter/Compare" bitfld.word 0x04 4.--5. " EDGB1 ,Edge B1" "Disabled,Falling,Rising,Any" bitfld.word 0x04 2.--3. " EDGB0 ,Edge B0" "Disabled,Falling,Rising,Any" bitfld.word 0x04 1. " ONESHOTB ,One shot mode B" "Free run,One shot" newline bitfld.word 0x04 0. " ARMB ,Arm B" "Disabled,Enabled" line.word 0x06 "CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x06 8.--15. 1. " EDGCNTB ,Edge counter B" hexmask.word.byte 0x06 0.--7. 1. " EDGCMPB ,Edge compare B" line.word 0x08 "CAPTCTRLX,Capture Control X Register" rbitfld.word 0x08 13.--15. " CX1CNT ,Capture X1 FIFO word count" "1,2,3,4,5,6,7,8" rbitfld.word 0x08 10.--12. " CX0CNT ,Capture X0 FIFO word count" "1,2,3,4,5,6,7,8" bitfld.word 0x08 8.--9. " CFXWM ,Capture X FIFOs water mark" "1,2,3,4" bitfld.word 0x08 7. " EDGCNTX_EN ,Edge counter X enable" "Disabled,Enabled" newline bitfld.word 0x08 6. " INP_SELX ,Input select X" "Raw PWM_X,Counter/Compare" bitfld.word 0x08 4.--5. " EDGX1 ,Edge X1" "Disabled,Falling,Rising,Any" bitfld.word 0x08 2.--3. " EDGX0 ,Edge X0" "Disabled,Falling,Rising,Any" newline bitfld.word 0x08 1. " ONESHOTX ,One shot mode X" "Free run,One shot" bitfld.word 0x08 0. " ARMX ,Arm X" "Disabled,Enabled" line.word 0x0A "CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x02 8.--15. 1. " EDGCNTX ,Edge counter X" hexmask.word.byte 0x02 0.--7. 1. " EDGCMPX ,Edge compare X" rgroup.word 0x40++0x03 line.word 0x00 "CVAL0,Capture Value 0 Register" line.word 0x02 "CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x02 0.--3. " CVAL0CYC ,Cycle number corresponding to the value captured in CVAL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x44++0x03 line.word 0x00 "CVAL1,Capture Value 1 Register" line.word 0x02 "CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x02 0.--3. " CVAL1CYC ,Cycle number corresponding to the value captured in CVAL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x48++0x03 line.word 0x00 "CVAL2,Capture Value 2 Register" line.word 0x02 "CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x02 0.--3. " CVAL2CYC ,Cycle number corresponding to the value captured in CVAL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x4C++0x03 line.word 0x00 "CVAL3,Capture Value 3 Register" line.word 0x02 "CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x02 0.--3. " CVAL3CYC ,Cycle number corresponding to the value captured in CVAL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x50++0x03 line.word 0x00 "CVAL4,Capture Value 4 Register" line.word 0x02 "CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x02 0.--3. " CVAL4CYC ,Cycle number corresponding to the value captured in CVAL4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x54++0x03 line.word 0x00 "CVAL5,Capture Value 5 Register" line.word 0x02 "CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x02 0.--3. " CVAL5CYC ,Cycle number corresponding to the value captured in CVAL5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "COMMON" base ad:0x40033000 width 10. group.word 0x180++0x15 line.word 0x00 "OUTEN,Output Enable Register" bitfld.word 0x00 11. " PWMA_EN3 ,PWM_A output of submodule 3 enable" "Disabled,Enabled" bitfld.word 0x00 10. " PWMA_EN2 ,PWM_A output of submodule 2 enable" "Disabled,Enabled" bitfld.word 0x00 9. " PWMA_EN1 ,PWM_A output of submodule 1 enable" "Disabled,Enabled" bitfld.word 0x00 8. " PWMA_EN0 ,PWM_A output of submodule 0 enable" "Disabled,Enabled" newline bitfld.word 0x00 7. " PWMB_EN3 ,PWM_B output of submodule 3 enable" "Disabled,Enabled" bitfld.word 0x00 6. " PWMB_EN2 ,PWM_B output of submodule 2 enable" "Disabled,Enabled" bitfld.word 0x00 5. " PWMB_EN1 ,PWM_B output of submodule 1 enable" "Disabled,Enabled" bitfld.word 0x00 4. " PWMB_EN0 ,PWM_B output of submodule 0 enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " PWMX_EN3 ,PWM_X output of submodule 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " PWMX_EN2 ,PWM_X output of submodule 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " PWMX_EN1 ,PWM_X output of submodule 1 enable" "Disabled,Enabled" bitfld.word 0x00 0. " PWMX_EN0 ,PWM_X output of submodule 0 enable" "Disabled,Enabled" line.word 0x02 "MASK,Mask Register" bitfld.word 0x02 15. " UPDATE_MASK3 ,Update mask bit of PWM_X submodule 3 immediately" "No effect,Update" bitfld.word 0x02 14. " UPDATE_MASK2 ,Update mask bit of PWM_X submodule 2 immediately" "No effect,Update" bitfld.word 0x02 13. " UPDATE_MASK1 ,Update mask bit of PWM_X submodule 1 immediately" "No effect,Update" bitfld.word 0x02 12. " UPDATE_MASK0 ,Update mask bit of PWM_X submodule 0 immediately" "No effect,Update" newline bitfld.word 0x02 11. " MASKA3 ,PWM_A submodule 3 mask" "Normal,Masked" bitfld.word 0x02 10. " MASKA2 ,PWM_A submodule 2 mask" "Normal,Masked" bitfld.word 0x02 9. " MASKA1 ,PWM_A submodule 1 mask" "Normal,Masked" bitfld.word 0x02 8. " MASKA0 ,PWM_A submodule 0 mask" "Normal,Masked" newline bitfld.word 0x02 7. " MASKB3 ,PWM_B submodule 3 mask" "Normal,Masked" bitfld.word 0x02 6. " MASKB2 ,PWM_B submodule 2 mask" "Normal,Masked" bitfld.word 0x02 5. " MASKB1 ,PWM_B submodule 1 mask" "Normal,Masked" bitfld.word 0x02 4. " MASKB0 ,PWM_B submodule 0 mask" "Normal,Masked" newline bitfld.word 0x02 3. " MASKX3 ,PWM_X submodule 3 Mask" "Normal,Masked" bitfld.word 0x02 2. " MASKX2 ,PWM_X submodule 2 mask" "Normal,Masked" bitfld.word 0x02 1. " MASKX1 ,PWM_X submodule 1 mask" "Normal,Masked" bitfld.word 0x02 0. " MASKX0 ,PWM_X submodule 0 mask" "Normal,Masked" line.word 0x04 "SWCOUT,Software Controlled Output Register" bitfld.word 0x04 7. " SM3OUT23 ,Submodule 3 software controlled output 23" "Logic 0,Logic 1" bitfld.word 0x04 6. " SM3OUT45 ,Submodule 3 software controlled output 45" "Logic 0,Logic 1" bitfld.word 0x04 5. " SM2OUT23 ,Submodule 2 software controlled output 23" "Logic 0,Logic 1" bitfld.word 0x04 4. " SM2OUT45 ,Submodule 2 software controlled output 45" "Logic 0,Logic 1" newline bitfld.word 0x04 3. " SM1OUT23 ,Submodule 1 software controlled output 23" "Logic 0,Logic 1" bitfld.word 0x04 2. " SM1OUT45 ,Submodule 1 software controlled output 45" "Logic 0,Logic 1" bitfld.word 0x04 1. " SM0OUT23 ,Submodule 0 software controlled output 23" "Logic 0,Logic 1" bitfld.word 0x04 0. " SM0OUT45 ,Submodule 0 software controlled output 45" "Logic 0,Logic 1" line.word 0x06 "DTSRCSEL,PWM Source Select Register" bitfld.word 0x06 14.--15. " SM3SEL23 ,Submodule 3 PWM23 control select" "SM3PWM23,Inverted SM3PWM23,SWCOUT[SM3OUT23],PWM3_EXTA" bitfld.word 0x06 12.--13. " SM3SEL45 ,Submodule 3 PWM45 control select" "SM3PWM45,Inverted SM3PWM45,SWCOUT[SM3OUT45],PWM3_EXTB" bitfld.word 0x06 10.--11. " SM2SEL23 ,Submodule 2 PWM23 control select" "SM2PWM23,Inverted SM2PWM23,SWCOUT[SM2OUT23],PWM2_EXTA" bitfld.word 0x06 8.--9. " SM2SEL45 ,Submodule 2 PWM45 control select" "SM2PWM45,Inverted SM2PWM45,SWCOUT[SM2OUT45],PWM2_EXTB" newline bitfld.word 0x06 6.--7. " SM1SEL23 ,Submodule 1 PWM23 control select" "SM1PWM23,Inverted SM1PWM23,SWCOUT[SM1OUT23],PWM1_EXTA" bitfld.word 0x06 4.--5. " SM1SEL45 ,Submodule 1 PWM45 control select" "SM1PWM45,Inverted SM1PWM45,SWCOUT[SM1OUT45],PWM1_EXTB" bitfld.word 0x06 2.--3. " SM0SEL23 ,Submodule 0 PWM23 control select" "SM0PWM23,Inverted SM0WM23,SWCOUT[SM0OUT23],PWM0_EXTA" bitfld.word 0x06 0.--1. " SM0SEL45 ,Submodule 0 PWM45 control select" "SM0PWM45,Inverted SM0PWM45,SWCOUT[SM0OUT45],PWM0_EXTB" line.word 0x08 "MCTRL,Master Control Register" bitfld.word 0x08 15. " IPOL3 ,Current polarity of submodule 3" "PWM23,PWM45" bitfld.word 0x08 14. " IPOL2 ,Current polarity of submodule 2" "PWM23,PWM45" newline bitfld.word 0x08 13. " IPOL1 ,Current polarity of submodule 1" "PWM23,PWM45" bitfld.word 0x08 12. " IPOL0 ,Current polarity of submodule 0" "PWM23,PWM45" newline bitfld.word 0x08 11. " RUN3 , PWM generator of submodule 3" "Disabled,Enabled" bitfld.word 0x08 10. " RUN2 , PWM generator of submodule 2" "Disabled,Enabled" newline bitfld.word 0x08 9. " RUN1 , PWM generator of submodule 1" "Disabled,Enabled" bitfld.word 0x08 8. " RUN0 , PWM generator of submodule 0" "Disabled,Enabled" newline eventfld.word 0x08 7. " CLDOK3 ,Clear load okay of submodule 3" "Not occurred,Occurred" eventfld.word 0x08 6. " CLDOK2 ,Clear load okay of submodule 2" "Not occurred,Occurred" newline eventfld.word 0x08 5. " CLDOK1 ,Clear load okay of submodule 1" "Not occurred,Occurred" eventfld.word 0x08 4. " CLDOK0 ,Clear load okay of submodule 0" "Not occurred,Occurred" newline bitfld.word 0x08 3. " LDOK3 ,Load okay of submodule 3" "Not load,Load" bitfld.word 0x08 2. " LDOK2 ,Load okay of submodule 2" "Not load,Load" newline bitfld.word 0x08 1. " LDOK1 ,Load okay of submodule 1" "Not load,Load" bitfld.word 0x08 0. " LDOK0 ,Load okay of submodule 0" "Not load,Load" line.word 0x0A "MCTRL2,Master Control 2 Register" bitfld.word 0x0A 0.--1. " MONPLL ,Monitor PLL state" "Not locked(Do not monitor),Not locked(Monitor),Locked(Do not monitor),Locked(Monitor)" line.word 0x0C "FCTRL,Fault Control Register" bitfld.word 0x0C 15. " FLVL3 ,Fault 3 level" "Logic 0,Logic 1" bitfld.word 0x0C 14. " FLVL2 ,Fault 2 level" "Logic 0,Logic 1" bitfld.word 0x0C 13. " FLVL1 ,Fault 1 level" "Logic 0,Logic 1" bitfld.word 0x0C 12. " FLVL0 ,Fault 0 level" "Logic 0,Logic 1" newline bitfld.word 0x0C 11. " FAUTO3 ,Automatic fault clearing 3" "Manual,Automatic" bitfld.word 0x0C 10. " FAUTO2 ,Automatic fault clearing 2" "Manual,Automatic" bitfld.word 0x0C 9. " FAUTO1 ,Automatic fault clearing 1" "Manual,Automatic" bitfld.word 0x0C 8. " FAUTO0 ,Automatic fault clearing 0" "Manual,Automatic" newline bitfld.word 0x0C 7. " FSAFE3 ,Fault safety mode 3" "Normal,Safe" bitfld.word 0x0C 6. " FSAFE2 ,Fault safety mode 2" "Normal,Safe" bitfld.word 0x0C 5. " FSAFE1 ,Fault safety mode 1" "Normal,Safe" bitfld.word 0x0C 4. " FSAFE0 ,Fault safety mode 0" "Normal,Safe" newline bitfld.word 0x0C 3. " FIE3 ,Fault interrupt enable 3" "Disabled,Enabled" bitfld.word 0x0C 2. " FIE2 ,Fault interrupt enable 2" "Disabled,Enabled" bitfld.word 0x0C 1. " FIE1 ,Fault interrupt enable 1" "Disabled,Enabled" bitfld.word 0x0C 0. " FIE0 ,Fault interrupt enable 0" "Disabled,Enabled" line.word 0x0E "FSTS,Fault Status Register" bitfld.word 0x0E 15. " FHALF3 ,Half cycle fault 3 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 14. " FHALF2 ,Half cycle fault 2 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 13. " FHALF1 ,Half cycle fault 1 recovery" "Not re-enabled,Re-enabled" bitfld.word 0x0E 12. " FHALF0 ,Half cycle fault 0 recovery" "Not re-enabled,Re-enabled" newline rbitfld.word 0x0E 11. " FFPIN3 ,Filtered fault pin 3" "Not occurred,Occurred" rbitfld.word 0x0E 10. " FFPIN2 ,Filtered fault pin 2" "Not occurred,Occurred" rbitfld.word 0x0E 9. " FFPIN1 ,Filtered fault pin 1" "Not occurred,Occurred" rbitfld.word 0x0E 8. " FFPIN0 ,Filtered fault pin 0" "Not occurred,Occurred" newline bitfld.word 0x0E 7. " FFULL3 ,Full cycle 3" "Not re-enabled,Re-enabled" bitfld.word 0x0E 6. " FFULL2 ,Full cycle 2" "Not re-enabled,Re-enabled" bitfld.word 0x0E 5. " FFULL1 ,Full cycle 1" "Not re-enabled,Re-enabled" bitfld.word 0x0E 4. " FFULL0 ,Full cycle 0" "Not re-enabled,Re-enabled" newline eventfld.word 0x0E 3. " FFLAG3 ,Fault flag 3" "Not fault,Fault" eventfld.word 0x0E 2. " FFLAG2 ,Fault flag 2" "Not fault,Fault" eventfld.word 0x0E 1. " FFLAG1 ,Fault flag 1" "Not fault,Fault" eventfld.word 0x0E 0. " FFLAG0 ,Fault flag 0" "Not fault,Fault" line.word 0x10 "FFILT,Fault Filter Register" bitfld.word 0x10 15. " GSTR ,Fault glitch stretch enable" "Disabled,Enabled" bitfld.word 0x10 8.--10. " FILT_CNT ,Fault filter count" "3,4,5,6,7,8,9,10" hexmask.word.byte 0x10 0.--7. 1. " FILT_PER ,Fault filter period" line.word 0x12 "FTST,Fault Test Register" bitfld.word 0x12 0. " FTEST ,Fault test" "Not fault,Simulated Fault" line.word 0x14 "FCTRL2,Fault Control 2 Register" bitfld.word 0x14 3. " NOCOMB3 ,No combinational path from fault input to PWM output" "No,Yes" bitfld.word 0x14 2. " NOCOMB2 ,No combinational path from fault input to PWM output" "No,Yes" bitfld.word 0x14 1. " NOCOMB1 ,No combinational path from fault input to PWM output" "No,Yes" newline bitfld.word 0x14 0. " NOCOMB0 ,No combinational path from fault input to PWM output" "No,Yes" width 0x0B tree.end tree.end tree.open "PDB (Programmable Delay Block)" tree "PDB_1" base ad:0x40031000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH4 (done),DMA CH5 (done),DMA CH6 (done),DMA CH7 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 19. " CF[3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " CF[2] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 3. " ERR[3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " ERR[2] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 3. " POEN[3] ,PDB Pulse out enable" "Disabled,Enabled" bitfld.long 0x00 2. " POEN[2] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x3 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x3 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB tree.end tree "PDB_0" base ad:0x40036000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN128VLH10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN256VFT12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN256VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN256VLH12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN256VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0,TPM1,TPM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" ",CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,FTM5,LPTMR output,Software trigger" elif cpuis("MKV10Z128VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z64VLF7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB_EXTRG0,CMP 0,CMP 1,PDB_EXTRG1,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,FTM3,FTM4,,LPTMR output,Software trigger" elif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP 0,CMP 1,,DMA CH0 (done),DMA CH1 (done),DMA CH2 (done),DMA CH3 (done),FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,,,,LPTMR output,Software trigger" elif cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,FTM2,FTM3,,,LPTMR output,Software trigger" elif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT CH0 OUT,PIT CH1 OUT,PIT CH2 OUT,PIT CH3 OUT,FTM0,FTM1,,FTM3,XBAR_OUT 38,,LPTMR output,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" bitfld.long 0x04 19. " CF[3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " CF[2] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 3. " ERR[3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " ERR[2] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") group.long 0x20++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 1 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 1 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 3. " POEN[3] ,PDB Pulse out enable" "Disabled,Enabled" bitfld.long 0x00 2. " POEN[2] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 1. " POEN[1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" group.long 0x194++0x3 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x3 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x3 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x3 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" width 0xB tree.end tree.end tree.open "FTM (FlexTimer Module)" tree "FTM_3" base ad:0x40026000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM3_SC,FTM3 Status And Control Register" in newline else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM3_SC,FTM3 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM3_CNT,FTM3 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM3_MOD,FTM3 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM3_C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM3_C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM3_C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM3_C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM3_C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM3_C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM3_C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM3_C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM3_C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM3_CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM3_STATUS,FTM3 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM3_MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM3_SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM3_OUTINIT,FTM3 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM3_OUTMASK,FTM3 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM3_COMBINE,FTM3 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM3_DEADTIME,FTM3 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM3_EXTTRIG,FTM3 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM3_POL,FTM3 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM3_FMS,FTM3 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM3_FILTER,FTM3 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM3_FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM3_QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM3_CONF,FTM3 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM3_FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM3_SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM3_INVCTRL,FTM3 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM3_SWOCTRL,FTM3 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM3_PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree "FTM_1" base ad:0x40029000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM1_SC,FTM1 Status And Control Register" in newline else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM1_SC,FTM1 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM1_CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM1_MOD,FTM1 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM1_C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM1_C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM1_C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM1_CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM1_STATUS,FTM1 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM1_MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM1_SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM1_OUTINIT,FTM1 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM1_OUTMASK,FTM1 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM1_COMBINE,FTM1 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM1_DEADTIME,FTM1 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM1_EXTTRIG,FTM1 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM1_POL,FTM1 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM1_FMS,FTM1 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM1_FILTER,FTM1 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM1_FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM1_QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM1_CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM1_FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM1_SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM1_INVCTRL,FTM1 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM1_SWOCTRL,FTM1 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM1_PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree "FTM_0" base ad:0x40028000 width 18. sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x00++0x03 hide.long 0x00 "FTM0_SC,FTM0 Status And Control Register" in newline else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "FTM0_SC,FTM0 Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "FTM0_CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "FTM0_MOD,FTM0 Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x0++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in newline group.long (0x0+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long (0x0+0x0C)++0x07 line.long 0x00 "FTM0_C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x8++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in newline group.long (0x8+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long (0x8+0x0C)++0x07 line.long 0x00 "FTM0_C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x10++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in newline group.long (0x10+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long (0x10+0x0C)++0x07 line.long 0x00 "FTM0_C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x18++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in newline group.long (0x18+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long (0x18+0x0C)++0x07 line.long 0x00 "FTM0_C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x20++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in newline group.long (0x20+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long (0x20+0x0C)++0x07 line.long 0x00 "FTM0_C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x28++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in newline group.long (0x28+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long (0x28+0x0C)++0x07 line.long 0x00 "FTM0_C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x30++0x03 hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" in newline group.long (0x30+0x04)++0x03 line.long 0x00 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long (0x30+0x0C)++0x07 line.long 0x00 "FTM0_C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif endif sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x38++0x03 hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" in newline group.long (0x38+0x04)++0x03 line.long 0x00 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" rbitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long (0x38+0x0C)++0x07 line.long 0x00 "FTM0_C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" newline bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" bitfld.long 0x00 1. " ICRST ,FTM counter reset by the selected input capture event" "No reset,Reset" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "FTM0_C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif endif group.long 0x4C++0x03 line.long 0x00 "FTM0_CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" sif cpuis("MKV5*")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline hgroup.long 0x50++0x03 hide.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" in newline else rgroup.long 0x50++0x03 line.long 0x00 "FTM0_STATUS,FTM0 Capture And Compare Status Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" newline endif bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "FTM0_MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even chn/man. CLR,All chn/man. CLR,All chn/auto CLR" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/hardware triggers usage)" "No,Yes" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "FTM0_SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "FTM0_OUTINIT,FTM0 Initial State For Channels Output Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" newline endif bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "FTM0_OUTMASK,FTM0 Output Mask Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" newline endif bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "FTM0_COMBINE,FTM0 Function For Linked Channels Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" newline endif bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" newline bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 comp. CH6" bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" bitfld.long 0x00 20. " DTEN2 ,Deadtime enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 comp. CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" newline bitfld.long 0x00 12. " DTEN1 ,Deadtime enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 comp. CH2" newline bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 comp. CH0" bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "FTM0_DEADTIME,FTM0 Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "FTM0_EXTTRIG,FTM0 External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL[5] ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "FTM0_POL,FTM0 Channels Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" newline endif bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" newline bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FTM0_FMS,FTM0 Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FTM0_FILTER,FTM0 Input Capture Filter Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FTM0_FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" endif newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" else newline bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" endif newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "FTM0_QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" newline bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->max,Max->min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "FTM0_CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/functional,Stopped/forced to safe value,Stopped/frozen,Functional/functional" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40026000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif else group.long 0x88++0x03 line.long 0x00 "FTM0_FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" endif newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif endif group.long 0x8C++0x0F line.long 0x00 "FTM0_SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (Hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (Hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (Software trigger)" "Not activated,Activated" newline bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (Software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Sysclk rising,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Sysclk rising,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "FTM0_INVCTRL,FTM0 Inverting Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" endif newline bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" else bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" endif line.long 0x08 "FTM0_SWOCTRL,FTM0 Software Output Control Register" sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" endif newline bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline else bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" newline bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline endif sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" newline endif bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "FTM0_PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline sif cpuis("MKV30F64VLF10*")||cpuis("MKV30F128VLF10P")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") sif !cpuis("MKV30F64VLF10*")&&!cpuis("MKV30F128VLF10P") bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" endif newline bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" newline bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif width 0x0B tree.end tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x40037000 width 9. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" sif cpuis("MKV5*") rgroup.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" endif group.long 0x100++0x03 "PIT0 Registers" line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register" rgroup.long (0x100+0x04)++0x03 line.long 0x00 "CVAL0,PIT0 Current Timer Value Register" group.long (0x100+0x08)++0x07 line.long 0x00 "TCTRL0,PIT0 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG0,PIT0 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x110++0x03 "PIT1 Registers" line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register" rgroup.long (0x110+0x04)++0x03 line.long 0x00 "CVAL1,PIT1 Current Timer Value Register" group.long (0x110+0x08)++0x07 line.long 0x00 "TCTRL1,PIT1 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG1,PIT1 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x120++0x03 "PIT2 Registers" line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register" rgroup.long (0x120+0x04)++0x03 line.long 0x00 "CVAL2,PIT2 Current Timer Value Register" group.long (0x120+0x08)++0x07 line.long 0x00 "TCTRL2,PIT2 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG2,PIT2 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" group.long 0x130++0x03 "PIT3 Registers" line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register" rgroup.long (0x130+0x04)++0x03 line.long 0x00 "CVAL3,PIT3 Current Timer Value Register" group.long (0x130+0x08)++0x07 line.long 0x00 "TCTRL3,PIT3 Timer Control Register" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "TFLG3,PIT3 Timer Flag Register" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "No interrupt,Interrupt" width 0x0B tree.end tree "ENC (Quadrature Encoder/Decoder)" base ad:0x40055000 width 8. group.word 0x00++0x07 line.word 0x00 "CTRL,Control Register" eventfld.word 0x00 15. " HIRQ ,HOME signal transition interrupt request" "No interrupt,Interrupt" bitfld.word 0x00 14. " HIE ,HOME interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " HIP ,Enable HOME to initialize position counters UPOS and LPOS" "Disabled,Enabled" newline bitfld.word 0x00 12. " HNE ,Use negative edge of HOME input" "Positive,Negative" bitfld.word 0x00 11. " SWIP ,Software triggered initialization of position counters UPOS and LPOS" "No,Yes" bitfld.word 0x00 10. " REV ,Enable reverse direction counting" "Normal,Reverse" newline bitfld.word 0x00 9. " PH1 ,Enable signal phase count mode" "Disabled,Enabled" eventfld.word 0x00 8. " XIRQ ,INDEX pulse interrupt request" "Not occurred,Occurred" bitfld.word 0x00 7. " XIE ,INDEX pulse interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 6. " XIP ,INDEX triggered initialization of position counters UPOS and LPOS" "No,Yes" bitfld.word 0x00 5. " XNE ,Use negative edge of index pulse" "Positive,Negative" eventfld.word 0x00 4. " DIRQ ,Watchdog timeout interrupt request" "Not occurred,Occurred" newline bitfld.word 0x00 3. " DIE ,Watchdog timeout interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" eventfld.word 0x00 1. " CMPIRQ ,Compare interrupt request" "Not occurred,Occurred" newline bitfld.word 0x00 0. " CMPIE ,Compare interrupt enable" "Disabled,Enabled" line.word 0x02 "FILT,Input Filter Register" bitfld.word 0x02 8.--10. " CNT ,Input filter sample count" "3,4,5,6,7,8,9,10" hexmask.word.byte 0x02 0.--7. 1. " PER ,Input filter sample period" line.word 0x04 "WTR,Watchdog Timeout Register" line.word 0x06 "POSD,Position Difference Counter" rgroup.word 0x08++0x01 line.word 0x00 "POSDH,Position Difference Hold Register" group.word 0x0A++0x01 line.word 0x00 "REV,Revolution Counter Register" rgroup.word 0x0C++0x01 line.word 0x00 "REVH,Revolution Hold Register" group.word 0x0E++0x03 line.word 0x00 "UPOS,Upper Position Counter Register" line.word 0x02 "LPOS,Lower Position Counter Register" rgroup.word 0x12++0x03 line.word 0x00 "UPOSH,Upper Position Hold Register" line.word 0x02 "LPOSH,Lower Position Hold Register" group.word 0x16++0x03 line.word 0x00 "UINIT,Upper Initialization Register" line.word 0x02 "LINIT,Lower Initialization Register" rgroup.word 0x1A++0x01 line.word 0x00 "IMR,Input Monitor Register" bitfld.word 0x00 7. " FPHA ,Filtered version of PHASEA input" "0,1" bitfld.word 0x00 6. " FPHB ,Filtered version of PHASEB input" "0,1" bitfld.word 0x00 5. " FIND ,Filtered version of INDEX input" "0,1" newline bitfld.word 0x00 4. " FHOM ,Filtered version of HOME input" "0,1" bitfld.word 0x00 3. " PHA ,Raw PHASEA input" "0,1" bitfld.word 0x00 2. " PHB ,Raw PHASEB input" "0,1" newline bitfld.word 0x00 1. " INDEX ,Raw INDEX input" "0,1" bitfld.word 0x00 0. " HOME ,Raw HOME input" "0,1" group.word 0x1C++0x0B line.word 0x00 "TST,Test Register" bitfld.word 0x00 15. " TEN ,Test mode enable" "Disabled,Enabled" bitfld.word 0x00 14. " TCE ,Test counter enable" "Disabled,Enabled" bitfld.word 0x00 13. " QDN ,Quadrature decoder negative signal" "Positive,Negative" newline bitfld.word 0x00 8.--12. " TEST_PERIOD ,These bits hold the period of quadrature phase in IPBus clock cycles" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" hexmask.word.byte 0x00 0.--7. 1. " TEST_COUNT ,These bits hold the number of quadrature advances to generate" line.word 0x02 "CTRL2,Control 2 Register" sif (cpuis("MKV5*"))||cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") eventfld.word 0x02 11. " SABIRQ , Indicates that the PHASEA and PHASEB inputs changed simultaneously" "Not occurred,Occurred" bitfld.word 0x02 10. " SABIE ,Simultaneous PHASEA and PHASEB change interrupt enable" "Disabled,Enabled" bitfld.word 0x02 9. " OUTCTL ,Output control" "On match,On read" newline bitfld.word 0x02 8. " REVMOD ,Revolution counter modulus enable" "INDEX pulse,Roll-over/under" eventfld.word 0x02 7. " ROIRQ ,Roll-over interrupt request" "Not occurred,Occurred" bitfld.word 0x02 6. " ROIE ,Roll-over interrupt enable" "Disabled,Enabled" newline eventfld.word 0x02 5. " RUIRQ ,Roll-under interrupt request" "Not occurred,Occurred" bitfld.word 0x02 4. " RUIE ,Roll-under interrupt enable" "Disabled,Enabled" rbitfld.word 0x02 3. " DIR ,Count direction flag" "Down,Up" newline bitfld.word 0x02 2. " MOD ,Enable modulo counting" "Disabled,Enabled" bitfld.word 0x02 1. " UPDPOS ,Update position registers" "Not cleared,Cleared" bitfld.word 0x02 0. " UPDHLD ,Update hold registers" "Disabled,Enabled" else bitfld.word 0x02 9. " OUTCTL ,Output control" "On match,On read" bitfld.word 0x02 8. " REVMOD ,Revolution counter modulus enable" "INDEX pulse,Roll-over/under" eventfld.word 0x02 7. " ROIRQ ,Roll-over interrupt request" "Not occurred,Occurred" newline bitfld.word 0x02 6. " ROIE ,Roll-over interrupt enable" "Disabled,Enabled" eventfld.word 0x02 5. " RUIRQ ,Roll-under interrupt request" "Not occurred,Occurred" bitfld.word 0x02 4. " RUIE ,Roll-under interrupt enable" "Disabled,Enabled" newline rbitfld.word 0x02 3. " DIR ,Count direction flag" "Down,Up" bitfld.word 0x02 2. " MOD ,Enable modulo counting" "Disabled,Enabled" bitfld.word 0x02 1. " UPDPOS ,Update position registers" "Not cleared,Cleared" newline bitfld.word 0x02 0. " UPDHLD ,Update hold registers" "No,Yes" endif line.word 0x04 "UMOD,Upper Modulus Register" line.word 0x06 "LMOD,Lower Modulus Register" line.word 0x08 "UCOMP,Upper Position Compare Register" line.word 0x0A "LCOMP,Lower Position Compare Register" width 0x0B tree.end tree "LPTMR (Low-Power Timer)" base ad:0x40040000 width 5. if (((per.l(ad:0x40040000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP0 OUT,LPTMR_ALT1,LPTMR_ALT2,LPTMR_ALT3" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x40040000))&0x01)==0x00) if (((per.l(ad:0x40040000))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif else if (((per.l(ad:0x40040000))&0x02)==0x00) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" sif cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK_UNDIV" elif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R") bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO,ERCLK32K,OSCERCLK" else bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif endif if (((per.l(ad:0x40040000))&0x01)==0x00)||(((per.l(ad:0x40040000))&0x81)==0x81) group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif else rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif sif cpuis("MKV5*")||cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7*")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV11Z128VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV11Z64VFM7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z64VLH7")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*")||cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV31F512VLL12P")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16*") group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree.open "FlexCAN (Flex Controller Area Network)" tree "CAN_0" base ad:0x40024000 width 15. if ((per.l(ad:0x40024000)&0x40000000)==0x00) group.long 0x00++0x07 line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline rbitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" rbitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" rbitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline rbitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" rbitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" rbitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline rbitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" else group.long 0x00++0x07 line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" endif group.long 0x08++0x03 line.long 0x00 "CAN0_TIMER,CAN0 Free Running Timer Register" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN0_RX14MASK,CAN0 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN0_RX15MASK,CAN0 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN0_RXMGMASK,CAN0 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN0_RX14MASK,CAN0 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN0_RX15MASK,CAN0 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "CAN0_ESR1,CAN0 Error and Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "CAN0_IMASK1,CAN0 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF31M ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BUF30M ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " BUF29M ,Buffer MB29 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 28. " BUF28M ,Buffer MB28 interrupt mask" "Masked,Not masked" bitfld.long 0x00 27. " BUF27M ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " BUF26M ,Buffer MB26 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 25. " BUF25M ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " BUF24M ,Buffer MB24 interrupt mask" "Masked,Not masked" bitfld.long 0x00 23. " BUF23M ,Buffer MB23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 22. " BUF22M ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " BUF21M ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " BUF20M ,Buffer MB20 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 19. " BUF19M ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " BUF18M ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " BUF17M ,Buffer MB17 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 16. " BUF16M ,Buffer MB16 interrupt mask" "Masked,Not masked" bitfld.long 0x00 15. " BUF15M ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " BUF14M ,Buffer MB14 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 13. " BUF13M ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " BUF12M ,Buffer MB12 interrupt mask" "Masked,Not masked" bitfld.long 0x00 11. " BUF11M ,Buffer MB11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 10. " BUF10M ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " BUF9M ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " BUF8M ,Buffer MB8 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 7. " BUF7M ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " BUF6M ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " BUF5M ,Buffer MB5 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 4. " BUF4M ,Buffer MB4 interrupt mask" "Masked,Not masked" bitfld.long 0x00 3. " BUF3M ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " BUF2M ,Buffer MB2 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 1. " BUF1M ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " BUF0M ,Buffer MB0 interrupt mask" "Masked,Not masked" if ((per.l(ad:0x40024000)&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " BUF7I ,Buffer MB7 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " BUF6I ,Buffer MB6 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " BUF5I ,Buffer MB5 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " BUF4I ,Buffer MB4 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " BUF3I ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BUF2I ,Buffer MB2 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " BUF1I ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" else group.long 0x30++0x03 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " RFO ,RX FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " RFW ,RX FIFO warning" "Not full,Almost full" eventfld.long 0x00 5. " FARF ,Frames available in RX FIFO" "Not available,Available" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" endif if ((per.l(ad:0x40024000)&0x40000000)==0x00) group.long 0x34++0x03 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" endif rgroup.long 0x38++0x03 line.long 0x00 "CAN0_ESR2,CAN0 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No,Yes" rgroup.long 0x44++0x03 line.long 0x00 "CAN0_CRCR,CAN0 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x40024000)&0x40000000)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "CAN0_RXFGMASK,CAN0 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" else group.long 0x48++0x03 line.long 0x00 "CAN0_RXFGMASK,CAN0 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "CAN0_RXFIR,CAN0 RX FIFO Information Register" in newline if ((per.l(ad:0x40024000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN0 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN0_CBT,CAN0 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" endif tree "CAN0 RX Individual Mask Registers $2" width 14. if (((per.l(ad:0x40024000))&0x40000000)==0x40000000) group.long 0x880++0x03 line.long 0x00 "CAN0_RXIMR0,CAN0 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x884++0x03 line.long 0x00 "CAN0_RXIMR1,CAN0 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x888++0x03 line.long 0x00 "CAN0_RXIMR2,CAN0 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x88C++0x03 line.long 0x00 "CAN0_RXIMR3,CAN0 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x890++0x03 line.long 0x00 "CAN0_RXIMR4,CAN0 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x894++0x03 line.long 0x00 "CAN0_RXIMR5,CAN0 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x898++0x03 line.long 0x00 "CAN0_RXIMR6,CAN0 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x89C++0x03 line.long 0x00 "CAN0_RXIMR7,CAN0 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A0++0x03 line.long 0x00 "CAN0_RXIMR8,CAN0 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A4++0x03 line.long 0x00 "CAN0_RXIMR9,CAN0 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A8++0x03 line.long 0x00 "CAN0_RXIMR10,CAN0 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8AC++0x03 line.long 0x00 "CAN0_RXIMR11,CAN0 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B0++0x03 line.long 0x00 "CAN0_RXIMR12,CAN0 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B4++0x03 line.long 0x00 "CAN0_RXIMR13,CAN0 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B8++0x03 line.long 0x00 "CAN0_RXIMR14,CAN0 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8BC++0x03 line.long 0x00 "CAN0_RXIMR15,CAN0 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" else rgroup.long 0x880++0x03 line.long 0x00 "CAN0_RXIMR0,CAN0 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x884++0x03 line.long 0x00 "CAN0_RXIMR1,CAN0 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x888++0x03 line.long 0x00 "CAN0_RXIMR2,CAN0 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x88C++0x03 line.long 0x00 "CAN0_RXIMR3,CAN0 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x890++0x03 line.long 0x00 "CAN0_RXIMR4,CAN0 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x894++0x03 line.long 0x00 "CAN0_RXIMR5,CAN0 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x898++0x03 line.long 0x00 "CAN0_RXIMR6,CAN0 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x89C++0x03 line.long 0x00 "CAN0_RXIMR7,CAN0 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A0++0x03 line.long 0x00 "CAN0_RXIMR8,CAN0 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A4++0x03 line.long 0x00 "CAN0_RXIMR9,CAN0 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A8++0x03 line.long 0x00 "CAN0_RXIMR10,CAN0 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8AC++0x03 line.long 0x00 "CAN0_RXIMR11,CAN0 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B0++0x03 line.long 0x00 "CAN0_RXIMR12,CAN0 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B4++0x03 line.long 0x00 "CAN0_RXIMR13,CAN0 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B8++0x03 line.long 0x00 "CAN0_RXIMR14,CAN0 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8BC++0x03 line.long 0x00 "CAN0_RXIMR15,CAN0 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" endif tree.end tree "CAN0 Message Buffer Structure" group.long 0x80++0x0F line.long 0x00 "MB0_0,Message Buffer 0 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB0_1,Message Buffer 0 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB0_2,Message Buffer 0 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB0_3,Message Buffer 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x90++0x0F line.long 0x00 "MB1_0,Message Buffer 1 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB1_1,Message Buffer 1 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB1_2,Message Buffer 1 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB1_3,Message Buffer 1 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xA0++0x0F line.long 0x00 "MB2_0,Message Buffer 2 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB2_1,Message Buffer 2 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB2_2,Message Buffer 2 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB2_3,Message Buffer 2 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xB0++0x0F line.long 0x00 "MB3_0,Message Buffer 3 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB3_1,Message Buffer 3 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB3_2,Message Buffer 3 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB3_3,Message Buffer 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xC0++0x0F line.long 0x00 "MB4_0,Message Buffer 4 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB4_1,Message Buffer 4 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB4_2,Message Buffer 4 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB4_3,Message Buffer 4 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xD0++0x0F line.long 0x00 "MB5_0,Message Buffer 5 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB5_1,Message Buffer 5 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB5_2,Message Buffer 5 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB5_3,Message Buffer 5 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xE0++0x0F line.long 0x00 "MB6_0,Message Buffer 6 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB6_1,Message Buffer 6 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB6_2,Message Buffer 6 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB6_3,Message Buffer 6 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xF0++0x0F line.long 0x00 "MB7_0,Message Buffer 7 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB7_1,Message Buffer 7 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB7_2,Message Buffer 7 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB7_3,Message Buffer 7 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x100++0x0F line.long 0x00 "MB8_0,Message Buffer 8 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB8_1,Message Buffer 8 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB8_2,Message Buffer 8 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB8_3,Message Buffer 8 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x110++0x0F line.long 0x00 "MB9_0,Message Buffer 9 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB9_1,Message Buffer 9 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB9_2,Message Buffer 9 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB9_3,Message Buffer 9 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x120++0x0F line.long 0x00 "MB10_0,Message Buffer 10 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB10_1,Message Buffer 10 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB10_2,Message Buffer 10 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB10_3,Message Buffer 10 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x130++0x0F line.long 0x00 "MB11_0,Message Buffer 11 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB11_1,Message Buffer 11 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB11_2,Message Buffer 11 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB11_3,Message Buffer 11 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x140++0x0F line.long 0x00 "MB12_0,Message Buffer 12 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB12_1,Message Buffer 12 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB12_2,Message Buffer 12 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB12_3,Message Buffer 12 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x150++0x0F line.long 0x00 "MB13_0,Message Buffer 13 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB13_1,Message Buffer 13 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB13_2,Message Buffer 13 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB13_3,Message Buffer 13 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x160++0x0F line.long 0x00 "MB14_0,Message Buffer 14 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB14_1,Message Buffer 14 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB14_2,Message Buffer 14 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB14_3,Message Buffer 14 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x170++0x0F line.long 0x00 "MB15_0,Message Buffer 15 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB15_1,Message Buffer 15 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB15_2,Message Buffer 15 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB15_3,Message Buffer 15 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline tree.end width 0x0B tree.end tree "CAN_1" base ad:0x40025000 width 15. if ((per.l(ad:0x40025000)&0x40000000)==0x00) group.long 0x00++0x07 line.long 0x00 "CAN1_MCR,CAN1 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" rbitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" rbitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" rbitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline rbitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline rbitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" rbitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline rbitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" rbitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN1_CTRL1,CAN1 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" rbitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" rbitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline rbitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" rbitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" rbitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline rbitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" rbitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" rbitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline rbitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" else group.long 0x00++0x07 line.long 0x00 "CAN1_MCR,CAN1 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,RX FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN not ready" "Ready,Not ready" bitfld.long 0x00 26. " WAKMSK ,Wake up interrupt mask" "Disabled,Enabled" newline bitfld.long 0x00 25. " SOFTRST ,Soft reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZACK ,Freeze mode acknowledge" "Not freezed,Freezed" bitfld.long 0x00 23. " SUPV ,Supervisor mode" "User,Supervisor" newline bitfld.long 0x00 22. " SLFWAK ,Self wake up enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRNEN ,Warning interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPMACK ,Low power mode acknowledge" "Not LPM,LPM" newline bitfld.long 0x00 19. " WAKSRC ,Wake up source" "Unfiltered RX,Filtered RX" bitfld.long 0x00 18. " DOZE ,Doze mode enable" "Disabled,Enabled" bitfld.long 0x00 17. " SRXDIS ,Self reception disable" "No,Yes" newline bitfld.long 0x00 16. " IRMQ ,Individual RX masking and queue enable" "Disabled,Enabled" bitfld.long 0x00 15. " DMA ,DMA enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIOEN ,Local priority enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AEN ,Abort enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID acceptance mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the last message buffer" line.long 0x04 "CAN1_CTRL1,CAN1 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler division factor" bitfld.long 0x04 22.--23. " RJW ,Resync jump width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" newline bitfld.long 0x04 16.--18. " PSEG2 ,Phase segment 2" ",2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 15. " BOFFMSK ,Bus off mask" "Masked,Not masked" bitfld.long 0x04 14. " ERRMSK ,Error mask" "Masked,Not masked" newline bitfld.long 0x04 13. " CLKSRC ,CAN engine clock source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop back" "Disabled,Enabled" bitfld.long 0x04 11. " TWRNMSK ,Tx warning interrupt mask" "Not masked,Masked" newline bitfld.long 0x04 10. " RWRNMSK ,RX warning interrupt mask" "Not masked,Masked" bitfld.long 0x04 7. " SMP ,Sampling mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFFREC ,Bus off recovery mode disable" "No,Yes" newline bitfld.long 0x04 5. " TSYN ,Timer sync mode" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest buffer transmitted first" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-only mode" "Deactivated,Activated" newline bitfld.long 0x04 0.--2. " PROPSEG ,Propagation segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" endif group.long 0x08++0x03 line.long 0x00 "CAN1_TIMER,CAN1 Free Running Timer Register" hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40025000)&0x40000000)==0x00) rgroup.long 0x10++0x0F line.long 0x00 "CAN1_RXMGMASK,CAN1 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN1_RX14MASK,CAN1 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN1_RX15MASK,CAN1 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN1_ECR,CAN1 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" else group.long 0x10++0x0F line.long 0x00 "CAN1_RXMGMASK,CAN1 RX Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG[31] ,RX mailboxes global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX mailboxes global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX mailboxes global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX mailboxes global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX mailboxes global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX mailboxes global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX mailboxes global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX mailboxes global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX mailboxes global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX mailboxes global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX mailboxes global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX mailboxes global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX mailboxes global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX mailboxes global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX mailboxes global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX mailboxes global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX mailboxes global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX mailboxes global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX mailboxes global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX mailboxes global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX mailboxes global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX mailboxes global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX mailboxes global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX mailboxes global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX mailboxes global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX mailboxes global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX mailboxes global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX mailboxes global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX mailboxes global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX mailboxes global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX mailboxes global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX mailboxes global mask bit 0" "Don't care,Checked" line.long 0x04 "CAN1_RX14MASK,CAN1 RX 14 Mask Register" bitfld.long 0x04 31. " RX14M[31] ,RX buffer 14 mask bit 31" "Don't care,Checked" bitfld.long 0x04 30. " [30] ,RX buffer 14 mask bit 30" "Don't care,Checked" bitfld.long 0x04 29. " [29] ,RX buffer 14 mask bit 29" "Don't care,Checked" newline bitfld.long 0x04 28. " [28] ,RX buffer 14 mask bit 28" "Don't care,Checked" bitfld.long 0x04 27. " [27] ,RX buffer 14 mask bit 27" "Don't care,Checked" bitfld.long 0x04 26. " [26] ,RX buffer 14 mask bit 26" "Don't care,Checked" newline bitfld.long 0x04 25. " [25] ,RX buffer 14 mask bit 25" "Don't care,Checked" bitfld.long 0x04 24. " [24] ,RX buffer 14 mask bit 24" "Don't care,Checked" bitfld.long 0x04 23. " [23] ,RX buffer 14 mask bit 23" "Don't care,Checked" newline bitfld.long 0x04 22. " [22] ,RX buffer 14 mask bit 22" "Don't care,Checked" bitfld.long 0x04 21. " [21] ,RX buffer 14 mask bit 21" "Don't care,Checked" bitfld.long 0x04 20. " [20] ,RX buffer 14 mask bit 20" "Don't care,Checked" newline bitfld.long 0x04 19. " [19] ,RX buffer 14 mask bit 19" "Don't care,Checked" bitfld.long 0x04 18. " [18] ,RX buffer 14 mask bit 18" "Don't care,Checked" bitfld.long 0x04 17. " [17] ,RX buffer 14 mask bit 17" "Don't care,Checked" newline bitfld.long 0x04 16. " [16] ,RX buffer 14 mask bit 16" "Don't care,Checked" bitfld.long 0x04 15. " [15] ,RX buffer 14 mask bit 15" "Don't care,Checked" bitfld.long 0x04 14. " [14] ,RX buffer 14 mask bit 14" "Don't care,Checked" newline bitfld.long 0x04 13. " [13] ,RX buffer 14 mask bit 13" "Don't care,Checked" bitfld.long 0x04 12. " [12] ,RX buffer 14 mask bit 12" "Don't care,Checked" bitfld.long 0x04 11. " [11] ,RX buffer 14 mask bit 11" "Don't care,Checked" newline bitfld.long 0x04 10. " [10] ,RX buffer 14 mask bit 10" "Don't care,Checked" bitfld.long 0x04 9. " [9] ,RX buffer 14 mask bit 9" "Don't care,Checked" bitfld.long 0x04 8. " [8] ,RX buffer 14 mask bit 8" "Don't care,Checked" newline bitfld.long 0x04 7. " [7] ,RX buffer 14 mask bit 7" "Don't care,Checked" bitfld.long 0x04 6. " [6] ,RX buffer 14 mask bit 6" "Don't care,Checked" bitfld.long 0x04 5. " [5] ,RX buffer 14 mask bit 5" "Don't care,Checked" newline bitfld.long 0x04 4. " [4] ,RX buffer 14 mask bit 4" "Don't care,Checked" bitfld.long 0x04 3. " [3] ,RX buffer 14 mask bit 3" "Don't care,Checked" bitfld.long 0x04 2. " [2] ,RX buffer 14 mask bit 2" "Don't care,Checked" newline bitfld.long 0x04 1. " [1] ,RX buffer 14 mask bit 1" "Don't care,Checked" bitfld.long 0x04 0. " [0] ,RX buffer 14 mask bit 0" "Don't care,Checked" line.long 0x08 "CAN1_RX15MASK,CAN1 RX 15 Mask Register" bitfld.long 0x08 31. " RX15M[31] ,RX buffer 15 mask bit 31" "Don't care,Checked" bitfld.long 0x08 30. " [30] ,RX buffer 15 mask bit 30" "Don't care,Checked" bitfld.long 0x08 29. " [29] ,RX buffer 15 mask bit 29" "Don't care,Checked" newline bitfld.long 0x08 28. " [28] ,RX buffer 15 mask bit 28" "Don't care,Checked" bitfld.long 0x08 27. " [27] ,RX buffer 15 mask bit 27" "Don't care,Checked" bitfld.long 0x08 26. " [26] ,RX buffer 15 mask bit 26" "Don't care,Checked" newline bitfld.long 0x08 25. " [25] ,RX buffer 15 mask bit 25" "Don't care,Checked" bitfld.long 0x08 24. " [24] ,RX buffer 15 mask bit 24" "Don't care,Checked" bitfld.long 0x08 23. " [23] ,RX buffer 15 mask bit 23" "Don't care,Checked" newline bitfld.long 0x08 22. " [22] ,RX buffer 15 mask bit 22" "Don't care,Checked" bitfld.long 0x08 21. " [21] ,RX buffer 15 mask bit 21" "Don't care,Checked" bitfld.long 0x08 20. " [20] ,RX buffer 15 mask bit 20" "Don't care,Checked" newline bitfld.long 0x08 19. " [19] ,RX buffer 15 mask bit 19" "Don't care,Checked" bitfld.long 0x08 18. " [18] ,RX buffer 15 mask bit 18" "Don't care,Checked" bitfld.long 0x08 17. " [17] ,RX buffer 15 mask bit 17" "Don't care,Checked" newline bitfld.long 0x08 16. " [16] ,RX buffer 15 mask bit 16" "Don't care,Checked" bitfld.long 0x08 15. " [15] ,RX buffer 15 mask bit 15" "Don't care,Checked" bitfld.long 0x08 14. " [14] ,RX buffer 15 mask bit 14" "Don't care,Checked" newline bitfld.long 0x08 13. " [13] ,RX buffer 15 mask bit 13" "Don't care,Checked" bitfld.long 0x08 12. " [12] ,RX buffer 15 mask bit 12" "Don't care,Checked" bitfld.long 0x08 11. " [11] ,RX buffer 15 mask bit 11" "Don't care,Checked" newline bitfld.long 0x08 10. " [10] ,RX buffer 15 mask bit 10" "Don't care,Checked" bitfld.long 0x08 9. " [9] ,RX buffer 15 mask bit 9" "Don't care,Checked" bitfld.long 0x08 8. " [8] ,RX buffer 15 mask bit 8" "Don't care,Checked" newline bitfld.long 0x08 7. " [7] ,RX buffer 15 mask bit 7" "Don't care,Checked" bitfld.long 0x08 6. " [6] ,RX buffer 15 mask bit 6" "Don't care,Checked" bitfld.long 0x08 5. " [5] ,RX buffer 15 mask bit 5" "Don't care,Checked" newline bitfld.long 0x08 4. " [4] ,RX buffer 15 mask bit 4" "Don't care,Checked" bitfld.long 0x08 3. " [3] ,RX buffer 15 mask bit 3" "Don't care,Checked" bitfld.long 0x08 2. " [2] ,RX buffer 15 mask bit 2" "Don't care,Checked" newline bitfld.long 0x08 1. " [1] ,RX buffer 15 mask bit 1" "Don't care,Checked" bitfld.long 0x08 0. " [0] ,RX buffer 15 mask bit 0" "Don't care,Checked" line.long 0x0C "CAN1_ECR,CAN1 Error Counter Register" hexmask.long.byte 0x0C 8.--15. 1. " RXERRCNT ,Receive error counter" hexmask.long.byte 0x0C 0.--7. 1. " TXERRCNT ,Transmit error counter" endif newline hgroup.long 0x20++0x03 hide.long 0x00 "CAN1_ESR1,CAN1 Error and Status 1 Register" in newline group.long 0x28++0x03 line.long 0x00 "CAN1_IMASK1,CAN1 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUF31M ,Buffer MB31 interrupt mask" "Masked,Not masked" bitfld.long 0x00 30. " BUF30M ,Buffer MB30 interrupt mask" "Masked,Not masked" bitfld.long 0x00 29. " BUF29M ,Buffer MB29 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 28. " BUF28M ,Buffer MB28 interrupt mask" "Masked,Not masked" bitfld.long 0x00 27. " BUF27M ,Buffer MB27 interrupt mask" "Masked,Not masked" bitfld.long 0x00 26. " BUF26M ,Buffer MB26 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 25. " BUF25M ,Buffer MB25 interrupt mask" "Masked,Not masked" bitfld.long 0x00 24. " BUF24M ,Buffer MB24 interrupt mask" "Masked,Not masked" bitfld.long 0x00 23. " BUF23M ,Buffer MB23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 22. " BUF22M ,Buffer MB22 interrupt mask" "Masked,Not masked" bitfld.long 0x00 21. " BUF21M ,Buffer MB21 interrupt mask" "Masked,Not masked" bitfld.long 0x00 20. " BUF20M ,Buffer MB20 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 19. " BUF19M ,Buffer MB19 interrupt mask" "Masked,Not masked" bitfld.long 0x00 18. " BUF18M ,Buffer MB18 interrupt mask" "Masked,Not masked" bitfld.long 0x00 17. " BUF17M ,Buffer MB17 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 16. " BUF16M ,Buffer MB16 interrupt mask" "Masked,Not masked" bitfld.long 0x00 15. " BUF15M ,Buffer MB15 interrupt mask" "Masked,Not masked" bitfld.long 0x00 14. " BUF14M ,Buffer MB14 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 13. " BUF13M ,Buffer MB13 interrupt mask" "Masked,Not masked" bitfld.long 0x00 12. " BUF12M ,Buffer MB12 interrupt mask" "Masked,Not masked" bitfld.long 0x00 11. " BUF11M ,Buffer MB11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 10. " BUF10M ,Buffer MB10 interrupt mask" "Masked,Not masked" bitfld.long 0x00 9. " BUF9M ,Buffer MB9 interrupt mask" "Masked,Not masked" bitfld.long 0x00 8. " BUF8M ,Buffer MB8 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 7. " BUF7M ,Buffer MB7 interrupt mask" "Masked,Not masked" bitfld.long 0x00 6. " BUF6M ,Buffer MB6 interrupt mask" "Masked,Not masked" bitfld.long 0x00 5. " BUF5M ,Buffer MB5 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 4. " BUF4M ,Buffer MB4 interrupt mask" "Masked,Not masked" bitfld.long 0x00 3. " BUF3M ,Buffer MB3 interrupt mask" "Masked,Not masked" bitfld.long 0x00 2. " BUF2M ,Buffer MB2 interrupt mask" "Masked,Not masked" newline bitfld.long 0x00 1. " BUF1M ,Buffer MB1 interrupt mask" "Masked,Not masked" bitfld.long 0x00 0. " BUF0M ,Buffer MB0 interrupt mask" "Masked,Not masked" if ((per.l(ad:0x40025000)&0x20000000)==0x00) group.long 0x30++0x03 line.long 0x00 "CAN1_IFLAG1,CAN1 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " BUF7I ,Buffer MB7 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " BUF6I ,Buffer MB6 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " BUF5I ,Buffer MB5 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " BUF4I ,Buffer MB4 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " BUF3I ,Buffer MB3 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BUF2I ,Buffer MB2 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " BUF1I ,Buffer MB1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" else group.long 0x30++0x03 line.long 0x00 "CAN1_IFLAG1,CAN1 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " BUF28I ,Buffer MB28 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 27. " BUF27I ,Buffer MB27 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " BUF25I ,Buffer MB25 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " BUF23I ,Buffer MB23 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " BUF22I ,Buffer MB22 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " BUF19I ,Buffer MB19 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " BUF16I ,Buffer MB16 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 15. " BUF15I ,Buffer MB15 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 13. " BUF13I ,Buffer MB13 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " BUF11I ,Buffer MB11 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " BUF10I ,Buffer MB10 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " RFO ,RX FIFO overflow" "No overflow,Overflow" eventfld.long 0x00 6. " RFW ,RX FIFO warning" "Not full,Almost full" eventfld.long 0x00 5. " FARF ,Frames available in RX FIFO" "Not available,Available" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 interrupt" "No interrupt,Interrupt" endif if ((per.l(ad:0x40025000)&0x40000000)==0x00) group.long 0x34++0x03 line.long 0x00 "CAN1_CTRL2,CAN1 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" rbitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline rbitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" rbitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline rbitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "CAN1_CTRL2,CAN1 Control 2 Register" bitfld.long 0x00 30. " BOFFDONEMSK ,Bus off done interrupt mask" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RFFN ,Number of RX FIFO filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" newline bitfld.long 0x00 19.--23. " TASD ,Tx arbitration start delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18. " MRP ,Mailboxes reception priority" "RXFIFO>Mailb,Mailb>RXFIFO" bitfld.long 0x00 17. " RRS ,Remote request storing" "Generated,Stored" newline bitfld.long 0x00 16. " EACEN ,Entire frame arbitration field comparison enable for RX mailboxes" "Disabled,Enabled" endif rgroup.long 0x38++0x03 line.long 0x00 "CAN1_ESR2,CAN1 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest priority Tx mailbox" bitfld.long 0x00 14. " VPS ,Valid priority status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive mailbox" "No,Yes" rgroup.long 0x44++0x03 line.long 0x00 "CAN1_CRCR,CAN1 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC transmitted" if ((per.l(ad:0x40025000)&0x40000000)==0x00) rgroup.long 0x48++0x03 line.long 0x00 "CAN1_RXFGMASK,CAN1 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" else group.long 0x48++0x03 line.long 0x00 "CAN1_RXFGMASK,CAN1 RX FIFO Global Mask Register" bitfld.long 0x00 31. " FGM[31] ,RX FIFO global mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,RX FIFO global mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,RX FIFO global mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,RX FIFO global mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,RX FIFO global mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,RX FIFO global mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,RX FIFO global mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,RX FIFO global mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,RX FIFO global mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,RX FIFO global mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,RX FIFO global mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,RX FIFO global mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,RX FIFO global mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,RX FIFO global mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,RX FIFO global mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,RX FIFO global mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,RX FIFO global mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,RX FIFO global mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,RX FIFO global mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,RX FIFO global mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,RX FIFO global mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,RX FIFO global mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,RX FIFO global mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,RX FIFO global mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,RX FIFO global mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,RX FIFO global mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,RX FIFO global mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,RX FIFO global mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,RX FIFO global mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,RX FIFO global mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,RX FIFO global mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,RX FIFO global mask bit 0" "Don't care,Checked" endif newline hgroup.long 0x4C++0x03 hide.long 0x00 "CAN1_RXFIR,CAN1 RX FIFO Information Register" in newline if ((per.l(ad:0x40025000)&0x40000000)==0x40000000) group.long 0x50++0x03 line.long 0x00 "CAN1_CBT,CAN1 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" else rgroup.long 0x50++0x03 line.long 0x00 "CAN1_CBT,CAN1 Bit Timing Register" bitfld.long 0x00 31. " BTF ,Bit timing format enable" "Disabled,Enabled" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ,Extended prescaler division factor" bitfld.long 0x00 16.--19. " ERJW ,Extended resync jump width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 10.--15. " EPROPSEG ,Extended propagation segment" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta,33xTime-Quanta,34xTime-Quanta,35xTime-Quanta,36xTime-Quanta,37xTime-Quanta,38xTime-Quanta,39xTime-Quanta,40xTime-Quanta,41xTime-Quanta,42xTime-Quanta,43xTime-Quanta,44xTime-Quanta,45xTime-Quanta,46xTime-Quanta,47xTime-Quanta,48xTime-Quanta,49xTime-Quanta,50xTime-Quanta,51xTime-Quanta,52xTime-Quanta,53xTime-Quanta,54xTime-Quanta,55xTime-Quanta,56xTime-Quanta,57xTime-Quanta,58xTime-Quanta,59xTime-Quanta,60xTime-Quanta,61xTime-Quanta,62xTime-Quanta,63xTime-Quanta,64xTime-Quanta" bitfld.long 0x00 5.--9. " EPSEG1 ,Extended phase segment 1" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" bitfld.long 0x00 0.--4. " EPSEG2 ,Extended phase segment 2" "1xTime-Quanta,2xTime-Quanta,3xTime-Quanta,4xTime-Quanta,5xTime-Quanta,6xTime-Quanta,7xTime-Quanta,8xTime-Quanta,9xTime-Quanta,10xTime-Quanta,11xTime-Quanta,12xTime-Quanta,13xTime-Quanta,14xTime-Quanta,15xTime-Quanta,16xTime-Quanta,17xTime-Quanta,18xTime-Quanta,19xTime-Quanta,20xTime-Quanta,21xTime-Quanta,22xTime-Quanta,23xTime-Quanta,24xTime-Quanta,25xTime-Quanta,26xTime-Quanta,27xTime-Quanta,28xTime-Quanta,29xTime-Quanta,30xTime-Quanta,31xTime-Quanta,32xTime-Quanta" endif tree "CAN1 RX Individual Mask Registers $2" width 14. if (((per.l(ad:0x40025000))&0x40000000)==0x40000000) group.long 0x880++0x03 line.long 0x00 "CAN1_RXIMR0,CAN1 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x884++0x03 line.long 0x00 "CAN1_RXIMR1,CAN1 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x888++0x03 line.long 0x00 "CAN1_RXIMR2,CAN1 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x88C++0x03 line.long 0x00 "CAN1_RXIMR3,CAN1 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x890++0x03 line.long 0x00 "CAN1_RXIMR4,CAN1 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x894++0x03 line.long 0x00 "CAN1_RXIMR5,CAN1 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x898++0x03 line.long 0x00 "CAN1_RXIMR6,CAN1 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x89C++0x03 line.long 0x00 "CAN1_RXIMR7,CAN1 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A0++0x03 line.long 0x00 "CAN1_RXIMR8,CAN1 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A4++0x03 line.long 0x00 "CAN1_RXIMR9,CAN1 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8A8++0x03 line.long 0x00 "CAN1_RXIMR10,CAN1 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8AC++0x03 line.long 0x00 "CAN1_RXIMR11,CAN1 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B0++0x03 line.long 0x00 "CAN1_RXIMR12,CAN1 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B4++0x03 line.long 0x00 "CAN1_RXIMR13,CAN1 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8B8++0x03 line.long 0x00 "CAN1_RXIMR14,CAN1 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" group.long 0x8BC++0x03 line.long 0x00 "CAN1_RXIMR15,CAN1 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" else rgroup.long 0x880++0x03 line.long 0x00 "CAN1_RXIMR0,CAN1 RX Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x884++0x03 line.long 0x00 "CAN1_RXIMR1,CAN1 RX Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x888++0x03 line.long 0x00 "CAN1_RXIMR2,CAN1 RX Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x88C++0x03 line.long 0x00 "CAN1_RXIMR3,CAN1 RX Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x890++0x03 line.long 0x00 "CAN1_RXIMR4,CAN1 RX Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x894++0x03 line.long 0x00 "CAN1_RXIMR5,CAN1 RX Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x898++0x03 line.long 0x00 "CAN1_RXIMR6,CAN1 RX Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x89C++0x03 line.long 0x00 "CAN1_RXIMR7,CAN1 RX Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A0++0x03 line.long 0x00 "CAN1_RXIMR8,CAN1 RX Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A4++0x03 line.long 0x00 "CAN1_RXIMR9,CAN1 RX Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8A8++0x03 line.long 0x00 "CAN1_RXIMR10,CAN1 RX Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8AC++0x03 line.long 0x00 "CAN1_RXIMR11,CAN1 RX Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B0++0x03 line.long 0x00 "CAN1_RXIMR12,CAN1 RX Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B4++0x03 line.long 0x00 "CAN1_RXIMR13,CAN1 RX Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8B8++0x03 line.long 0x00 "CAN1_RXIMR14,CAN1 RX Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" rgroup.long 0x8BC++0x03 line.long 0x00 "CAN1_RXIMR15,CAN1 RX Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI[31] ,Individual mask bit 31" "Don't care,Checked" bitfld.long 0x00 30. " [30] ,Individual mask bit 30" "Don't care,Checked" bitfld.long 0x00 29. " [29] ,Individual mask bit 29" "Don't care,Checked" newline bitfld.long 0x00 28. " [28] ,Individual mask bit 28" "Don't care,Checked" bitfld.long 0x00 27. " [27] ,Individual mask bit 27" "Don't care,Checked" bitfld.long 0x00 26. " [26] ,Individual mask bit 26" "Don't care,Checked" newline bitfld.long 0x00 25. " [25] ,Individual mask bit 25" "Don't care,Checked" bitfld.long 0x00 24. " [24] ,Individual mask bit 24" "Don't care,Checked" bitfld.long 0x00 23. " [23] ,Individual mask bit 23" "Don't care,Checked" newline bitfld.long 0x00 22. " [22] ,Individual mask bit 22" "Don't care,Checked" bitfld.long 0x00 21. " [21] ,Individual mask bit 21" "Don't care,Checked" bitfld.long 0x00 20. " [20] ,Individual mask bit 20" "Don't care,Checked" newline bitfld.long 0x00 19. " [19] ,Individual mask bit 19" "Don't care,Checked" bitfld.long 0x00 18. " [18] ,Individual mask bit 18" "Don't care,Checked" bitfld.long 0x00 17. " [17] ,Individual mask bit 17" "Don't care,Checked" newline bitfld.long 0x00 16. " [16] ,Individual mask bit 16" "Don't care,Checked" bitfld.long 0x00 15. " [15] ,Individual mask bit 15" "Don't care,Checked" bitfld.long 0x00 14. " [14] ,Individual mask bit 14" "Don't care,Checked" newline bitfld.long 0x00 13. " [13] ,Individual mask bit 13" "Don't care,Checked" bitfld.long 0x00 12. " [12] ,Individual mask bit 12" "Don't care,Checked" bitfld.long 0x00 11. " [11] ,Individual mask bit 11" "Don't care,Checked" newline bitfld.long 0x00 10. " [10] ,Individual mask bit 10" "Don't care,Checked" bitfld.long 0x00 9. " [9] ,Individual mask bit 9" "Don't care,Checked" bitfld.long 0x00 8. " [8] ,Individual mask bit 8" "Don't care,Checked" newline bitfld.long 0x00 7. " [7] ,Individual mask bit 7" "Don't care,Checked" bitfld.long 0x00 6. " [6] ,Individual mask bit 6" "Don't care,Checked" bitfld.long 0x00 5. " [5] ,Individual mask bit 5" "Don't care,Checked" newline bitfld.long 0x00 4. " [4] ,Individual mask bit 4" "Don't care,Checked" bitfld.long 0x00 3. " [3] ,Individual mask bit 3" "Don't care,Checked" bitfld.long 0x00 2. " [2] ,Individual mask bit 2" "Don't care,Checked" newline bitfld.long 0x00 1. " [1] ,Individual mask bit 1" "Don't care,Checked" bitfld.long 0x00 0. " [0] ,Individual mask bit 0" "Don't care,Checked" endif tree.end tree "CAN1 Message Buffer Structure" group.long 0x80++0x0F line.long 0x00 "MB0_0,Message Buffer 0 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB0_1,Message Buffer 0 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB0_2,Message Buffer 0 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB0_3,Message Buffer 0 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x90++0x0F line.long 0x00 "MB1_0,Message Buffer 1 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB1_1,Message Buffer 1 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB1_2,Message Buffer 1 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB1_3,Message Buffer 1 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xA0++0x0F line.long 0x00 "MB2_0,Message Buffer 2 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB2_1,Message Buffer 2 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB2_2,Message Buffer 2 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB2_3,Message Buffer 2 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xB0++0x0F line.long 0x00 "MB3_0,Message Buffer 3 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB3_1,Message Buffer 3 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB3_2,Message Buffer 3 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB3_3,Message Buffer 3 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xC0++0x0F line.long 0x00 "MB4_0,Message Buffer 4 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB4_1,Message Buffer 4 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB4_2,Message Buffer 4 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB4_3,Message Buffer 4 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xD0++0x0F line.long 0x00 "MB5_0,Message Buffer 5 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB5_1,Message Buffer 5 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB5_2,Message Buffer 5 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB5_3,Message Buffer 5 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xE0++0x0F line.long 0x00 "MB6_0,Message Buffer 6 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB6_1,Message Buffer 6 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB6_2,Message Buffer 6 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB6_3,Message Buffer 6 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0xF0++0x0F line.long 0x00 "MB7_0,Message Buffer 7 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB7_1,Message Buffer 7 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB7_2,Message Buffer 7 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB7_3,Message Buffer 7 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x100++0x0F line.long 0x00 "MB8_0,Message Buffer 8 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB8_1,Message Buffer 8 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB8_2,Message Buffer 8 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB8_3,Message Buffer 8 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x110++0x0F line.long 0x00 "MB9_0,Message Buffer 9 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB9_1,Message Buffer 9 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB9_2,Message Buffer 9 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB9_3,Message Buffer 9 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x120++0x0F line.long 0x00 "MB10_0,Message Buffer 10 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB10_1,Message Buffer 10 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB10_2,Message Buffer 10 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB10_3,Message Buffer 10 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x130++0x0F line.long 0x00 "MB11_0,Message Buffer 11 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB11_1,Message Buffer 11 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB11_2,Message Buffer 11 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB11_3,Message Buffer 11 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x140++0x0F line.long 0x00 "MB12_0,Message Buffer 12 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB12_1,Message Buffer 12 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB12_2,Message Buffer 12 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB12_3,Message Buffer 12 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x150++0x0F line.long 0x00 "MB13_0,Message Buffer 13 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB13_1,Message Buffer 13 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB13_2,Message Buffer 13 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB13_3,Message Buffer 13 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x160++0x0F line.long 0x00 "MB14_0,Message Buffer 14 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB14_1,Message Buffer 14 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB14_2,Message Buffer 14 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB14_3,Message Buffer 14 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline group.long 0x170++0x0F line.long 0x00 "MB15_0,Message Buffer 15 Register" bitfld.long 0x00 31. " EDL ,Extended data length" "0,1" bitfld.long 0x00 30. " BRS ,Bit rate switch" "0,1" bitfld.long 0x00 29. " ESI ,Error state indicator" "0,1" newline bitfld.long 0x00 24.--27. " CODE ,Message buffer code" "Inactive,Busy,Full,,Inactive,,Overrun,,,Abort,Ranswer,,Data/Remote,,Tanswer,?..." bitfld.long 0x00 22. " SRR ,Substitute remote request" "Not requested,Requested" bitfld.long 0x00 21. " IDE ,ID extended" "Standard,Extended" newline bitfld.long 0x00 20. " RTR ,Remote transmission request" "Not requested,Requested" bitfld.long 0x00 16.--19. " DLC ,Length of the data to be stored/transmitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TIME_STAMP ,Counter time stamp" line.long 0x04 "MB15_1,Message Buffer 15 Register" bitfld.long 0x04 29.--31. " PRIO ,Local priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 18.--28. 1. " STD ,Contains standard/extended (HIGH word) identifier of message buffer" hexmask.long.tbyte 0x04 0.--17. 1. " EXT ,Contains extended (LOW word) identifier of message buffer" line.long 0x08 "MB15_2,Message Buffer 15 Register" hexmask.long.byte 0x08 24.--31. 1. " DATA_BYTE_0 ,Data byte 3 of Rx/Tx frame" hexmask.long.byte 0x08 16.--23. 1. " DATA_BYTE_1 ,Data byte 2 of Rx/Tx frame" hexmask.long.byte 0x08 8.--15. 1. " DATA_BYTE_2 ,Data byte 1 of Rx/Tx frame" newline hexmask.long.byte 0x08 0.--7. 1. " DATA_BYTE_3 ,Data byte 0 of Rx/Tx frame" line.long 0x0C "MB15_3,Message Buffer 15 Register" hexmask.long.byte 0x0C 24.--31. 1. " DATA_BYTE_4 ,Data byte 4 of Rx/Tx frame" hexmask.long.byte 0x0C 16.--23. 1. " DATA_BYTE_5 ,Data byte 5 of Rx/Tx frame" hexmask.long.byte 0x0C 8.--15. 1. " DATA_BYTE_6 ,Data byte 6 of Rx/Tx frame" newline hexmask.long.byte 0x0C 0.--7. 1. " DATA_BYTE_7 ,Data byte 7 of Rx/Tx frame" newline tree.end width 0x0B tree.end tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x4002C000 width 13. if ((per.l(ad:0x4002C000+0x2C)&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline rbitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline rbitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline rbitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "No,Yes" newline bitfld.long 0x00 26. " MTFE ,Modified transfer format enable" "Disabled,Enabled" newline sif !cpuis("MKV10Z32VLC7R")&&!cpuis("MKV10Z32VFM7R")&&!cpuis("MKV10Z64VFM7P")&&!cpuis("MKV10Z128VFM7")&&!cpuis("MKV11Z128VFM7")&&!cpuis("MKV11Z128VFM7P")&&!cpuis("MKV10Z64VFM7")&&!cpuis("MKV11Z64VFM7")&&!cpuis("MKV10Z128VLF7")&&!cpuis("MKV11Z128VLF7")&&!cpuis("MKV11Z128VLF7P")&&!cpuis("MKV10Z64VLF7")&&!cpuis("MKV11Z64VLF7")&&!cpuis("MKV11Z128VLH7")&&!cpuis("MKV10Z128VLH7")&&!cpuis("MKV11Z64VLH7")&&!cpuis("MKV11Z128VLH7P")&&!cpuis("MKV10Z64VLH7")&&!cpuis("MKV10Z64VLH7P") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCSIS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCSIS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "Not cleared,Cleared" bitfld.long 0x00 10. " CLR_RXF ,Clear RX counter" "Not cleared,Cleared" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 cycles,1 cycle,2 cycles,?..." bitfld.long 0x00 0. " HALT ,Halt" "Start,Stop" endif group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" if ((per.l(ad:0x4002C000)&0x80000000)==0x80000000) if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0xC++0x03 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif if (((per.l(ad:0x4002C000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x10++0x03 line.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" newline bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase [captured/changed]" "Leading/following,Following/leading" hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1,Clock And Transfer Attributes Register 1" endif group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x4002C000)+0x2C)&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Register Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EQQ ,End of queue" "Not last,Last" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not cleared,Cleared" newline sif cpuis("MKV31F128VLH10P")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12*")||cpuis("MKV31F512VLH12*")||cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z128VFM7")||cpuis("MKV11Z128VFM7")||cpuis("MKV11Z128VFM7P")||cpuis("MKV10Z64VFM7")||cpuis("MKV11Z64VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV11Z128VLF7")||cpuis("MKV11Z128VLF7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV11Z64VLF7")||cpuis("MKV11Z128VLH7")||cpuis("MKV10Z128VLH7")||cpuis("MKV11Z64VLH7")||cpuis("MKV11Z128VLH7P")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10*") newline bitfld.long 0x00 20. " PCS[4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" elif cpuis("MKV31F512VLL12P")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV42F128VLF16")||cpuis("MKV46F256VLH16*") newline bitfld.long 0x00 21. " PCS[5] ,PCS5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,PCS4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,PCS3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,PCS2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,PCS1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,PCS0 inactive state" "Low,High" endif newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x38++0x03 line.long 0x00 "POPR,POP RX FIFO Register" if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif if (((per.l(ad:0x4002C000))&0x80000000)==0x80000000) rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" sif cpuis("MKV10Z32VLC7R")||cpuis("MKV10Z32VFM7R") group.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" rbitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" newline bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" newline bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" newline eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" newline eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" newline in newline if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" newline bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif cpuis("MKV10Z128VFM7")||cpuis("MKV10Z128VLF7")||cpuis("MKV10Z128VLH7")||cpuis("MKV10Z64VFM7")||cpuis("MKV10Z64VFM7P")||cpuis("MKV10Z64VLF7")||cpuis("MKV10Z64VLH7")||cpuis("MKV10Z64VLH7P")||cpuis("MKV10Z32VFM7R")||cpuis("MKV10Z32VLC7R")||cpuis("MKV42F128VLF16")||cpuis("MKV42F64VLF16")||cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R")||cpuis("MKV31F256VLH12P")||cpuis("MKV31F256VLH12R")||cpuis("MKV30F128VLF10P")||cpuis("MKV30F64VLF10R")||cpuis("MKV31F512VLH12R")||cpuis("MKV31F512VLL12P")||cpuis("MKV31F128VLH10P") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("MKV10Z*") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" newline eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "Not started,Started" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control And Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" newline bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" newline eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" width 0x0B tree.end tree.open "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART_0" base ad:0x4006A000 width 8. group.byte 0x00++0x03 line.byte 0x00 "BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "BDL,UART Baud Rate Register Low" line.byte 0x02 "C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Disabled,Enabled" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not empty,Empty" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not completed,Completed" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not full,Full" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not idle,Idle" newline bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "No overrun,Overrun" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "No error,Error" bitfld.byte 0x00 0. " PF ,Parity error flag" "No error,Error" group.byte 0x05++0x01 line.byte 0x00 "S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "No interrupt,Interrupt" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bits,13/14 bits" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at length of)" "Disabled,11 bits time" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "MA1,UART Match Address Registers 1" line.byte 0x01 "MA2,UART Match Address Registers 2" line.byte 0x02 "C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt,DMA" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt,DMA" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "No noise,Noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "No error,Error" group.byte 0x0D++0x00 line.byte 0x00 "MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((per.b(ad:0x4006A000+0x03)&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "No effect,Flush" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "No effect,Flush" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" line.byte 0x01 "SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" if ((per.b(ad:0x4006A000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006A000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "RCFIFO,UART FIFO Receive Count" width 0x0B tree.end tree "UART_1" base ad:0x4006B000 width 8. group.byte 0x00++0x03 line.byte 0x00 "BDH,UART Baud Rate Register High" bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SBNS ,Stop bit number select" "1 bit,2 bits" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "BDL,UART Baud Rate Register Low" line.byte 0x02 "C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Disabled,Enabled" bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Int. loop-back,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" newline bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" newline bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not empty,Empty" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not completed,Completed" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not full,Full" bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not idle,Idle" newline bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "No overrun,Overrun" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" bitfld.byte 0x00 1. " FE ,Framing error flag" "No error,Error" bitfld.byte 0x00 0. " PF ,Parity error flag" "No error,Error" group.byte 0x05++0x01 line.byte 0x00 "S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "No interrupt,Interrupt" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "No interrupt,Interrupt" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bits,13/14 bits" bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable (detected at length of)" "Disabled,11 bits time" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "D,UART Data Register" newline in newline group.byte 0x08++0x03 line.byte 0x00 "MA1,UART Match Address Registers 1" line.byte 0x01 "MA2,UART Match Address Registers 2" line.byte 0x02 "C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt,DMA" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt,DMA" bitfld.byte 0x03 3. " LBKDDMAS , LIN break detect DMA select bit" "Interrupt,DMA" rgroup.byte 0x0C++0x00 line.byte 0x00 "ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "No noise,Noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "No error,Error" group.byte 0x0D++0x00 line.byte 0x00 "MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((per.b(ad:0x4006B000+0x03)&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/buffer flush" "No effect,Flush" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/buffer flush" "No effect,Flush" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" line.byte 0x01 "SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" newline eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflow,Overflow" if ((per.b(ad:0x4006B000+0x03)&0x8)==0x8) rgroup.byte 0x13++0x00 line.byte 0x00 "TWFIFO,UART FIFO Transmit Watermark" else group.byte 0x13++0x00 line.byte 0x00 "TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "TCFIFO,UART FIFO Transmit Count" if ((per.b(ad:0x4006B000+0x03)&0x4)==0x4) rgroup.byte 0x15++0x00 line.byte 0x00 "RWFIFO,UART FIFO Receive Watermark" else group.byte 0x15++0x00 line.byte 0x00 "RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "RCFIFO,UART FIFO Receive Count" width 0x0B tree.end tree.end tree.open "GPIO (General Purpose Input/Output)" tree "GPIOA" base ad:0x400FF000 width 14. group.long 0x00++0x03 line.long 0x00 "PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port data output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output" "Low level,High level" newline sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Port data output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Port data output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output" "Low level,High level" newline endif setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 18. " [18] ,Port toggle output" "Not toggled,Toggled" newline sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 13. " [13] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 12. " [12] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 5. " [5] ,Port toggle output" "Not toggled,Toggled" newline endif bitfld.long 0x00 4. " [4] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 3. " [3] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 2. " [2] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 1. " [1] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 0. " [0] ,Port toggle output" "Not toggled,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low level,High level" bitfld.long 0x00 18. " [18] ,Port data input" "Low level,High level" newline sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 13. " [13] ,Port data input" "Low level,High level" bitfld.long 0x00 12. " [12] ,Port data input" "Low level,High level" bitfld.long 0x00 5. " [5] ,Port data input" "Low level,High level" newline endif bitfld.long 0x00 4. " [4] ,Port data input" "Low level,High level" bitfld.long 0x00 3. " [3] ,Port data input" "Low level,High level" bitfld.long 0x00 2. " [2] ,Port data input" "Low level,High level" newline bitfld.long 0x00 1. " [1] ,Port data input" "Low level,High level" bitfld.long 0x00 0. " [0] ,Port data input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Toggle Output Register" bitfld.long 0x00 19. " PDD[19] ,Port toggle output" "Input,Output" bitfld.long 0x00 18. " [18] ,Port toggle output" "Input,Output" newline sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 13. " [13] ,Port toggle output" "Input,Output" bitfld.long 0x00 12. " [12] ,Port toggle output" "Input,Output" bitfld.long 0x00 5. " [5] ,Port toggle output" "Input,Output" newline endif bitfld.long 0x00 4. " [4] ,Port toggle output" "Input,Output" bitfld.long 0x00 3. " [3] ,Port toggle output" "Input,Output" bitfld.long 0x00 2. " [2] ,Port toggle output" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Port toggle output" "Input,Output" bitfld.long 0x00 0. " [0] ,Port toggle output" "Input,Output" width 0xb tree.end tree "GPIOB" base ad:0x400FF040 width 14. group.long 0x00++0x03 line.long 0x00 "PDOR_SET/CLR,Port Data Output Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port data output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output" "Low level,High level" newline endif setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 19. " PTTO[19] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 18. " [18] ,Port toggle output" "Not toggled,Toggled" newline endif bitfld.long 0x00 17. " [17] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 16. " [16] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 3. " [3] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 2. " [2] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 1. " [1] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 0. " [0] ,Port toggle output" "Not toggled,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 19. " PDI[19] ,Port data input" "Low level,High level" bitfld.long 0x00 18. " [18] ,Port data input" "Low level,High level" newline endif bitfld.long 0x00 17. " [17] ,Port data input" "Low level,High level" bitfld.long 0x00 16. " [16] ,Port data input" "Low level,High level" newline bitfld.long 0x00 3. " [3] ,Port data input" "Low level,High level" bitfld.long 0x00 2. " [2] ,Port data input" "Low level,High level" bitfld.long 0x00 1. " [1] ,Port data input" "Low level,High level" bitfld.long 0x00 0. " [0] ,Port data input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 19. " PDD[19] ,Port data direction" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction" "Input,Output" newline endif bitfld.long 0x00 17. " [17] ,Port data direction" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction" "Input,Output" width 0x0B tree.end tree "GPIOC" base ad:0x400FF080 width 14. group.long 0x00++0x03 line.long 0x00 "PDOR_SET/CLR,Port Data Output Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port data output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Port data output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Port data output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Port data output" "Low level,High level" endif newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Port data output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 11. " PTTO[11] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 10. " [10] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 9. " [9] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 8. " [8] ,Port toggle output" "Not toggled,Toggled" endif newline bitfld.long 0x00 7. " [7] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 6. " [6] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 5. " [5] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 4. " [4] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 3. " [3] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 2. " [2] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 1. " [1] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 0. " [0] ,Port toggle output" "Not toggled,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 11. " PDI[11] ,Port data input" "Low level,High level" bitfld.long 0x00 10. " [10] ,Port data input" "Low level,High level" bitfld.long 0x00 9. " [9] ,Port data input" "Low level,High level" bitfld.long 0x00 8. " [8] ,Port data input" "Low level,High level" endif newline bitfld.long 0x00 7. " [7] ,Port data input" "Low level,High level" bitfld.long 0x00 6. " [6] ,Port data input" "Low level,High level" bitfld.long 0x00 5. " [5] ,Port data input" "Low level,High level" bitfld.long 0x00 4. " [4] ,Port data input" "Low level,High level" newline bitfld.long 0x00 3. " [3] ,Port data input" "Low level,High level" bitfld.long 0x00 2. " [2] ,Port data input" "Low level,High level" bitfld.long 0x00 1. " [1] ,Port data input" "Low level,High level" bitfld.long 0x00 0. " [0] ,Port data input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") bitfld.long 0x00 11. " PDD[11] ,Port data direction" "Input,Output" bitfld.long 0x00 10. " [10] ,Port data direction" "Input,Output" bitfld.long 0x00 9. " [9] ,Port data direction" "Input,Output" bitfld.long 0x00 8. " [8] ,Port data direction" "Input,Output" endif newline bitfld.long 0x00 7. " [7] ,Port data direction" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction" "Input,Output" width 0xb tree.end tree "GPIOD" base ad:0x400FF0C0 width 14. group.long 0x00++0x03 line.long 0x00 "PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port data output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Port data output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Port data output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Port data output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Port data output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" bitfld.long 0x00 7. " PTTO[7] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 6. " [6] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 5. " [5] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 4. " [4] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 3. " [3] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 2. " [2] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 1. " [1] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 0. " [0] ,Port toggle output" "Not toggled,Toggled" rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 7. " PDI[7] ,Port data input" "Low level,High level" bitfld.long 0x00 6. " [6] ,Port data input" "Low level,High level" bitfld.long 0x00 5. " [5] ,Port data input" "Low level,High level" bitfld.long 0x00 4. " [4] ,Port data input" "Low level,High level" newline bitfld.long 0x00 3. " [3] ,Port data input" "Low level,High level" bitfld.long 0x00 2. " [2] ,Port data input" "Low level,High level" bitfld.long 0x00 1. " [1] ,Port data input" "Low level,High level" bitfld.long 0x00 0. " [0] ,Port data input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 7. " PDD[7] ,Port data direction" "Input,Output" bitfld.long 0x00 6. " [6] ,Port data direction" "Input,Output" bitfld.long 0x00 5. " [5] ,Port data direction" "Input,Output" bitfld.long 0x00 4. " [4] ,Port data direction" "Input,Output" newline bitfld.long 0x00 3. " [3] ,Port data direction" "Input,Output" bitfld.long 0x00 2. " [2] ,Port data direction" "Input,Output" bitfld.long 0x00 1. " [1] ,Port data direction" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction" "Input,Output" width 0xb tree.end tree "GPIOE" base ad:0x400FF100 width 14. group.long 0x00++0x03 line.long 0x00 "PDOR_SET/CLR,Port Data Output Register" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " PDO[30] ,Port data output" "Low level,High level" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Port data output" "Low level,High level" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Port data output" "Low level,High level" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Port data output" "Low level,High level" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Port data output" "Low level,High level" newline endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Port data output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Port data output" "Low level,High level" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Port data output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Port data output" "Low level,High level" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Port data output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Port data output" "Low level,High level" endif wgroup.long 0x0C++0x03 line.long 0x00 "PTOR,Port Toggle Output Register" bitfld.long 0x00 30. " PTTO[30] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 29. " [29] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 25. " [25] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 24. " [24] ,Port toggle output" "Not toggled,Toggled" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 21. " [21] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 20. " [20] ,Port toggle output" "Not toggled,Toggled" newline endif bitfld.long 0x00 19. " [19] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 18. " [18] ,Port toggle output" "Not toggled,Toggled" newline bitfld.long 0x00 17. " [17] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 16. " [16] ,Port toggle output" "Not toggled,Toggled" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline bitfld.long 0x00 1. " [1] ,Port toggle output" "Not toggled,Toggled" bitfld.long 0x00 0. " [0] ,Port toggle output" "Not toggled,Toggled" endif rgroup.long 0x10++0x03 line.long 0x00 "PDIR,Port Data Input Register" bitfld.long 0x00 30. " PDI[30] ,Port data input" "Low level,High level" bitfld.long 0x00 29. " [29] ,Port data input" "Low level,High level" newline bitfld.long 0x00 25. " [25] ,Port data input" "Low level,High level" bitfld.long 0x00 24. " [24] ,Port data input" "Low level,High level" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 21. " [21] ,Port data input" "Low level,High level" bitfld.long 0x00 20. " [20] ,Port data input" "Low level,High level" newline endif bitfld.long 0x00 19. " [19] ,Port data input" "Low level,High level" bitfld.long 0x00 18. " [18] ,Port data input" "Low level,High level" newline bitfld.long 0x00 17. " [17] ,Port data input" "Low level,High level" bitfld.long 0x00 16. " [16] ,Port data input" "Low level,High level" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline bitfld.long 0x00 1. " [1] ,Port data input" "Low level,High level" bitfld.long 0x00 0. " [0] ,Port data input" "Low level,High level" endif group.long 0x14++0x03 line.long 0x00 "PDDR,Port Data Direction Register" bitfld.long 0x00 30. " PDD[30] ,Port data direction" "Input,Output" bitfld.long 0x00 29. " [29] ,Port data direction" "Input,Output" newline bitfld.long 0x00 25. " [25] ,Port data direction" "Input,Output" bitfld.long 0x00 24. " [24] ,Port data direction" "Input,Output" newline sif cpuis("MKV42F64VLF16")||cpuis("MKV42F128VLF16") bitfld.long 0x00 21. " [21] ,Port data direction" "Input,Output" bitfld.long 0x00 20. " [20] ,Port data direction" "Input,Output" newline endif bitfld.long 0x00 19. " [19] ,Port data direction" "Input,Output" bitfld.long 0x00 18. " [18] ,Port data direction" "Input,Output" newline bitfld.long 0x00 17. " [17] ,Port data direction" "Input,Output" bitfld.long 0x00 16. " [16] ,Port data direction" "Input,Output" sif cpuis("MKV42F64VLH16")||cpuis("MKV46F256VLH16R") newline bitfld.long 0x00 1. " [1] ,Port data direction" "Input,Output" bitfld.long 0x00 0. " [0] ,Port data direction" "Input,Output" endif width 0xb tree.end tree.end endif newline