; -------------------------------------------------------------------------------- ; @Title: KMx On-Chip Peripherals ; @Props: Released ; @Author: SZM, BCA, BBP ; @Changelog: 2014-05-08 SZM ; 2018-04-03 BCA ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: Kinetis M Family Reference Manual Rev4.pdf (Rev.4, 2013-06) ; KM Family Datasheet Rev.4.pdf (Rev.4, 2013-07) ; MKMxxZxxACxx5RM.pdf (Rev.1, 2014-09) ; MKMxxZxxCxx5RM.pdf (Rev.5, 2013-10) ; KM34P144M75SF0RM.pdf (Rev.3, 2017-09) ; MKMxxZxxACxx5.pdf (Rev.1, 2014-09) ; MKMxxZxxCxx5.pdf (Rev.7, 2014-01) ; KM34P144M75SF0.pdf (Rev.2, 2015-05) ; @Chip: MKM14Z128CHH5,MKM14Z64CHH5,MKM33Z128CLH5,MKM33Z128CLL5 ; MKM33Z64CLH5,MKM33Z64CLL5,MKM34Z128CLL5,MKM14Z128ACHH5 ; MKM14Z128ACHH5R,MKM14Z64ACHH5,MKM33Z128ACLH5,MKM33Z128ACLH5R ; MKM33Z64ACLH5,MKM33Z128CLH5R,MKM33Z64ACLL5,MKM33Z64ACLL5R ; MKM33Z128ACLL5,MKM34Z128ACLL5,MKM34Z128ACLL5R,MKM33Z64CLL5R ; MKM14Z128CHH5R,MKM34Z256VLL7,MKM34Z256VLL7R,MKM34Z256VLQ7 ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perkinetism.per 13155 2021-04-08 14:50:24Z kwitkowski $ config 16. 8. width 0x0B ;Known Problems: ; ;XBAR (Inter-Peripheral Crossbar Switch) XBAR_SEL10, XBAR_SEL12, XBAR_SEL15 Not enough bits (only 5 bits, when 6 are needed) for all possible XBAR Inputs(33 values), while other registers in XBAR Module have. tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "PORT (Port control and interrupts)" tree "PORTA" base ad:0x40046000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x00++0x0B line.long 0x00 "PORTA_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P23,PTA0/LLWU_P16,,,,,,LCD_P23" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD23,PTA0,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P24,PTA1,,,,,,LCD_P24" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD24,PTA1,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P25,PTA2,,,,,,LCD_P25" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD25,PTA2,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x0C++0x03 line.long 0x00 "PORTA_PCR3,Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P26,PTA3,,,,,,LCD_P26" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD26,PTA3,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x10++0x0F line.long 0x00 "PORTA_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD27,PTA4,LLWU_P15,,,,,NMI_B" textline " " elif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P27,PTA4/LLWU_P15,,,,,LCD_P27,NMI_B" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTA4,LLWU_P15,,,,,NMI_B" textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTA_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD28,PTA5,CMP0OUT,?..." textline " " elif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P28,PTA5,CMP0OUT,,,,,LCD_P28" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTA5,CMP0OUT,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTA_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P29,PTA6,XBAR_IN0,LLWU_P14,?..." textline " " elif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P29,PTA6/LLWU_P14,XBAR_IN0,,,,,LCD_P29" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTA6,XBAR_IN0,LLWU_P14,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTA_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD30,PTA7,XBAR_OUT0,?..." textline " " elif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P30,PTA7,XBAR_OUT0,,,,,LCD_P30" textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTA7,XBAR_OUT0,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTA_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTA_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end sif (!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")) tree "PORTB" base ad:0x40047000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x00++0x1B line.long 0x00 "PORTB_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P31,PTB0,,,,,,LCD_P31" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD31,PTB0,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTB_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P32,PTB1/LLWU_P17,,,,,,LCD_P32" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD32,PTB1,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTB_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P33,PTB2,,,,,,LCD_P33" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD33,PTB2,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTB_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P34,PTB3,,,,,,LCD_P34" textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD34,PTB3,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTB_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P35,PTB4,,,,,,LCD_P35" textline " " else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD35,PTB4,?..." textline " " endif bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTB_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P36,PTB5,,,,,,LCD_P36" textline " " else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD36,PTB5,?..." textline " " endif bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTB_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P37/CMP1P0,PTB6,,,,,,LCD_P37" textline " " else bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD37/CMP1P0,PTB6,?..." textline " " endif bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR7,Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P38,PTB7,AFE_CLK,,,,,LCD_P38" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD38,PTB7,AFE_CLK,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTB_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTB_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTB_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTC" base ad:0x40048000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) group.long 0x00++0x0F line.long 0x00 "PORTC_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD39,PTC0,SCI3_RTS,XBAR_IN1,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P39,PTC0,UART3_RTS_b,XBAR_IN1,PDB0_EXTRG,,,LCD_P39" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD39,PTC0,UART3_RTS,XBAR_IN1,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD40/CMP1P1,PTC1,SCI3_CTS,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P40/CMP1_IN1,PTC1,UART3_CTS_b,,,,,LCD_P40" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD40/CMP1P1,PTC1,UART3_CTS,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD41,PTC2,SCI3_TxD,XBAR_OUT1,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P41,PTC2,UART3_TX,XBAR_OUT1,,,,LCD_P41" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD41,PTC2,UART3_TxD,XBAR_OUT1,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD42/CMP0P3,PTC3,SCI3_RxD,LLWU_P13,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P42/CMP0_IN3,PTC3/LLWU_P13,UART3_RX,,,,,LCD_P42" textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD42/CMP0P3,PTC3,UART3_RxD,LLWU_P13,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x10++0x0F line.long 0x00 "PORTC_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P43,PTC4,,,,,,LCD_P43" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD43,PTC4,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTC_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD0,PTC5,SCI0_RTS,LLWU_P12,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE0/CMP2_IN0,PTC5/LLWU_P12,UART0_RTS_b,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD0,PTC5,UART0_RTS,LLWU_P12,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTC_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64CLL5*")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "AD1,PTC6,SCI0_CTS,TMR_1,?..." textline " " elif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "AD1,PTC6,SCI0_CTS,QT1,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE1/CMP2_IN1,PTC6,UART0_CTS_b,QTMR0_TMR_1,PDB0_EXTRG,?..." textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "AD1,PTC6,UART0_CTS,TMR_1,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTC_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "AD2,PTC7,SCI0_TxD,XBAR_OUT2,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE2/CMP2_IN2,PTC7,UART0_TX,XBAR_OUT2,?..." textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "AD2,PTC7,UART0_TxD,XBAR_OUT2,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTC_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTC_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTD" base ad:0x40049000 width 13. sif !cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*") group.long 0x00++0x03 line.long 0x00 "PORTD_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P0,PTD0,SCI0_RxD,XBAR_IN2,LLWU_P11,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0_IN0,PTD0/LLWU_P11,UART0_RX,XBAR_IN2,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P0,PTD0,UART0_RxD,XBAR_IN2,LLWU_P11,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x0F line.long 0x00 "PORTD_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD1,SCI1_TxD,SPI0_SS_B,XBAR_OUT3,QT3,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD1,UART1_TX,SPI0_PCS0,XBAR_OUT3,QTMR0_TMR3,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTD1,UART1_TxD,SPI0_SS_B,XBAR_OUT3,TMR_3,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR2,Pin Control Register 2" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "CMP0P1,PTD2,SCI1_RxD,SPI0_SCK,XBAR_IN3,LLWU_P10,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "CMP0_IN1,PTD2/LLWU_P10,UART1_RX,SPI0_SCK,XBAR_IN3,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "CMP0P1,PTD2,UART1_RxD,SPI0_SCK,XBAR_IN3,LLWU_P10,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR3,Pin Control Register 3" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD3,SCI1_CTS,SPI0_MOSI,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD3,UART1_CTS_b,SPI0_MOSI,?..." textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTD3,UART1_CTS,SPI0_MOSI,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTD_PCR4,Pin Control Register 4" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "AD3,PTD4,SCI1_RTS,SPI0_MISO,LLWU_P9,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE3,PTD4/LLWU_P9,UART1_RTS_b,SPI0_MISO,?..." textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "AD3,PTD4,UART1_RTS,SPI0_MISO,LLWU_P9,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" sif !cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*") group.long 0x14++0x0B line.long 0x00 "PORTD_PCR5,Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD4,PTD5,LPTIM2,QT0,SCI3_CTS,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE4a,PTD5,LPTMR0_ALT3,QTMR0_TMR0,UART3_CTS_b,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD4,PTD5,LPTMR2,TMR_0,UART3_CTS,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTD_PCR6,Pin Control Register 6" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD5,PTD6,LPTIM1,CMP1OUT,SCI3_RTS,LLWU_P8,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE5a,PTD6/LLWU_P8,LPTMR0_ALT2,CMP1_OUT,UART3_RTS_b,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD5,PTD6,LPTMR1,CMP1OUT,UART3_RTS,LLWU_P8,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTD_PCR7,Pin Control Register 7" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP0P4,PTD7,I2C0_SCL,XBAR_IN4,SCI3_RxD,LLWU_P7,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP0_IN4,PTD7/LLWU_P7,I2C0_SCL,XBAR_IN4,UART3_RX,?..." textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "CMP0P4,PTD7,I2C0_SCL,XBAR_IN4,UART3_RxD,LLWU_P7,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTD_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTD_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTD_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable " "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable " "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable " "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 4. " DFE4 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable " "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable " "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable " "Disabled,Enabled" endif line.long 0x04 "PORTD_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTD_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end endif tree "PORTE" base ad:0x4004A000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x00++0x03 line.long 0x00 "PORTE_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE0,I2C0_SDA,XBAR_OUT4,SCI3_TxD,CLKOUT,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE0,I2C0_SDA,XBAR_OUT4,UART3_TxD,CLKOUT,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x03 line.long 0x00 "PORTE_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE1,,,,,,RESET_B" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x08++0x07 line.long 0x00 "PORTE_PCR2,Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL0,PTE2,EWM_IN,XBAR_IN6,I2C1_SDA,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "EXTAL1,PTE2,EWM_IN,XBAR_IN6,I2C1_SDA,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR3,Pin Control Register 3" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL0,PTE3,EWM_OUT_b,AFE_CLK,I2C1_SCL,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "XTAL1,PTE3,EWM_OUT,AFE_CLK,I2C1_SCL,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x10++0x07 line.long 0x00 "PORTE_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE4,LPTIM0,SCI2_CTS,EWM_IN,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE4,LPTMR0_ALT1,UART2_CTS_b,EWM_IN,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTE4,LPTMR0,UART2_CTS,EWM_IN,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE5,QT3,SCI2_RTS,EWM_OUT,LLWU_P6,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE5/LLWU_P6,QTMR0_TMR3,UART2_RTS_b,EWM_OUT_b,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTE5,TMR_3,UART2_RTS,EWM_OUT,LLWU_P6,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x18++0x07 line.long 0x00 "PORTE_PCR6,Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P2,PTE6,XBAR_IN5,SCI2_RxD,LLWU_P5,I2C0_SCL,,SWD_IO" textline " " elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P2,PTE6,PXBAR_IN5,SCI2_RxD,LLWU_P5,I2C0_SCL,,SWD_IO" textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0_IN2,PTE6/LLWU_P5,XBAR_IN5,UART2_RxD,,I2C0_SCL,,SWD_DIO" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P2,PTE6,XBAR_IN5,UART2_RxD,LLWU_P5,,,SWD_IO" textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTE_PCR7,Pin Control Register 7" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD6,PTE7,XBAR_OUT5,SCI2_TxD,,I2C0_SDA,,SWD_CLK" textline " " elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD6,PTE7,PXBAR_OUT5,SCI2_TxD,,I2C0_SDA,,SWD_CLK" textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE6a,PTE7,XBAR_OUT5,UART2_TxD,,I2C0_SDA,,SWD_CLK" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD6,PTE7,XBAR_OUT5,UART2_TxD,,,,SWD_CLK" textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTE_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTE_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTE_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTE_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTE_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTF" base ad:0x4004B000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x00++0x03 line.long 0x00 "PORTF_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD7,PTF0,RTCCLKOUT,TMR_2,CMP0OUT,LLWU_P4,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE7a/CMP2_IN3,PTF0/LLWU_P4,RTC_CLKOUT,QTMR0_TMR2,CMP0_OUT,?..." textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD7,PTF0,RTCCLKOUT,QT2,CMP0OUT,LLWU_P4,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD7,PTF0,RTCCLKOUT,TMR_2,CMP0OUT,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x07 line.long 0x00 "PORTF_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD0/AD8,PTF1,TMR_0,XBAR_OUT6,?..." textline " " elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD0/AD8,PTF1,QT0,XBAR_OUT6,?..." textline " " elif cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD0/AD8,PTF1,TMR_0,XBAR_OUT6,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P0/ADC0_SE8/CMP2_IN4,PTF1,QTMR0_TMR0,XBAR_OUT6,,,,LCD_P0" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD8,PTF1,TMR_0,XBAR_OUT6,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTF_PCR2,Pin Control Register 2" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD1/AD9,PTF2,CMP1OUT,RTCCLKOUT,?..." textline " " elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD1/AD9,PTF2,CMP1OUT,RTCCLKOUT,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P1/ADC0_SE9/CMP2_IN5,PTF2,CMP1_OUT,RTC_CLKOUT,,,,LCD_P1" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD9,PTF2,CMP1OUT,RTCCLKOUT,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x0C++0x13 line.long 0x00 "PORTF_PCR3,Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD2,PTF3,SPI1_SS_B,LPTMR1,SCI0_RxD,?..." textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD2,PTF3,SPI1_SS_B,LPTIM1,SCI0_RxD,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P2,PTF3/LLWU_P20,SPI1_PCS0,LPTMR0_ALT2,UART0_RxD,,,LCD_P2" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD2,PTF3,SPI1_SS_B,LPTMR1,UART0_RxD,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTF_PCR4,Pin Control Register 4" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD3,PTF4,SPI1_SCK,LPTMR0,SCI0_TxD,?..." textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD3,PTF4,SPI1_SCK,LPTIM0,SCI0_TxD,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P3,PTF4,SPI1_SCK,LPTMR0_ALT1,UART0_TxD,,,LCD_P3" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD3,PTF4,SPI1_SCK,LPTMR0,UART0_TxD,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTF_PCR5,Pin Control Register 5" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD4,PTF5,SPI1_MISO,I2C1_SCL,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P4,PTF5,SPI1_MISO,I2C1_SCL,,,,LCD_P4" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD4,PTF5,SPI1_MISO,I2C1_SCL,LLWU_P4,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTF_PCR6,Pin Control Register 6" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P5,PTF6/LLWU_P3,SPI1_MOSI,I2C1_SDA,,,,LCD_P5" textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD5,PTF6,SPI1_MOSI,I2C1_SDA,LLWU_P3,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTF_PCR7,Pin Control Register 7" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD6,PTF7,QT2,CLKOUT,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P6,PTF7,QTMR0_TMR2,CLKOUT,CMP2_OUT,,,LCD_P6" textline " " else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD6,PTF7,TMR_2,CLKOUT,?..." textline " " endif bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTF_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTF_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTF_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTF_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTF_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTF_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTG" base ad:0x4004C000 width 13. sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x00++0x03 line.long 0x00 "PORTG_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD7,PTG0,QT1,LPTIM2,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P7,PTG0,QTMR0_TMR1,LPTMR0_ALT3,,,,LCD_P7" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD7,PTG0,TMR_1,LPTMR2,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x04++0x13 line.long 0x00 "PORTG_PCR1,Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD8/AD10,PTG1,LLWU_P2,LPTMR0,?..." textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD8/AD10,PTG1,LLWU_P2,LPTIM0,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P8/ADC0_SE10,PTG1/LLWU_P2,,LPTMR0_ALT1,,,,LCD_P8" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "AD10,PTG1,LLWU_P2,LPTMR0,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTG_PCR2,Pin Control Register 2" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD9/AD11,PTG2,SPI0_SS_B,LLWU_P1,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P9/ADC0_SE11,PTG2/LLWU_P1,SPI0_PCS0,,,,,LCD_P9" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "AD11,PTG2,SPI0_SS_B,LLWU_P1,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTG_PCR3,Pin Control Register 3" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD10,PTG3,SPI0_SCK,I2C0_SCL,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P10,PTG3,SPI0_SCK,I2C0_SCL,,,,LCD_P10" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x08 8.--10. " MUX ,Pin mux control" ",PTG3,SPI0_SCK,I2C0_SCL,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTG_PCR4,Pin Control Register 4" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD11,PTG4,SPI0_MOSI,I2C0_SDA,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P11,PTG4,SPI0_MOSI,I2C0_SDA,,,,LCD_P11" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTG4,SPI0_MOSI,I2C0_SDA,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTG_PCR5,Pin Control Register 5" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD12,PTG5,SPI0_MISO,LPTMR1,?..." textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD12,PTG5,SPI0_MISO,LPTIM1,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P12,PTG5,SPI0_MISO,LPTMR0_ALT2,,,,LCD_P12" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTG5,SPI0_MISO,LPTMR1,?..." textline " " endif bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x18++0x03 line.long 0x00 "PORTG_PCR6,Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P13,PTG6/LLWU_P0,,LPTMR0_ALT3,,,,LCD_P13" textline " " elif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD13,PTG6,LLWU_P0,LPTIM2,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD13,PTG6,LLWU_P0,LPTMR2,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x1C++0x03 line.long 0x00 "PORTG_PCR7,Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P14,PTG7,,,,,,LCD_P14" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD14,PTG7,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTG_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTG_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTG_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTG_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTG_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTG_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end sif (!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5")) tree "PORTH" base ad:0x4004D000 width 13. sif (!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM14Z128CHH5*")) group.long 0x00++0x17 line.long 0x00 "PORTH_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P15,PTH0,LPUART0_CTS_b,,,,,LCD_P15" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD15,PTH0,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTH_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P16,PTH1,LPUART0_RTS_b,,,,,LCD_P16" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD16,PTH1,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTH_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P17,PTH2,LPUART0_RX,,,,,LCD_P17" textline " " else bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD17,PTH2,?..." textline " " endif bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTH_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P18,PTH3,LPUART0_TX,,,,,LCD_P18" textline " " else bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD18,PTH3,?..." textline " " endif bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTH_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P19,PTH4,,,,,,LCD_P19" textline " " else bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD19,PTH4,?..." textline " " endif bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTH_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P20,PTH5,,,,,,LCD_P20" textline " " else bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD20,PTH5,?..." textline " " endif bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" endif group.long 0x18++0x07 line.long 0x00 "PORTH_PCR6,Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTH6,SCI1_CTS,SPI1_SS_B,XBAR_IN7,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTH6,UART1_CTS_b,SPI1_PCS0,XBAR_IN7,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" ",PTH6,UART1_CTS,SPI1_SS_B,XBAR_IN7,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTH_PCR7,Pin Control Register 7" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTH7,SCI1_RTS,SPI1_SCK,XBAR_OUT7,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTH7,UART1_RTS,SPI1_SCK,XBAR_OUT7,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTH_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTH_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTH_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTH_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTH_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTH_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end endif tree "PORTI" base ad:0x4004E000 width 13. group.long 0x00++0x07 line.long 0x00 "PORTI_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P5,PTI0,SCI1_RxD,XBAR_IN8,SPI1_MISO,SPI1_MOSI,?..." textline " " elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0_IN5,PTI0/LLWU_P21,UART1_RX,XBAR_IN8,SPI1_MISO,SPI1_MOSI,?..." textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "CMP0P5,PTI0,UART1_RxD,XBAR_IN8,SPI1_MISO,SPI1_MOSI,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTI_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTI1,SCI1_TxD,XBAR_OUT8,SPI1_MOSI,SPI1_MISO,?..." textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" ",PTI1,UART1_TxD,XBAR_OUT8,SPI1_MOSI,SPI1_MISO,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x08++0x07 line.long 0x00 "PORTI_PCR2,Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P21,PTI2/LLWU_P22,LPUART0_RX,,,,,LCD_P21" textline " " else bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD21,PTI2,?..." textline " " endif bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTI_PCR3,Pin Control Register 3" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P22,PTI3,LPUART0_TX,CMP2_OUT,,,,LCD_P22" textline " " else bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD22,PTI3,?..." textline " " endif bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" endif sif cpuis("MKM34Z256VLQ7") group.long 0x10++0x0F line.long 0x00 "PORTI_PCR4,Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P44,PTI4,,,,,,LCD_P44" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTI_PCR5,Pin Control Register 5" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P45,PTI5,,,,,,LCD_P45" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTI_PCR6,Pin Control Register 6" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P46,PTI6,UART2_RX,,,,,LCD_P46" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTI_PCR7,Pin Control Register 7" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P47,PTI7,UART2_TX,,,,,LCD_P47" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" endif wgroup.long 0x80++0x07 line.long 0x00 "PORTI_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTI_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTI_ISFR,Interrupt Status Flag Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")) eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" elif cpuis("MKM34Z256VLQ7") eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" endif group.long 0xC0++0x0B line.long 0x00 "PORTI_DFER,Digital Filter Enable Register" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")) bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" elif cpuis("MKM34Z256VLQ7") bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" endif line.long 0x04 "PORTI_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTI_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") sif cpuis("MKM34Z256VLQ7") tree "PORTJ" base ad:0x40037000 width 13. group.long 0x00++0x1F line.long 0x00 "PORTJ_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P48,PTJ0,I2C1_SDA,,,,,LCD_P48" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTJ_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P49,PTJ1,I2C1_SCL,,,,,LCD_P49" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTJ_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P50,PTJ2,,,,,,LCD_P50" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTJ_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" ",PTJ3,LPUART0_RTS_b,CMP2_OUT,?..." bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTJ_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--10. " MUX ,Pin mux control" ",PTJ4,LPUART0_CTS_b,?..." bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTJ_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTJ5,LPUART0_TX,?..." bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTJ_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTJ6/LLWU_P18,LPUART0_RX,?..." bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTJ_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" ",PTJ7,?..." bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTJ_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTJ_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTJ_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTJ_DFER,Digital Filter Enable Register" bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTJ_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTJ_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTK" base ad:0x40038000 width 13. group.long 0x00++0x1F line.long 0x00 "PORTK_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ADC0_SE12,PTK0,?..." bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTK_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "ADC0_SE13,PTK1,?..." bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTK_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "ADC0_SE14,PTK2,UART0_TX,?..." bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTK_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "ADC0_SE15,PTK3/LLWU_P19,UART0_RX,?..." bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTK_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P51,PTK4,XBAR_IN9,AFE_CLK,,,,LCD_P51" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTK_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--10. " MUX ,Pin mux control" ",PTK5,UART1_RX,?..." bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTK_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--10. " MUX ,Pin mux control" ",PTK6,UART1_TX,?..." bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x1C "PORTK_PCR7,Pin Control Register 7" eventfld.long 0x1C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x1C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x1C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x1C 8.--10. " MUX ,Pin mux control" "LCD_P52,PTK7,I2C0_SCL,XBAR_OUT9,,,,LCD_P52" bitfld.long 0x1C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x1C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTK_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTK_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTK_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTK_DFER,Digital Filter Enable Register" bitfld.long 0x00 7. " DFE7 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTK_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTK_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORTL" base ad:0x40039000 width 13. group.long 0x00++0x1B line.long 0x00 "PORTL_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "LCD_P53,PTL0,I2C0_SDA,,,,,LCD_P53" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTL_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "LCD_P54,PTL1,XBAR_IN10,,,,,LCD_P54" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTL_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "LCD_P55,PTL2,XBAR_OUT10,,,,,LCD_P55" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTL_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "LCD_P56,PTL3,EWM_IN,,,,,LCD_P56" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x10 "PORTL_PCR4,Pin Control Register 4" eventfld.long 0x10 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x10 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x10 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x10 8.--10. " MUX ,Pin mux control" "LCD_P57,PTL4,EWM_OUT_b,,,,,LCD_P57" bitfld.long 0x10 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x10 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x14 "PORTL_PCR5,Pin Control Register 5" eventfld.long 0x14 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x14 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x14 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x14 8.--10. " MUX ,Pin mux control" "LCD_P58,PTL5/LLWU_P23,,,,,,LCD_P58" bitfld.long 0x14 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x14 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x18 "PORTL_PCR6,Pin Control Register 6" eventfld.long 0x18 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x18 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x18 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x18 8.--10. " MUX ,Pin mux control" "LCD_P59,PTL6,,,,,,LCD_P59" bitfld.long 0x18 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x18 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x18 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTL_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTL_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTL_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTL_DFER,Digital Filter Enable Register" bitfld.long 0x00 6. " DFE6 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTL_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTL_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end endif tree "PORTM" base ad:0x4003A000 width 13. group.long 0x00++0x0F line.long 0x00 "PORTM_PCR0,Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x00 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x00 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "VLL2/LCD_P60,PTM0,,,,,,LCD_P60" bitfld.long 0x00 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x04 "PORTM_PCR1,Pin Control Register 1" eventfld.long 0x04 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x04 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x04 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x04 8.--10. " MUX ,Pin mux control" "VLL1/LCD_P61,PTM1,,,,,,LCD_P61" bitfld.long 0x04 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x04 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x08 "PORTM_PCR2,Pin Control Register 2" eventfld.long 0x08 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x08 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x08 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x08 8.--10. " MUX ,Pin mux control" "VCAP2/LCD_P62,PTM2,,,,,,LCD_P62" bitfld.long 0x08 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x08 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " PS ,Pull select" "Pull-down,Pull-up" line.long 0x0C "PORTM_PCR3,Pin Control Register 3" eventfld.long 0x0C 24. " ISF ,Interrupt status flag" "Not detected,Detected" bitfld.long 0x0C 16.--19. " IRQC ,Interrupt configuration" "Disabled,DMA-rising,DMA-falling,DMA-either,,,,,Low,Rising,Falling,Either,High,?..." bitfld.long 0x0C 15. " LK ,Lock register" "Not locked,Locked" textline " " bitfld.long 0x0C 8.--10. " MUX ,Pin mux control" "VCAP1/LCD_P63,PTM3,,,,,,LCD_P63" bitfld.long 0x0C 2. " SRE ,Slew rate enable" "Fast,Slow" bitfld.long 0x0C 1. " PE ,Pull enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " PS ,Pull select" "Pull-down,Pull-up" wgroup.long 0x80++0x07 line.long 0x00 "PORTM_GPCLR,Global Pin Control Low Register" hexmask.long.word 0x00 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTM_GPCHR,Global Pin Control High Register" hexmask.long.word 0x04 16.--31. 1. " GPWE ,Global pin write enable" hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xA0++0x03 line.long 0x00 "PORTM_ISFR,Interrupt Status Flag Register" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag" "Not detected,Detected" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag" "Not detected,Detected" textline " " eventfld.long 0x00 0. " ISF0 ,Interrupt status flag" "Not detected,Detected" group.long 0xC0++0x0B line.long 0x00 "PORTM_DFER,Digital Filter Enable Register" bitfld.long 0x00 3. " DFE3 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DFE0 ,Digital filter enable" "Disabled,Enabled" line.long 0x04 "PORTM_DFCR,Digital Filter Clock Register" bitfld.long 0x04 0. " CS ,Clock source" "Bus,1kHz LPO" line.long 0x08 "PORTM_DFWR,Digital Filter Width Register" bitfld.long 0x08 0.--4. " FILT ,Filter length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end endif tree.end tree "SIM (System Integration Module)" base ad:0x4003E000 width 18. group.long 0x00++0x07 line.long 0x00 "SIM_SOPT1,System Options Register 1" bitfld.long 0x00 18.--19. " OSC32KSEL ,32K oscillator clock select" "OSC32KCLK,ERCLK32K,MCGIRCLK,LPO" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rbitfld.long 0x00 12.--15. " SRAMSIZE ,Returns the size of the system RAM" ",,,,,32kBSystem RAM,?..." else rbitfld.long 0x00 12.--15. " SRAMSIZE ,Returns the size of the system RAM" ",,,,,16kBSystem RAM,?..." endif line.long 0x04 "SIM_SOPT1_CFG,SOPT1 Configuration Register" bitfld.long 0x04 9. " RAMBPEN ,RAM bitline precharge" "Disabled,Enabled" bitfld.long 0x04 8. " RAMSBDIS ,Source bias disable of System SRAM arrays during VLPR and VLPW modes" "No,Yes" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x04 6.--7. " LPTMR3SEL ,LP timer channel3 select" "Pad PTD5,Pad PTG0,Pad PTG6,?..." bitfld.long 0x04 4.--5. " LPTMR2SEL ,LP timer channe2 select" "Pad PTD6,Pad PTF3,Pad PTG5,?..." textline " " bitfld.long 0x04 2.--3. " LPTMR1SEL ,LP timer channel select" "Pad PTE4,Pad PTF4,Pad PTG1,?..." bitfld.long 0x04 0.--1. " LPTMR0SEL ,LP timer channel1 select" "CMP[0],CMP[1],CMP[2],?..." elif (cpuis("MKM??Z64ACHH*")||cpuis("MKM??Z128ACHH*")||cpuis("MKM??Z64CHH*")||cpuis("MKM??Z128CHH*")) bitfld.long 0x04 6. " CMPOLPTMR0SEL ,Comparator output selection for LPTMR channel0" "CMP[1],CMP[0]" bitfld.long 0x04 2.--3. " LPTMR2SEL ,LP timer channel2 select" ",,Pad PTG5,?..." textline " " bitfld.long 0x04 0.--1. " LPTMR1SEL ,LP timer channel1 select" ",,Pad PTG1,?..." elif cpuis("MKM??Z64ACLH*")||cpuis("MKM??Z128ACLH*")||cpuis("MKM??Z64CLH*")||cpuis("MKM??Z128CLH*") bitfld.long 0x04 6. " CMPOLPTMR0SEL ,Comparator output selection for LPTMR channel0" "CMP[1],CMP[0]" bitfld.long 0x04 4.--5. " LPTMR3SEL ,LP timer channel3 select" ",Pad PTG0,Pad PTG6,?..." textline " " bitfld.long 0x04 2.--3. " LPTMR2SEL ,LP timer channel2 select" ",Pad PTF3,Pad PTG5,?..." bitfld.long 0x04 0.--1. " LPTMR1SEL ,LP timer channel1 select" ",Pad PTF4,Pad PTG1,?..." else bitfld.long 0x04 6. " CMPOLPTMR0SEL ,Comparator output selection for LPTMR channel0" "CMP[1],CMP[0]" bitfld.long 0x04 4.--5. " LPTMR3SEL ,LP timer channel3 select" "Pad PTD5,Pad PTG0,Pad PTG6,?..." textline " " bitfld.long 0x04 2.--3. " LPTMR2SEL ,LP timer channel2 select" "Pad PTD6,Pad PTF3,Pad PTG5,?..." bitfld.long 0x04 0.--1. " LPTMR1SEL ,LP timer channel1 select" "Pad PTE4,Pad PTF4,Pad PTG1,?..." endif group.long 0x1004++0x03 line.long 0x00 "SIM_CTRL_REG,System Control Register" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 31. " TMRFREEZE ,QTMR counters Freeze control" "Not freezed,Freezed" bitfld.long 0x00 26.--27. " LPUARTSRC ,LPUART clock Source configuration" "Disabled,MCGPLLCLK/MCGFLLCLK,OSCERCLK,MCGIRCLK" textline " " bitfld.long 0x00 24. " AFEOUTCLKSEL ,AFE clock output select" "Divided,No divided" bitfld.long 0x00 21.--23. " XBARCLKOUT ,XBAR clock out selection" "Disabled,Gated Core Clk,Bus Clk,LPO clock from PMC,IRC clock from MCG,MUXed 32 kHz source,MHz Oscillator external reference clock,PLL clock output from MCG" textline " " bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL selection" "MCGFLLCLK,MCGPLLCLK,BUSCLK,OSC32KCLK" bitfld.long 0x00 15. " SPI1_INV3 ,Invert the SPI1 signal output" "No inverted,Inverted" textline " " bitfld.long 0x00 14. " SPI1_INV2 ,This bit inverts the SPI1 signal output" "No inverted,Inverted" bitfld.long 0x00 13. " SPI1_INV1 ,This bit inverts the SPI1 signal output" "No inverted,Inverted" textline " " bitfld.long 0x00 12. " SPI1_INV0 ,This bit inverts the SPI1 signal output" "No inverted,Inverted" bitfld.long 0x00 11. " SPI0_INV3 ,Invert the SPI0 signal output" "No inverted,Inverted" textline " " bitfld.long 0x00 10. " SPI0_INV2 ,This bit inverts the SPI0 signal output" "No inverted,Inverted" bitfld.long 0x00 9. " SPI0_INV1 ,This bit inverts the SPI0 signal output" "No inverted,Inverted" textline " " bitfld.long 0x00 8. " SPI0_INV0 ,This bit inverts the SPI0 signal output" "No inverted,Inverted" bitfld.long 0x00 5.--7. " CLKOUT ,Clock out select" "Disabled,Gated Core Clk,Bus Clk,LPO clock from PMC,IRC clock from MCG,Muxed 32Khz source,MHz Oscillator external reference clock,PLL clock output from MCG" textline " " bitfld.long 0x00 3.--4. " ADCTRGSEL ,SAR ADC trigger clk select" "Bus,ADC,ERCLK32K,OSCCLK" bitfld.long 0x00 1. " PLLVLPEN ,PLL VLP" "Disabled,Enabled" else bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "Disabled,Gated Core Clk,Bus/Flash Clk,LPO clock from PMC,IRC clock from MCG,Muxed 32Khz source,External,PLL from MCG" bitfld.long 0x00 3.--4. " SAR_TRG_CLK_SEL ,SAR ADC trigger clk select" "Bus,ADC,ERCLK32K,OSCCLK" textline " " bitfld.long 0x00 2. " PTC2_HD_EN ,PTC2 highDrive" "Disabled,Enabled" bitfld.long 0x00 1. " PLL_VLP_EN ,PLL VLP" "Disabled,Enabled" endif bitfld.long 0x00 0. " NMIDIS ,NMI disable" "No,Yes" rgroup.long 0x1024++0x03 line.long 0x00 "SIM_SDID,System Device Identification Register" sif cpuis("MKM3*") bitfld.long 0x00 28.--31. " FAMID ,Metering family ID" ",without LCD,,with LCD,?..." elif cpuis("MKM1*") bitfld.long 0x00 28.--31. " FAMID ,Metering family ID" ",without LCD,?..." endif textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 24.--27. " SUBFAMID ,Sub-family ID" "NO AFE enabled,1 AFE enabled,2AFE enabled,3AFE enabled,4AFE enabled,?..." else bitfld.long 0x00 24.--27. " SUBFAMID ,Sub-family ID" ",,2AFE enabled,3AFE enabled,4AFE enabled,?..." endif textline " " bitfld.long 0x00 20.--23. " SERIESID ,Series ID" ",,,Metering,?..." bitfld.long 0x00 16.--19. " ATTR ,Attribute ID" "M0+ core,?..." sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 12.--15. " SRAMSIZE ,SRAM size" ",,,,,32kB SRAM,?..." else bitfld.long 0x00 12.--15. " SRAMSIZE ,SRAM size" ",,,,,16kB SRAM,?..." endif sif (cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLL5*")) textline " " bitfld.long 0x00 8.--11. " REVID ,Revision ID" ",Second Cut,?..." elif (cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")) textline " " bitfld.long 0x00 8.--11. " REVID ,Revision ID" ",,Third Cut,?..." elif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) textline " " bitfld.long 0x00 8.--11. " REVID ,Revision ID" "First Cut,?..." endif textline " " bitfld.long 0x00 4.--7. " DIEID ,Die ID" "First cut,?..." sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,64-pin,,,100-pin,128-pin,144-pin,?..." else bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,44-pin,,64-pin,,,100-pin,?..." endif group.long 0x1034++0x17 line.long 0x00 "SIM_SCGC4,System Clock Gating Control Register 4" bitfld.long 0x00 22. " SPI1 ,SPI1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 21. " SPI0 ,SPI0 clock gate control" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 18. " CMP ,High speed comparator0 clock gate control" "Disabled,Enabled" else bitfld.long 0x00 19. " CMP1 ,High speed comparator1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 18. " CMP0 ,High speed comparator0 clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x00 15. " VREF ,VREF clock gate control" "Disabled,Enabled" sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 13. " UART3 ,UART3 clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x00 12. " UART2 ,UART2 clock gate control" "Disabled,Enabled" bitfld.long 0x00 11. " UART1 ,UART1 clock gate control" "Disabled,Enabled" sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 10. " UART0 ,UART0 clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x00 8. " I2C1 ,I2C1 clock gate control" "Disabled,Enabled" bitfld.long 0x00 7. " I2C0 ,I2C0 clock gate control" "Disabled,Enabled" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 6. " OSC ,Oscillator (Mhz) clock gate control" "Disabled,Enabled" bitfld.long 0x00 4. " MCG ,MCG clock gate control" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " EWM ,External watchdog monitor clock gate control" "Disabled,Enabled" line.long 0x04 "SIM_SCGC5,System Clock Gating Control Register 5" sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x04 26. " TMR3 ,Quadtimer3 clock gate control" "Disabled,Enabled" bitfld.long 0x04 25. " TMR2 , Quadtimer2 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x04 24. " TMR1 ,Quadtimer1 clock gate control" "Disabled,Enabled" bitfld.long 0x04 23. " TMR0 ,Quadtimer0 clock gate control" "Disabled,Enabled" else bitfld.long 0x04 23. " TMR0 ,Quadtimer0 clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x04 21. " XBAR ,Peripheral crossbar clock gate control" "Disabled,Enabled" sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x04 19. " WDOG ,Watchdog clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x04 17. " IRTCREGFILE ,IRTC_REG_FILE clock gate control" "Disabled,Enabled" bitfld.long 0x04 16. " IRTC ,IRTC clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PORTI ,PCTLI clock gate control" "Disabled,Enabled" sif !cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM33Z64ACLH5")&&!cpuis("MKM33Z128ACLH5*") bitfld.long 0x04 13. " PORTH ,PCTLH clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x04 12. " PORTG ,PCTLG clock gate control" "Disabled,Enabled" bitfld.long 0x04 11. " PORTF ,PCTLF clock gate control" "Disabled,Enabled" bitfld.long 0x04 10. " PORTE ,PCTLE clock gate control" "Disabled,Enabled" textline " " sif !cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM14Z128ACHH5*") bitfld.long 0x04 9. " PORTD ,PCTLD clock gate control" "Disabled,Enabled" bitfld.long 0x04 8. " PORTC ,PCTLC clock gate control" "Disabled,Enabled" bitfld.long 0x04 7. " PORTB ,PCTLB clock gate control" "Disabled,Enabled" textline " " endif bitfld.long 0x04 6. " PORTA ,PCTLA clock gate control" "Disabled,Enabled" bitfld.long 0x04 3. " SLCD ,Segmented LCD clock gate control" "Disabled,Enabled" line.long 0x08 "SIM_SCGC6,System Clock Gating Control Register 6" sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") rbitfld.long 0x08 31. " SIM_HP ,SIM_HP clock gate control" ",Enabled" bitfld.long 0x08 30. " SIM_LP ,SIM_LP clock gate control" "Disabled,Enabled" textline " " endif bitfld.long 0x08 28. " LPTMR ,LPTMR clock gate control" "Disabled,Enabled" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 26. " PORTM ,PCTLM clock gate control" "Disabled,Enabled" sif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 25. " PORTL ,PCTLL clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x08 24. " PORTK ,PCTLK clock gate control" "Disabled,Enabled" bitfld.long 0x08 23. " PORTJ ,PCTLJ clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x08 22. " PDB ,PDB clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x08 20. " CRC ,Programmable CRC clock gate control" "Disabled,Enabled" bitfld.long 0x08 16. " AFE ,AFE clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x08 14. " PIT1 ,PIT1 clock gate control" "Disabled,Enabled" bitfld.long 0x08 13. " PIT0 ,PIT0 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ADC ,SAR ADC clock gate control" "Disabled,Enabled" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 10. " LPUART ,LPUART clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x08 9. " RNGA ,RNGA clock gate control" "Disabled,Enabled" sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x08 4. " DMAMUX3 ,DMA MUX3 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " DMAMUX2 ,DMA MUX2 clock gate control" "Disabled,Enabled" bitfld.long 0x08 2. " DMAMUX1 ,DMA MUX1 clock gate control" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " DMAMUX0 ,DMA MUX0 clock gate control" "Disabled,Enabled" else bitfld.long 0x08 1. " DMAMUX ,DMA MUX clock gate control" "Disabled,Enabled" endif textline " " bitfld.long 0x08 0. " FTFA ,FTFA clock gate control" "Disabled,Enabled" line.long 0x0C "SIM_SCGC7,System Clock Gating Control Register 7" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x0C 2. " CAU ,CAU clock gate control" "Disabled,Enabled" bitfld.long 0x0C 1. " DMA ,DMA clock gate control" "Disabled,Enabled" bitfld.long 0x0C 0. " MPU ,MPU clock gate control" "Disabled,Enabled" else bitfld.long 0x0C 1. " DMA ,DMA Clock Gate control" "Disabled,Enabled" bitfld.long 0x0C 0. " MPU ,MPU clock gate control" "Disabled,Enabled" endif line.long 0x10 "SIM_CLKDIV1,System Clock Divider Register 1" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x10 28.--31. " SYSDIV ,System clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 24.--25. " CLKDIVBUS ,Bus clock divider" "1:1,2:1,3:1,4:1" bitfld.long 0x10 16. " FLASHCLKMODE ,Flash clock mode" "Same as BUS,1/2 BUS" else bitfld.long 0x10 28.--31. " SYSDIV ,System clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 27. " SYSCLKMODE ,System clock mode" "1:1:1,2:1:1" endif line.long 0x14 "SIM_FCFG1,Flash Configuration Register 1" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rbitfld.long 0x14 24.--27. " PFSIZE ,Program flash size" ",,,,,,,128kB/4kB,,256kB/4kB,,,,,,Default" bitfld.long 0x14 1. " FLASHDOZE ,Flash doze" "No,Yes" bitfld.long 0x14 0. " FLASHDIS ,Flash disable" "No,Yes" else rbitfld.long 0x14 24.--27. " PFSIZE ,Program flash size" ",,,,,64kB/2kB,,128kB/4kB,,,,,,,,Default" bitfld.long 0x14 1. " FLASHDOZE ,Flash doze" "No,Yes" bitfld.long 0x14 0. " FLASHDIS ,Flash disable" "No,Yes" endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rgroup.long 0x1050++0x13 line.long 0x00 "SIM_FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 0x01 " MAXADDR ,Max address block" line.long 0x04 "SIM_UIDH,Unique Identification Register 0" line.long 0x08 "SIM_UIDMH,Unique Identification Register 1" line.long 0x0C "SIM_UIDML,Unique Identification Register 2" line.long 0x10 "SIM_UIDL,Unique Identification Register 3" else rgroup.long 0x1050++0x13 line.long 0x00 "SIM_FCFG2,Flash Configuration Register 2" hexmask.long.byte 0x00 24.--30. 0x01 " MAXADDR ,Max address block" line.long 0x04 "SIM_UID0,Unique Identification Register 0" line.long 0x08 "SIM_UID1,Unique Identification Register 1" line.long 0x0C "SIM_UID2,Unique Identification Register 2" line.long 0x10 "SIM_UID3,Unique Identification Register 3" endif group.long 0x106C++0x03 line.long 0x00 "SIM_MISC_CTL,Miscellaneous Control Register" bitfld.long 0x00 31. " VREFBUFPD ,VrefBuffer power down" "Not PowerDown,PowerDown" bitfld.long 0x00 30. " VREFBUFINSEL ,VrefBuffer input select" "Internal,External" bitfld.long 0x00 29. " VREFBUFOUTEN ,VrefBuffer output enable" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 28. " RTCCLKSEL ,RTC Clock select" "RTC OSC_32K,MCGIRCLK" else bitfld.long 0x00 28. " RTCCLKSEL ,RTC Clock select" "RTC OSC_32K,32K IRC" endif bitfld.long 0x00 26.--27. " TMR3PCSSEL ,Quadtimer channel3 primary count source select" "Bus,Output[9],Output[10],Disabled" bitfld.long 0x00 24.--25. " TMR2PCSSEL ,Quadtimer channel2 primary count source select" "Bus,Output[9],Output[10],Disabled" textline " " bitfld.long 0x00 22.--23. " TMR1PCSSEL ,Quadtimer channel1 primary count source select" "Bus,Output[9],Output[10],Disabled" bitfld.long 0x00 20.--21. " TMR0PCSSEL ,Quadtimer channel0 primary count source select" "Bus,Output[9],Output[10],Disabled" sif cpuis("MKM??Z64ACLL*")||cpuis("MKM??Z128ACLL*")||cpuis("MKM??Z64CLL*")||cpuis("MKM??Z128CLL*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 19. " TMR3SCSSEL ,Quadtimer channel3 secondary count source select" "PTE5/PTD1,Output[8]" elif cpuis("MKM??Z64ACLH*")||cpuis("MKM??Z128ACLH*")||cpuis("MKM??Z64CLH*")||cpuis("MKM??Z128CLH*") bitfld.long 0x00 19. " TMR3SCSSEL ,Quadtimer channel3 secondary count source select" "PTD1,Output[8]" else bitfld.long 0x00 19. " TMR3SCSSEL ,Quadtimer channel3 secondary count source select" ",Output[8]" endif textline " " sif !cpuis("MKM??Z64ACHH*")&&!cpuis("MKM??Z128ACHH*")&&!cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 18. " TMR2SCSSEL ,Quadtimer channel2 secondary count source select" "PTF7/PTF0,Output[7]" else bitfld.long 0x00 18. " TMR2SCSSEL ,Quadtimer channel2 secondary count source select" ",Output[7]" endif sif cpuis("MKM??Z64ACLL*")||cpuis("MKM??Z128ACLL*")||cpuis("MKM??Z64CLL*")||cpuis("MKM??Z128CLL*")||cpuis("MKM??Z64ACLH*")||cpuis("MKM??Z128ACLH*")||cpuis("MKM??Z64CLH*")||cpuis("MKM??Z128CLH*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") sif cpuis("*LL*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 17. " TMR1SCSSEL ,Quadtimer channel1 secondary count source select" "PTG0/PTC6,Output[6]" else bitfld.long 0x00 17. " TMR1SCSSEL ,Quadtimer channel1 secondary count source select" "PTG0,Output[6]" endif else bitfld.long 0x00 17. " TMR1SCSSEL ,Quadtimer channel1 secondary count source select" ",Output[6]" endif sif cpuis("MKM??Z64ACLL*")||cpuis("MKM??Z128ACLL*")||cpuis("MKM??Z64CLL*")||cpuis("MKM??Z128CLL*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 16. " TMR0SCSSEL ,Quadtimer channel0 secondary count source select" "PTF1/PTD5,Output[5]" else bitfld.long 0x00 16. " TMR0SCSSEL ,Quadtimer channel0 secondary count source select" "PTF1,Output[5]" endif textline " " bitfld.long 0x00 15. " TMR0PLLCLKSEL ,Timer CH0 PLL clock select" "Bus,PLL_AFE" bitfld.long 0x00 14. " EWMINSEL ,External watchdog monitor input select" "PAD,Output[32]" sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 12.--13. " XBARPITOUTSEL ,XBAR PIT output select" "PIT0[0],PIT0[1],PIT1[0],PI1[1]" endif textline " " sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 11. " UART3IRSEL ,UART3 IRDA select" "Pad RX,UART3" textline " " endif bitfld.long 0x00 10. " UART2IRSEL ,UART2 IRDA select" "Pad RX,UART2" textline " " bitfld.long 0x00 9. " UART1IRSEL ,UART1 IRDA select" "Pad RX,UART1" sif !cpuis("MKM??Z64CHH*")&&!cpuis("MKM??Z128CHH*") bitfld.long 0x00 8. " UART0IRSEL ,UART0 IRDA select" "Pad RX,UART0" endif textline " " bitfld.long 0x00 7. " UARTMODTYPE ,UART modulation type" "TypeA,TypeB" bitfld.long 0x00 6. " AFECLKPADDIR ,AFE clock pad direction" "Input,Output" bitfld.long 0x00 4.--5. " AFECLKSEL ,AFE clock source select" "MCG PLL,MCG FLL,OSC,Disabled" textline " " bitfld.long 0x00 2.--3. " DMADONESEL ,DMA done select" "DMA0,DMA1,DMA2,DMA3" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 1. " PDBADCTRG ,PDB bypass XBAR as ADC trigger" "XBAR,PDB" bitfld.long 0x00 0. " OSCON ,RTC oscillator status" "Disabled,Enabled" else bitfld.long 0x00 0.--1. " XBARAFEMODOUTSEL ,XBAR AFE modulator output select" "SigmaDelta0,SigmaDelta1,SigmaDelta2,SigmaDelta3" endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.long 0x10C8++0x07 line.long 0x00 "SIM_ADC_COMP0,ADC Compensation Register 0" hexmask.long.word 0x00 16.--31. 1. " ADCCOMPVAL1 ,ADC temperature compensation value 1" hexmask.long.word 0x00 0.--15. 1. " ADCCOMPVAL0 ,ADC temperature compensation value 0" line.long 0x04 "SIM_ADC_COMP1,ADC Compensation Register 1" hexmask.long.word 0x04 0.--15. 1. " ADCCOMPVAL2 ,ADC temperature compensation value 2" endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xF0003008 width 12. rgroup.word 0x00++0x03 line.word 0x00 "MCM_PLASC,Crossbar Switch (AXBS) Slave Configuration" bitfld.word 0x00 7. " ASC7 ,A bus slave input port 7 connection" "Absent,Present" bitfld.word 0x00 6. " ASC6 ,A bus slave input port 6 connection" "Absent,Present" bitfld.word 0x00 5. " ASC5 ,A bus slave input port 5 connection" "Absent,Present" textline " " bitfld.word 0x00 4. " ASC4 ,A bus slave input port 4 connection" "Absent,Present" bitfld.word 0x00 3. " ASC3 ,A bus slave input port 3 connection" "Absent,Present" bitfld.word 0x00 2. " ASC2 ,A bus slave input port 2 connection" "Absent,Present" textline " " bitfld.word 0x00 1. " ASC1 ,A bus slave input port 1 connection" "Absent,Present" bitfld.word 0x00 0. " ASC0 ,A bus slave input port 0 connection" "Absent,Present" line.word 0x02 "MCM_PLAMC,Crossbar Switch (AXBS) Master Configuration" bitfld.word 0x02 7. " AMC7 ,A bus master input port 7 connection" "Absent,Present" bitfld.word 0x02 6. " AMC6 ,A bus master input port 6 connection" "Absent,Present" bitfld.word 0x02 5. " AMC5 ,A bus master input port 5 connection" "Absent,Present" textline " " bitfld.word 0x02 4. " AMC4 ,A bus master input port 4 connection" "Absent,Present" bitfld.word 0x02 3. " AMC3 ,A bus master input port 3 connection" "Absent,Present" bitfld.word 0x02 2. " AMC2 ,A bus master input port 2 connection" "Absent,Present" textline " " bitfld.word 0x02 1. " AMC1 ,A bus master input port 1 connection" "Absent,Present" bitfld.word 0x02 0. " AMC0 ,A bus master input port 0 connection" "Absent,Present" group.long 0x04++0x03 line.long 0x00 "MCM_PLACR,Platform Control Register" bitfld.long 0x00 16. " ESFC ,Enable stalling flash controller" "Disabled,Enabled" bitfld.long 0x00 15. " DFCS ,Disable flash controller speculation" "No,Yes" bitfld.long 0x00 14. " EFDS ,Enable flash data speculation" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DFCC ,Disable flash controller cache" "No,Yes" bitfld.long 0x00 12. " DFCIC ,Disable flash controller instruction caching" "No,Yes" bitfld.long 0x00 11. " DFCDA ,Disable flash controller data caching" "No,Yes" textline " " eventfld.long 0x00 10. " CFCC ,Clear flash controller cache" "No effect,Clear" bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin" group.long 0x28++0x03 line.long 0x00 "MCM_PID,Process ID register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID For MPU" group.long 0x38++0x03 line.long 0x00 "MCM_CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,CPOREQ clear" rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Not completed,Completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" group.long 0x78++0x03 line.long 0x00 "MCM_MATCR0,Master Attribute Configuration Register" bitfld.long 0x00 23. " RO2 ,Read-only master 2" "Writes allowed,Writes ignored" bitfld.long 0x00 16.--18. " ATC2 ,Attribute configuration master 2" "Privileged-Secure,Privileged-Secure,User-Secure,User-Nonsecure,Privileged||User-Secure,Privileged||User-Nonsecure,Privileged||User-Secure||Nonsecure,Privileged||User-Secure||Nonsecure" textline " " bitfld.long 0x00 7. " RO0 ,Read-only master 0" "Writes allowed,Writes ignored" bitfld.long 0x00 0.--2. " ATC0 ,Attribute configuration master 0" "Privileged-Secure,Privileged-Secure,User-Secure,User-Nonsecure,Privileged||User-Secure,Privileged||User-Nonsecure,Privileged||User-Secure||Nonsecure,Privileged||User-Secure||Nonsecure" width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007B000 width 11. rgroup.byte 0x00++0x01 line.byte 0x00 "RCM_SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on-reset" "Not occurred,Occurred" bitfld.byte 0x00 6. " PIN ,External reset pin" "Not occurred,Occurred" bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " LOL ,Loss-of-Lock reset" "Not occurred,Occurred" bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not occurred,Occurred" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not occurred,Occurred" textline " " bitfld.byte 0x00 0. " WAKEUP ,Low leakage wakeup reset" "Not occurred,Occurred" line.byte 0x01 "RCM_SRS1,System Reset Status Register 1" bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not occurred,Occurred" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not occurred,Occurred" bitfld.byte 0x01 2. " SW ,Software" "Not occurred,Occurred" textline " " bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not occurred,Occurred" group.byte 0x04++0x01 line.byte 0x00 "RCM_RPFC,Reset Pin Filter Control register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "Disabled,Bus clock,LPO clock,?..." line.byte 0x01 "RCM_RPFW,Reset Pin Filter Width register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Reset pin filter bus clock select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x08++0x01 line.byte 0x00 "RCM_SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on-reset" "Not occurred,Occurred" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "Not occurred,Occurred" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "Not occurred,Occurred" textline " " eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "Not occurred,Occurred" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not occurred,Occurred" eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not occurred,Occurred" line.byte 0x01 "RCM_SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "Not occurred,Occurred" eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "Not occurred,Occurred" eventfld.byte 0x01 2. " SSW ,Sticky software" "Not occurred,Occurred" textline " " eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "Not occurred,Occurred" endif width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 width 14. group.byte 0x00++0x02 line.byte 0x00 "SMC_PMPROT,Power Mode Protection Register" bitfld.byte 0x00 5. " AVLP ,Allow very-low-power modes" "Not allowed,Allowed" bitfld.byte 0x00 1. " AVLLS ,Allow very-low-leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "SMC_PMCTRL,Power Mode Control Register" bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "RUN,,VLPR,?..." rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Successful,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "STOP,,VLPS,,VLLSx,?..." line.byte 0x02 "SMC_STOPCTRL,Stop Control Register" bitfld.byte 0x02 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x02 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x02 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." rgroup.byte 0x03++0x00 line.byte 0x00 "SMC_PMSTAT,Power Mode Status Register" bitfld.byte 0x00 6. " PMSTAT[6] ,Current power mode is VLLS" "No,Yes" bitfld.byte 0x00 4. " [4] ,Current power mode is VLPS" "No,Yes" bitfld.byte 0x00 3. " [3] ,Current power mode is VLPW" "No,Yes" textline " " bitfld.byte 0x00 2. " [2] ,Current power mode is VLPR" "No,Yes" bitfld.byte 0x00 1. " [1] ,Current power mode is STOP" "No,Yes" bitfld.byte 0x00 0. " [0] ,Current power mode is RUN" "No,Yes" width 0x0B tree.end tree "XBAR (Inter-Peripheral Crossbar Switch)" base ad:0x40055000 width 12. sif (cpuis("MKM34Z256VLQ7")) group.word 0x00++0x02B line.word 0x00 "XBAR_SEL0,Crossbar Select Register 0" bitfld.word 0x00 8.--13. " SEL1 ,XBAR_OUT1 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x00 0.--5. " SEL0 ,XBAR_OUT0 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x02 "XBAR_SEL1,Crossbar Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBAR_OUT3 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBAR_OUT2 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x04 "XBAR_SEL2,Crossbar Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBAR_OUT5 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBAR_OUT4 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x06 "XBAR_SEL3,Crossbar Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBAR_OUT7 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBAR_OUT6 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x08 "XBAR_SEL4,Crossbar Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBAR_OUT9 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBAR_OUT8 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0A "XBAR_SEL5,Crossbar Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBAR_OUT11 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBAR_OUT10 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0C "XBAR_SEL6,Crossbar Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBAR_OUT13 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBAR_OUT12 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0E "XBAR_SEL7,Crossbar Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBAR_OUT15 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBAR_OUT14 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x10 "XBAR_SEL8,Crossbar Select Register 8" bitfld.word 0x10 8.--13. " SEL17 ,XBAR_OUT17 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x10 0.--5. " SEL16 ,XBAR_OUT16 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x12 "XBAR_SEL9,Crossbar Select Register 9" bitfld.word 0x12 8.--13. " SEL19 ,XBAR_OUT19 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x12 0.--5. " SEL18 ,XBAR_OUT18 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x14 "XBAR_SEL10,Crossbar Select Register 10" bitfld.word 0x14 8.--13. " SEL21 ,XBAR_OUT21 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x14 0.--5. " SEL20 ,XBAR_OUT20 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x16 "XBAR_SEL11,Crossbar Select Register 11" bitfld.word 0x16 8.--13. " SEL23 ,XBAR_OUT23 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x16 0.--5. " SEL22 ,XBAR_OUT22 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x18 "XBAR_SEL12,Crossbar Select Register 12" bitfld.word 0x18 8.--13. " SEL25 ,XBAR_OUT25 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x18 0.--5. " SEL24 ,XBAR_OUT24 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1A "XBAR_SEL13,Crossbar Select Register 13" bitfld.word 0x1A 8.--13. " SEL27 ,XBAR_OUT27 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1A 0.--5. " SEL26 ,XBAR_OUT26 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1C "XBAR_SEL14,Crossbar Select Register 14" bitfld.word 0x1C 8.--13. " SEL29 ,XBAR_OUT29 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1C 0.--5. " SEL28 ,XBAR_OUT28 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1E "XBAR_SEL15,Crossbar Select Register 15" bitfld.word 0x1E 8.--13. " SEL31 ,XBAR_OUT31 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1E 0.--5. " SEL30 ,XBAR_OUT30 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x20 "XBAR_SEL16,Crossbar Select Register 16" bitfld.word 0x20 8.--13. " SEL33 ,XBAR_OUT33 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x20 0.--5. " SEL32 ,XBAR_OUT32 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x22 "XBAR_SEL17,Crossbar Select Register 17" bitfld.word 0x22 8.--13. " SEL35 ,XBAR_OUT35 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x22 0.--5. " SEL34 ,XBAR_OUT34 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x24 "XBAR_SEL18,Crossbar Select Register 18" bitfld.word 0x24 8.--13. " SEL37 ,XBAR_OUT37 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x24 0.--5. " SEL36 ,XBAR_OUT36 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x26 "XBAR_SEL19,Crossbar Select Register 19" bitfld.word 0x26 8.--13. " SEL39 ,XBAR_OUT39 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x26 0.--5. " SEL38 ,XBAR_OUT38 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x28 "XBAR_SEL20,Crossbar Select Register 20" bitfld.word 0x28 8.--13. " SEL41 ,XBAR_OUT41 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x28 0.--5. " SEL40 ,XBAR_OUT40 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x2A "XBAR_SEL21,Crossbar Select Register 21" bitfld.word 0x2A 8.--13. " SEL43 ,XBAR_OUT43 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x2A 0.--5. " SEL42 ,XBAR_OUT42 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,XBAR_IN pin 9,XBAR_IN pin 10,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." elif (cpuis("MKM34Z256VLL7*")) group.word 0x00++0x02B line.word 0x00 "XBAR_SEL0,Crossbar Select Register 0" bitfld.word 0x00 8.--13. " SEL1 ,XBAR_OUT1 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x00 0.--5. " SEL0 ,XBAR_OUT0 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x02 "XBAR_SEL1,Crossbar Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBAR_OUT3 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBAR_OUT2 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x04 "XBAR_SEL2,Crossbar Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBAR_OUT5 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBAR_OUT4 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x06 "XBAR_SEL3,Crossbar Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBAR_OUT7 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBAR_OUT6 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x08 "XBAR_SEL4,Crossbar Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBAR_OUT9 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBAR_OUT8 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0A "XBAR_SEL5,Crossbar Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBAR_OUT11 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBAR_OUT10 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0C "XBAR_SEL6,Crossbar Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBAR_OUT13 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBAR_OUT12 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x0E "XBAR_SEL7,Crossbar Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBAR_OUT15 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBAR_OUT14 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x10 "XBAR_SEL8,Crossbar Select Register 8" bitfld.word 0x10 8.--13. " SEL17 ,XBAR_OUT17 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x10 0.--5. " SEL16 ,XBAR_OUT16 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x12 "XBAR_SEL9,Crossbar Select Register 9" bitfld.word 0x12 8.--13. " SEL19 ,XBAR_OUT19 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x12 0.--5. " SEL18 ,XBAR_OUT18 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x14 "XBAR_SEL10,Crossbar Select Register 10" bitfld.word 0x14 8.--13. " SEL21 ,XBAR_OUT21 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x14 0.--5. " SEL20 ,XBAR_OUT20 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x16 "XBAR_SEL11,Crossbar Select Register 11" bitfld.word 0x16 8.--13. " SEL23 ,XBAR_OUT23 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x16 0.--5. " SEL22 ,XBAR_OUT22 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x18 "XBAR_SEL12,Crossbar Select Register 12" bitfld.word 0x18 8.--13. " SEL25 ,XBAR_OUT25 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x18 0.--5. " SEL24 ,XBAR_OUT24 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1A "XBAR_SEL13,Crossbar Select Register 13" bitfld.word 0x1A 8.--13. " SEL27 ,XBAR_OUT27 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1A 0.--5. " SEL26 ,XBAR_OUT26 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1C "XBAR_SEL14,Crossbar Select Register 14" bitfld.word 0x1C 8.--13. " SEL29 ,XBAR_OUT29 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1C 0.--5. " SEL28 ,XBAR_OUT28 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x1E "XBAR_SEL15,Crossbar Select Register 15" bitfld.word 0x1E 8.--13. " SEL31 ,XBAR_OUT31 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x1E 0.--5. " SEL30 ,XBAR_OUT30 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x20 "XBAR_SEL16,Crossbar Select Register 16" bitfld.word 0x20 8.--13. " SEL33 ,XBAR_OUT33 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x20 0.--5. " SEL32 ,XBAR_OUT32 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x22 "XBAR_SEL17,Crossbar Select Register 17" bitfld.word 0x22 8.--13. " SEL35 ,XBAR_OUT35 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x22 0.--5. " SEL34 ,XBAR_OUT34 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x24 "XBAR_SEL18,Crossbar Select Register 18" bitfld.word 0x24 8.--13. " SEL37 ,XBAR_OUT37 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x24 0.--5. " SEL36 ,XBAR_OUT36 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x26 "XBAR_SEL19,Crossbar Select Register 19" bitfld.word 0x26 8.--13. " SEL39 ,XBAR_OUT39 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x26 0.--5. " SEL38 ,XBAR_OUT38 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x28 "XBAR_SEL20,Crossbar Select Register 20" bitfld.word 0x28 8.--13. " SEL41 ,XBAR_OUT41 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x28 0.--5. " SEL40 ,XBAR_OUT40 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." line.word 0x2A "XBAR_SEL21,Crossbar Select Register 21" bitfld.word 0x2A 8.--13. " SEL43 ,XBAR_OUT43 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." bitfld.word 0x2A 0.--5. " SEL42 ,XBAR_OUT42 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT 0 TIF0,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA Done Signal,,,CMP2 Output,PIT 0 TIF1,PIT 1 TIF0,PIT 1 TIF1,AFE MOD 1 DATA_OUT,AFE MOD 2 DATA_OUT,AFE MOD 3 DATA_OUT,SAR ADC COCO A,SAR ADC COCO B,SAR ADC COCO C,SAR ADC COCO D,PDB0 CH0 Pre-trigger 0,PDB0 CH0 Pre-trigger 1,PDB0 CH0 Pre-trigger 2,PDB0 CH0 Pre-trigger 3,PDB0 CH0 Trigger,PDB0 Pulse-Out 0,?..." elif cpuis("MKM??Z64ACLL*")||cpuis("MKM??Z128ACLL*")||cpuis("MKM??Z64CLL*")||cpuis("MKM??Z128CLL*") group.word 0x00++0x021 line.word 0x00 "XBAR_SEL0,Crossbar Select Register 0" bitfld.word 0x00 8.--13. " SEL43 ,XBAR_OUT43 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x00 0.--5. " SEL42 ,XBAR_OUT42 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x02 "XBAR_SEL1,Crossbar Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBAR_OUT3 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBAR_OUT2 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x04 "XBAR_SEL2,Crossbar Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBAR_OUT5 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBAR_OUT4 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x06 "XBAR_SEL3,Crossbar Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBAR_OUT7 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBAR_OUT6 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x08 "XBAR_SEL4,Crossbar Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBAR_OUT9 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBAR_OUT8 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0A "XBAR_SEL5,Crossbar Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBAR_OUT11 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBAR_OUT10 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0C "XBAR_SEL6,Crossbar Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBAR_OUT13 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBAR_OUT12 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0E "XBAR_SEL7,Crossbar Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBAR_OUT15 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBAR_OUT14 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x10 "XBAR_SEL8,Crossbar Select Register 8" bitfld.word 0x10 8.--13. " SEL17 ,XBAR_OUT17 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x10 0.--5. " SEL16 ,XBAR_OUT16 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x12 "XBAR_SEL9,Crossbar Select Register 9" bitfld.word 0x12 8.--13. " SEL19 ,XBAR_OUT19 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x12 0.--5. " SEL18 ,XBAR_OUT18 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x14 "XBAR_SEL10,Crossbar Select Register 10" bitfld.word 0x14 8.--12. " SEL21 ,XBAR_OUT21 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x14 0.--4. " SEL20 ,XBAR_OUT20 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x16 "XBAR_SEL11,Crossbar Select Register 11" bitfld.word 0x16 8.--13. " SEL23 ,XBAR_OUT23 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x16 0.--5. " SEL22 ,XBAR_OUT22 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x18 "XBAR_SEL12,Crossbar Select Register 12" bitfld.word 0x18 8.--12. " SEL25 ,XBAR_OUT25 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x18 0.--4. " SEL24 ,XBAR_OUT24 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x1A "XBAR_SEL13,Crossbar Select Register 13" bitfld.word 0x1A 8.--13. " SEL27 ,XBAR_OUT27 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1A 0.--5. " SEL26 ,XBAR_OUT26 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1C "XBAR_SEL14,Crossbar Select Register 14" bitfld.word 0x1C 8.--13. " SEL29 ,XBAR_OUT29 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1C 0.--5. " SEL28 ,XBAR_OUT28 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1E "XBAR_SEL15,Crossbar Select Register 15" bitfld.word 0x1E 8.--12. " SEL31 ,XBAR_OUT31 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x1E 0.--4. " SEL30 ,XBAR_OUT30 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x20 "XBAR_SEL16,Crossbar Select Register 16" bitfld.word 0x20 0.--5. " SEL32 ,XBAR_OUT32 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,XBAR_IN pin 2,XBAR_IN pin 3,XBAR_IN pin 4,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." elif cpuis("MKM??Z64ACLH*")||cpuis("MKM??Z128ACLH*")||cpuis("MKM??Z64CLH*")||cpuis("MKM??Z128CLH*") group.word 0x00++0x021 line.word 0x00 "XBAR_SEL0,Crossbar Select Register 0" bitfld.word 0x00 8.--13. " SEL43 ,XBAR_OUT43 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x00 0.--5. " SEL42 ,XBAR_OUT42 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x02 "XBAR_SEL1,Crossbar Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBAR_OUT3 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBAR_OUT2 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x04 "XBAR_SEL2,Crossbar Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBAR_OUT5 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBAR_OUT4 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x06 "XBAR_SEL3,Crossbar Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBAR_OUT7 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBAR_OUT6 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x08 "XBAR_SEL4,Crossbar Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBAR_OUT9 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBAR_OUT8 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0A "XBAR_SEL5,Crossbar Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBAR_OUT11 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBAR_OUT10 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0C "XBAR_SEL6,Crossbar Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBAR_OUT13 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBAR_OUT12 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0E "XBAR_SEL7,Crossbar Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBAR_OUT15 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBAR_OUT14 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x10 "XBAR_SEL8,Crossbar Select Register 8" bitfld.word 0x10 8.--13. " SEL17 ,XBAR_OUT17 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x10 0.--5. " SEL16 ,XBAR_OUT16 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x12 "XBAR_SEL9,Crossbar Select Register 9" bitfld.word 0x12 8.--13. " SEL19 ,XBAR_OUT19 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x12 0.--5. " SEL18 ,XBAR_OUT18 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x14 "XBAR_SEL10,Crossbar Select Register 10" bitfld.word 0x14 8.--12. " SEL21 ,XBAR_OUT21 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x14 0.--4. " SEL20 ,XBAR_OUT20 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x16 "XBAR_SEL11,Crossbar Select Register 11" bitfld.word 0x16 8.--13. " SEL23 ,XBAR_OUT23 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x16 0.--5. " SEL22 ,XBAR_OUT22 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x18 "XBAR_SEL12,Crossbar Select Register 12" bitfld.word 0x18 8.--12. " SEL25 ,XBAR_OUT25 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x18 0.--4. " SEL24 ,XBAR_OUT24 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x1A "XBAR_SEL13,Crossbar Select Register 13" bitfld.word 0x1A 8.--13. " SEL27 ,XBAR_OUT27 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1A 0.--5. " SEL26 ,XBAR_OUT26 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1C "XBAR_SEL14,Crossbar Select Register 14" bitfld.word 0x1C 8.--13. " SEL29 ,XBAR_OUT29 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1C 0.--5. " SEL28 ,XBAR_OUT28 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1E "XBAR_SEL15,Crossbar Select Register 15" bitfld.word 0x1E 8.--12. " SEL31 ,XBAR_OUT31 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x1E 0.--4. " SEL30 ,XBAR_OUT30 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x20 "XBAR_SEL16,Crossbar Select Register 16" bitfld.word 0x20 0.--5. " SEL32 ,XBAR_OUT32 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,XBAR_IN pin 1,,XBAR_IN pin 3,,XBAR_IN pin 5,,,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." elif cpuis("MKM??Z64ACHH*")||cpuis("MKM??Z128ACHH*")||cpuis("MKM??Z64CHH*")||cpuis("MKM??Z128CHH*") group.word 0x00++0x021 line.word 0x00 "XBAR_SEL0,Crossbar Select Register 0" bitfld.word 0x00 8.--13. " SEL43 ,XBAR_OUT43 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x00 0.--5. " SEL42 ,XBAR_OUT42 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x02 "XBAR_SEL1,Crossbar Select Register 1" bitfld.word 0x02 8.--13. " SEL3 ,XBAR_OUT3 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x02 0.--5. " SEL2 ,XBAR_OUT2 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x04 "XBAR_SEL2,Crossbar Select Register 2" bitfld.word 0x04 8.--13. " SEL5 ,XBAR_OUT5 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x04 0.--5. " SEL4 ,XBAR_OUT4 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x06 "XBAR_SEL3,Crossbar Select Register 3" bitfld.word 0x06 8.--13. " SEL7 ,XBAR_OUT7 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x06 0.--5. " SEL6 ,XBAR_OUT6 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x08 "XBAR_SEL4,Crossbar Select Register 4" bitfld.word 0x08 8.--13. " SEL9 ,XBAR_OUT9 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x08 0.--5. " SEL8 ,XBAR_OUT8 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0A "XBAR_SEL5,Crossbar Select Register 5" bitfld.word 0x0A 8.--13. " SEL11 ,XBAR_OUT11 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0A 0.--5. " SEL10 ,XBAR_OUT10 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0C "XBAR_SEL6,Crossbar Select Register 6" bitfld.word 0x0C 8.--13. " SEL13 ,XBAR_OUT13 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0C 0.--5. " SEL12 ,XBAR_OUT12 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x0E "XBAR_SEL7,Crossbar Select Register 7" bitfld.word 0x0E 8.--13. " SEL15 ,XBAR_OUT15 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x0E 0.--5. " SEL14 ,XBAR_OUT14 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x10 "XBAR_SEL8,Crossbar Select Register 8" bitfld.word 0x10 8.--13. " SEL17 ,XBAR_OUT17 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x10 0.--5. " SEL16 ,XBAR_OUT16 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x12 "XBAR_SEL9,Crossbar Select Register 9" bitfld.word 0x12 8.--13. " SEL19 ,XBAR_OUT19 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x12 0.--5. " SEL18 ,XBAR_OUT18 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x14 "XBAR_SEL10,Crossbar Select Register 10" bitfld.word 0x14 8.--12. " SEL21 ,XBAR_OUT21 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x14 0.--4. " SEL20 ,XBAR_OUT20 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x16 "XBAR_SEL11,Crossbar Select Register 11" bitfld.word 0x16 8.--13. " SEL23 ,XBAR_OUT23 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x16 0.--5. " SEL22 ,XBAR_OUT22 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x18 "XBAR_SEL12,Crossbar Select Register 12" bitfld.word 0x18 8.--12. " SEL25 ,XBAR_OUT25 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x18 0.--4. " SEL24 ,XBAR_OUT24 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x1A "XBAR_SEL13,Crossbar Select Register 13" bitfld.word 0x1A 8.--13. " SEL27 ,XBAR_OUT27 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1A 0.--5. " SEL26 ,XBAR_OUT26 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1C "XBAR_SEL14,Crossbar Select Register 14" bitfld.word 0x1C 8.--13. " SEL29 ,XBAR_OUT29 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." bitfld.word 0x1C 0.--5. " SEL28 ,XBAR_OUT28 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." line.word 0x1E "XBAR_SEL15,Crossbar Select Register 15" bitfld.word 0x1E 8.--12. " SEL31 ,XBAR_OUT31 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" bitfld.word 0x1E 0.--4. " SEL30 ,XBAR_OUT30 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete" line.word 0x20 "XBAR_SEL16,Crossbar Select Register 16" bitfld.word 0x20 0.--5. " SEL32 ,XBAR_OUT32 input selection" "VDD,VSS,AFE_CLK,AFE MOD 0 DATA_OUT,LPTimer_OUT,Clock_OUT,Quad_TMR_OUT ch 0,Quad_TMR_OUT ch 1,Quad_TMR_OUT ch 2,Quad_TMR_OUT ch 3,IRTC_CLK_OUT,CMP0 output,CMP1 output,IRTC Alarm_OUT,UART_Tx_OUT,EWM_OUT,PIT output,XBAR_IN pin 0,,,,,XBAR_IN pin 5,XBAR_IN pin 6,XBAR_IN pin 7,XBAR_IN pin 8,OR'ed conversion complete flag (SAR ADC),OR'ed conversion complete flag (AFE),AFE CH 0 CONV complete,AFE CH 1 CONV complete,AFE CH 2 CONV complete,AFE CH 3 CONV complete,DMA done signal,?..." endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.word 0x2C++0x03 line.word 0x00 "XBAR_CTRL0,Crossbar Control Register 0" eventfld.word 0x00 12. " STS1 ,Edge detection status for XBAR_OUT1" "Not detected,Detected" bitfld.word 0x00 10.--11. " EDGE1 ,Active edge for edge detection on XBAR_OUT1" "None,Rising,Falling,Both" textline " " bitfld.word 0x00 9. " IEN1 ,Interrupt Enable for XBAR_OUT1" "Disabled,Enabled" bitfld.word 0x00 8. " DEN1 ,DMA Enable for XBAR_OUT1" "Disabled,Enabled" textline " " eventfld.word 0x00 4. " STS0 ,Edge detection status for XBAR_OUT0" "Not detected,Detected" bitfld.word 0x00 2.--3. " EDGE0 ,Active edge for edge detection on XBAR_OUT0" "None,Rising,Falling,Both" textline " " bitfld.word 0x00 1. " IEN0 ,Interrupt Enable for XBAR_OUT0" "Disabled,Enabled" bitfld.word 0x00 0. " DEN0 ,DMA Enable for XBAR_OUT0" "Disabled,Enabled" line.word 0x02 "XBAR_CTRL1,Crossbar Control Register 0" eventfld.word 0x02 12. " STS3 ,Edge detection status for XBAR_OUT3" "Not detected,Detected" bitfld.word 0x02 10.--11. " EDGE3 ,Active edge for edge detection on XBAR_OUT3" "None,Rising,Falling,Both" textline " " bitfld.word 0x02 9. " IEN3 ,Interrupt Enable for XBAR_OUT3" "Disabled,Enabled" bitfld.word 0x02 8. " DEN3 ,DMA Enable for XBAR_OUT3" "Disabled,Enabled" textline " " eventfld.word 0x02 4. " STS2 ,Edge detection status for XBAR_OUT2" "Not detected,Detected" bitfld.word 0x02 2.--3. " EDGE2 ,Active edge for edge detection on XBAR_OUT2" "None,Rising,Falling,Both" textline " " bitfld.word 0x02 1. " IEN2 ,Interrupt Enable for XBAR_OUT2" "Disabled,Enabled" bitfld.word 0x02 0. " DEN2 ,DMA Enable for XBAR_OUT2" "Disabled,Enabled" else group.word 0x22++0x01 line.word 0x00 "XBAR_CTRL0,Crossbar Control Register 0" eventfld.word 0x00 4. " STS0 ,Edge detection status for XBAR_OUT0" "Not detected,Detected" bitfld.word 0x00 2.--3. " EDGE0 ,Active edge for edge detection on XBAR_OUT0" "None,Rising,Falling,Both" textline " " bitfld.word 0x00 1. " IEN0 ,Interrupt Enable for XBAR_OUT0" "Disabled,Enabled" bitfld.word 0x00 0. " DEN0 ,DMA Enable for XBAR_OUT0" "Disabled,Enabled" endif width 0x0B tree.end sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "MMAU (Memory Mapped Arithmetic Unit)" base ad:0xF0004000 width 17. group.long 0x00++0x0B line.long 0x00 "MMAU_X0,Operand Register X0" line.long 0x04 "MMAU_X1,Operand Register X1" line.long 0x08 "MMAU_X2,Operand Register X2" if ((per.l(ad:0xF0004000+0x18)&0x80000000)==0x80000000) group.long 0x0C++0x0F line.long 0x00 "MMAU_X3,Operand Register X3" line.long 0x04 "MMAU_A0,Accumulator Register A0" line.long 0x08 "MMAU_A1,Accumulator Register A1" line.long 0x0C "MMAU_CSR,Control/Status Register" rbitfld.long 0x0A 31. " BUSY ,Indicator operations performance" "Idle,Busy" rbitfld.long 0x0A 20.--23. " HDR ,Hardware Revision Level" "Current Hardware Revision Level is 0000,?..." bitfld.long 0x0A 17. " SO ,Supervisor-Only" "Disabled,Enabled" bitfld.long 0x0A 16. " DRE ,DMA Request Enable" "Disabled,Enabled" textline " " bitfld.long 0x0A 14. " DZIE ,Divide-by-Zero Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0A 13. " VIE ,Divide/Multiply Overflow (V flag) Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0A 12. " QIE ,Accumulation Overflow (Q flag) Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x0A 6. " DZIF ,DZ Interrupt Flag: Divide by Zero" "No interrupted,Interupted" textline " " rbitfld.long 0x0A 5. " VIF ,V Interrupt Flag: Multiply or Divide overflow" "No interrupted,Interupted" rbitfld.long 0x0A 4. " QIF ,Q Interrupt Flag: Accumulation Overflow Interrupt Status," "No interrupted,Interupted" bitfld.long 0x0A 3. " N ,N flag: Signed calculation result is negative" "Zero or positive,Negative" bitfld.long 0x0A 2. " DZ ,DZ flag: Divide by Zero" "Not zero,Zero" textline " " bitfld.long 0x0A 1. " V ,V flag: Multiply or Divide overflow" "No overflow,Overflow" bitfld.long 0x0A 0. " Q ,Q flag: Accumulation Overflow" "No overflow,Overflow" else rgroup.long 0x0C++0x03 line.long 0x00 "MMAU_X3,Operand Register X3" hgroup.long 0x10++0x07 hide.long 0x00 "MMAU_A0,Accumulator Register A0" in hide.long 0x04 "MMAU_A1,Accumulator Register A1" in rgroup.long 0x18++0x03 line.long 0x00 "MMAU_CSR,Control/Status Register" bitfld.long 0x00 31. " BUSY ,Indicator operations performance" "Idle,Busy" bitfld.long 0x00 20.--23. " HDR ,Hardware Revision Level" "Current Hardware Revision Level is 0000,?..." bitfld.long 0x00 17. " SO ,Supervisor-Only" "Disabled,Enabled" bitfld.long 0x00 16. " DRE ,DMA Request Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DZIE ,Divide-by-Zero Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. " VIE ,Divide/Multiply Overflow (V flag) Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. " QIE ,Accumulation Overflow (Q flag) Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " DZIF ,DZ Interrupt Flag" "No interrupted,Interupted" textline " " bitfld.long 0x00 5. " VIF ,V Interrupt Flag" "No interrupted,Interupted" bitfld.long 0x00 4. " QIF ,Q Interrupt Flag" "No interrupted,Interupted" bitfld.long 0x00 3. " N ,N flag" "Zero or positive,Negative" bitfld.long 0x00 2. " DZ ,DZ flag" "Not zero,Zero" textline " " bitfld.long 0x00 1. " V ,V flag" "No overflow,Overflow" bitfld.long 0x00 0. " Q ,Q flag" "No overflow,Overflow" endif wgroup.long 0x1C++0x03 line.long 0x00 "MMAU_CSR_IF_CLR,CSR Interrupt Flags Clearance Register" eventfld.long 0x00 6. " DZIF ,DZ Interrupt Flag" "Not Occured,Occured" eventfld.long 0x00 5. " VIF ,V Interrupt Flag" "Not Occured,Occured" eventfld.long 0x00 4. " QIF ,Q Interrupt Flag" "Not Occured,Occured" bitfld.long 0x00 3. " N ,N flag" "Not Occured,Occured" textline " " bitfld.long 0x00 2. " DZ ,DZ flag" "Not Occured,Occured" bitfld.long 0x00 1. " V ,V flag" "Not Occured,Occured" bitfld.long 0x00 0. " Q ,Q flag" "Not Occured,Occured" width 0x0B tree.end endif tree "LLWU (Low-Leakage Wakeup Unit)" base ad:0x4007C000 width 12. group.byte 0x00++0x01 line.byte 0x00 "LLWU_PE1,LLWU Pin Enable 1 Register" sif (cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Rising edge,Falling edge,Any edge" textline " " else bitfld.byte 0x00 6.--7. " WUPE3 ,Wakeup pin enable for LLWU_P3" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE2 ,Wakeup pin enable for LLWU_P2" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE1 ,Wakeup pin enable for LLWU_P1" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x00 0.--1. " WUPE0 ,Wakeup pin enable for LLWU_P0" "Disabled,Rising edge,Falling edge,Any edge" endif line.byte 0x01 "LLWU_PE2,LLWU Pin Enable 2 Register" sif (cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any edge" elif (cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z128CLH5*")) bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any edge" else bitfld.byte 0x01 6.--7. " WUPE7 ,Wakeup pin enable for LLWU_P7" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 4.--5. " WUPE6 ,Wakeup pin enable for LLWU_P6" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 2.--3. " WUPE5 ,Wakeup pin enable for LLWU_P5" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x01 0.--1. " WUPE4 ,Wakeup pin enable for LLWU_P4" "Disabled,Rising edge,Falling edge,Any edge" endif sif !cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM14Z128ACHH5*") group.byte 0x02++0x00 line.byte 0x00 "LLWU_PE3,LLWU Pin Enable 3 Register" sif (cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z128CLH5*")) bitfld.byte 0x00 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any edge" else bitfld.byte 0x00 6.--7. " WUPE11 ,Wakeup pin enable for LLWU_P11" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE10 ,Wakeup pin enable for LLWU_P10" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE9 ,Wakeup pin enable for LLWU_P9" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x00 0.--1. " WUPE8 ,Wakeup pin enable for LLWU_P8" "Disabled,Rising edge,Falling edge,Any edge" endif endif group.byte 0x03++0x00 line.byte 0x00 "LLWU_PE4,LLWU Pin Enable 4 Register" sif (cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any edge" elif (cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z128CLH5*")) bitfld.byte 0x00 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any edge" else bitfld.byte 0x00 6.--7. " WUPE15 ,Wakeup pin enable for LLWU_P15" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE14 ,Wakeup pin enable for LLWU_P14" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE13 ,Wakeup pin enable for LLWU_P13" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x00 0.--1. " WUPE12 ,Wakeup pin enable for LLWU_P12" "Disabled,Rising edge,Falling edge,Any edge" endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x04++0x01 line.byte 0x00 "LLWU_PE5,LLWU Pin Enable 5 Register" sif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled,Rising edge,Falling edge,Any edge" else bitfld.byte 0x00 6.--7. " WUPE19 ,Wakeup pin enable for LLWU_P19" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 4.--5. " WUPE18 ,Wakeup pin enable for LLWU_P18" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x00 2.--3. " WUPE17 ,Wakeup pin enable for LLWU_P17" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x00 0.--1. " WUPE16 ,Wakeup pin enable for LLWU_P16" "Disabled,Rising edge,Falling edge,Any edge" endif line.byte 0x01 "LLWU_PE6,LLWU Pin Enable 6 Register" sif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x01 4.--5. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 2.--3. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 0.--1. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled,Rising edge,Falling edge,Any edge" else bitfld.byte 0x01 6.--7. " WUPE23 ,Wakeup pin enable for LLWU_P23" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 4.--5. " WUPE22 ,Wakeup pin enable for LLWU_P22" "Disabled,Rising edge,Falling edge,Any edge" bitfld.byte 0x01 2.--3. " WUPE21 ,Wakeup pin enable for LLWU_P21" "Disabled,Rising edge,Falling edge,Any edge" textline " " bitfld.byte 0x01 0.--1. " WUPE20 ,Wakeup pin enable for LLWU_P20" "Disabled,Rising edge,Falling edge,Any edge" endif group.byte 0x08++0x00 line.byte 0x00 "LLWU_ME,LLWU Module Enable Register" bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Not used,Used" bitfld.byte 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Not used,Used" bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Not used,Used" textline " " bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Not used,Used" bitfld.byte 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Not used,Used" bitfld.byte 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Not used,Used" textline " " bitfld.byte 0x00 1. " WUME1 ,Wakeup module enable for module 1" "Not used,Used" bitfld.byte 0x00 0. " WUME0 ,Wakeup module enable for module 0" "Not used,Used" else group.byte 0x04++0x00 line.byte 0x00 "LLWU_ME,LLWU Module Enable Register" bitfld.byte 0x00 7. " WUME7 ,Wakeup module enable for module 7" "Not used,Used" bitfld.byte 0x00 6. " WUME6 ,Wakeup module enable for module 6" "Not used,Used" bitfld.byte 0x00 5. " WUME5 ,Wakeup module enable for module 5" "Not used,Used" textline " " bitfld.byte 0x00 4. " WUME4 ,Wakeup module enable for module 4" "Not used,Used" bitfld.byte 0x00 3. " WUME3 ,Wakeup module enable for module 3" "Not used,Used" bitfld.byte 0x00 2. " WUME2 ,Wakeup module enable for module 2" "Not used,Used" textline " " bitfld.byte 0x00 1. " WUME1 ,Wakeup module enable for module 1" "Not used,Used" bitfld.byte 0x00 0. " WUME0 ,Wakeup module enable for module 0" "Not used,Used" endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x09++0x02 line.byte 0x00 "LLWU_PF1,LLWU Flag 1 Register" eventfld.byte 0x00 7. " WUF7 ,Wakeup flag for LLWU_P7" "Not detected,Detected" eventfld.byte 0x00 6. " WUF6 ,Wakeup flag for LLWU_P6" "Not detected,Detected" eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Not detected,Detected" textline " " eventfld.byte 0x00 4. " WUF4 ,Wakeup flag for LLWU_P4" "Not detected,Detected" eventfld.byte 0x00 3. " WUF3 ,Wakeup flag for LLWU_P3" "Not detected,Detected" eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Not detected,Detected" textline " " eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Not detected,Detected" eventfld.byte 0x00 0. " WUF0 ,Wakeup flag for LLWU_P0" "Not detected,Detected" line.byte 0x01 "LLWU_PF2,LLWU Flag 2 Register" eventfld.byte 0x01 7. " WUF15 ,Wakeup flag for LLWU_P15" "Not detected,Detected" eventfld.byte 0x01 6. " WUF14 ,Wakeup flag for LLWU_P14" "Not detected,Detected" eventfld.byte 0x01 5. " WUF13 ,Wakeup flag for LLWU_P13" "Not detected,Detected" textline " " eventfld.byte 0x01 4. " WUF12 ,Wakeup flag for LLWU_P12" "Not detected,Detected" eventfld.byte 0x01 3. " WUF11 ,Wakeup flag for LLWU_P11" "Not detected,Detected" eventfld.byte 0x01 2. " WUF10 ,Wakeup flag for LLWU_P10" "Not detected,Detected" textline " " eventfld.byte 0x01 1. " WUF9 ,Wakeup flag for LLWU_P9" "Not detected,Detected" eventfld.byte 0x01 0. " WUF8 ,Wakeup flag for LLWU_P8" "Not detected,Detected" line.byte 0x02 "LLWU_PF3,LLWU Flag 3 register" sif (cpuis("MKM34Z256VLQ7")) eventfld.byte 0x02 7. " WUF23 ,Wakeup flag for LLWU_P23" "Not detected,Detected" textline " " endif eventfld.byte 0x02 6. " WUF22 ,Wakeup flag for LLWU_P22" "Not detected,Detected" eventfld.byte 0x02 5. " WUF21 ,Wakeup flag for LLWU_P21" "Not detected,Detected" eventfld.byte 0x02 4. " WUF20 ,Wakeup flag for LLWU_P20" "Not detected,Detected" textline " " sif (cpuis("MKM34Z256VLQ7")) eventfld.byte 0x02 3. " WUF19 ,Wakeup flag for LLWU_P19" "Not detected,Detected" eventfld.byte 0x02 2. " WUF18 ,Wakeup flag for LLWU_P18" "Not detected,Detected" textline " " endif eventfld.byte 0x02 1. " WUF17 ,Wakeup flag for LLWU_P17" "Not detected,Detected" eventfld.byte 0x02 0. " WUF16 ,Wakeup flag for LLWU_P16" "Not detected,Detected" else sif (cpuis("MKM33Z128ACLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) group.byte 0x05++0x01 line.byte 0x00 "LLWU_F1,LLWU Flag 1 Register" eventfld.byte 0x00 7. " WUF7 ,Wakeup flag for LLWU_P7" "Not detected,Detected" eventfld.byte 0x00 6. " WUF6 ,Wakeup flag for LLWU_P6" "Not detected,Detected" eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Not detected,Detected" textline " " eventfld.byte 0x00 4. " WUF4 ,Wakeup flag for LLWU_P4" "Not detected,Detected" eventfld.byte 0x00 3. " WUF3 ,Wakeup flag for LLWU_P3" "Not detected,Detected" eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Not detected,Detected" textline " " eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Not detected,Detected" eventfld.byte 0x00 0. " WUF0 ,Wakeup flag for LLWU_P0" "Not detected,Detected" line.byte 0x01 "LLWU_F2,LLWU Flag 2 register" eventfld.byte 0x01 7. " WUF15 ,Wakeup flag for LLWU_P15" "Not detected,Detected" eventfld.byte 0x01 6. " WUF14 ,Wakeup flag for LLWU_P14" "Not detected,Detected" eventfld.byte 0x01 5. " WUF13 ,Wakeup flag for LLWU_P13" "Not detected,Detected" textline " " eventfld.byte 0x01 4. " WUF12 ,Wakeup flag for LLWU_P12" "Not detected,Detected" eventfld.byte 0x01 3. " WUF11 ,Wakeup flag for LLWU_P11" "Not detected,Detected" eventfld.byte 0x01 2. " WUF10 ,Wakeup flag for LLWU_P10" "Not detected,Detected" textline " " eventfld.byte 0x01 1. " WUF9 ,Wakeup flag for LLWU_P9" "Not detected,Detected" eventfld.byte 0x01 0. " WUF8 ,Wakeup flag for LLWU_P8" "Not detected,Detected" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128CLH5*")) group.byte 0x05++0x01 line.byte 0x00 "LLWU_F1,LLWU Flag 1 Register" eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Not detected,Detected" eventfld.byte 0x00 4. " WUF4 ,Wakeup flag for LLWU_P4" "Not detected,Detected" eventfld.byte 0x00 3. " WUF3 ,Wakeup flag for LLWU_P3" "Not detected,Detected" textline " " eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Not detected,Detected" eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Not detected,Detected" eventfld.byte 0x00 0. " WUF0 ,Wakeup flag for LLWU_P0" "Not detected,Detected" line.byte 0x01 "LLWU_F2,LLWU Flag 2 register" eventfld.byte 0x01 7. " WUF15 ,Wakeup flag for LLWU_P15" "Not detected,Detected" eventfld.byte 0x01 6. " WUF14 ,Wakeup flag for LLWU_P14" "Not detected,Detected" eventfld.byte 0x01 5. " WUF13 ,Wakeup flag for LLWU_P13" "Not detected,Detected" textline " " eventfld.byte 0x01 2. " WUF10 ,Wakeup flag for LLWU_P10" "Not detected,Detected" eventfld.byte 0x01 1. " WUF9 ,Wakeup flag for LLWU_P9" "Not detected,Detected" elif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) group.byte 0x05++0x01 line.byte 0x00 "LLWU_F1,LLWU Flag 1 Register" eventfld.byte 0x00 5. " WUF5 ,Wakeup flag for LLWU_P5" "Not detected,Detected" eventfld.byte 0x00 2. " WUF2 ,Wakeup flag for LLWU_P2" "Not detected,Detected" eventfld.byte 0x00 1. " WUF1 ,Wakeup flag for LLWU_P1" "Not detected,Detected" line.byte 0x01 "LLWU_F2,LLWU Flag 2 register" eventfld.byte 0x01 7. " WUF15 ,Wakeup flag for LLWU_P15" "Not detected,Detected" eventfld.byte 0x01 6. " WUF14 ,Wakeup flag for LLWU_P14" "Not detected,Detected" endif endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rgroup.byte 0x0D++0x00 line.byte 0x00 "LLWU_MF5,LLWU Module Flag 5 Register" bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not detected,Detected" bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not detected,Detected" bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not detected,Detected" bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not detected,Detected" bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not detected,Detected" bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not detected,Detected" else rgroup.byte 0x07++0x00 line.byte 0x00 "LLWU_F3,LLWU Flag 3 Register" bitfld.byte 0x00 7. " MWUF7 ,Wakeup flag for module 7" "Not detected,Detected" bitfld.byte 0x00 6. " MWUF6 ,Wakeup flag for module 6" "Not detected,Detected" bitfld.byte 0x00 5. " MWUF5 ,Wakeup flag for module 5" "Not detected,Detected" textline " " bitfld.byte 0x00 4. " MWUF4 ,Wakeup flag for module 4" "Not detected,Detected" bitfld.byte 0x00 3. " MWUF3 ,Wakeup flag for module 3" "Not detected,Detected" bitfld.byte 0x00 2. " MWUF2 ,Wakeup flag for module 2" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " MWUF1 ,Wakeup flag for module 1" "Not detected,Detected" bitfld.byte 0x00 0. " MWUF0 ,Wakeup flag for module 0" "Not detected,Detected" endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x0E++0x01 line.byte 0x00 "LLWU_FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "Not detected,Detected" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" sif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,,,P20,P21,P22,?..." elif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 0.--4. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,P18,P19,P20,P21,P22,P23,?..." endif line.byte 0x01 "LLWU_FILT2,LLWU Pin Filter 2 register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "Not detected,Detected" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" sif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,,,P20,P21,P22,?..." elif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x01 0.--4. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,P18,P19,P20,P21,P22,P23,?..." endif else group.byte 0x08++0x01 line.byte 0x00 "LLWU_FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "Not detected,Detected" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM33Z64ACLL5*")) bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")) bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,,,,P9,P10,,,P13,P14,P15" elif (cpuis("MKM14Z128CHH5*")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")) bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",P1,P2,,,P5,,,,,,,,,P14,P15" endif line.byte 0x01 "LLWU_FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "Not detected,Detected" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Posedge,Negedge,Any edge" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM33Z64ACLL5*")) bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15" elif (cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLH5")||cpuis("MKM33Z128ACLH5*")) bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "P0,P1,P2,P3,P4,P5,,,,P9,P10,,,P13,P14,P15" elif (cpuis("MKM14Z128CHH5*")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128ACHH5*")) bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",P1,P2,,,P5,,,,,,,,,P14,P15" endif endif width 0x0B tree.end tree "DMAC (Direct Memory Access Controller Module)" tree "CHANNEL 0" base ad:0x40008100 width 14. group.long 0x00++0x0B line.long 0x00 "DMA_SAR0,Source Address Register 0" line.long 0x04 "DMA_DAR0,Destination Address Register 0" line.long 0x08 "DMA_DSR_BCR0,DMA Status Register / Byte Count Register 0" rbitfld.long 0x08 30. " CE ,Configuration error" "No Error,Error" rbitfld.long 0x08 29. " BES ,Bus error on source" "No Error,Error" rbitfld.long 0x08 28. " BED ,Bus error on destination" "No Error,Error" textline " " rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested" rbitfld.long 0x08 25. " BSY ,Busy" "Inactive,Busy" eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed" textline " " hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter" if (((per.l(ad:0x40008100+0x0C))&0x03000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR0,DMA Control Register 0" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,Read/Write,Read/Write" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" elif (((per.l(ad:0x40008100+0x0C))&0x03000000)==0x02000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR0,DMA Control Register 0" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" else group.long 0x0C++0x03 line.long 0x00 "DMA_DCR0,DMA Control Register 0" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,None,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" endif width 0x0B tree.end tree "CHANNEL 1" base ad:0x40008110 width 14. group.long 0x00++0x0B line.long 0x00 "DMA_SAR1,Source Address Register 1" line.long 0x04 "DMA_DAR1,Destination Address Register 1" line.long 0x08 "DMA_DSR_BCR1,DMA Status Register / Byte Count Register 1" rbitfld.long 0x08 30. " CE ,Configuration error" "No Error,Error" rbitfld.long 0x08 29. " BES ,Bus error on source" "No Error,Error" rbitfld.long 0x08 28. " BED ,Bus error on destination" "No Error,Error" textline " " rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested" rbitfld.long 0x08 25. " BSY ,Busy" "Inactive,Busy" eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed" textline " " hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter" if (((per.l(ad:0x40008110+0x0C))&0x03000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR1,DMA Control Register 1" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,Read/Write,Read/Write" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" elif (((per.l(ad:0x40008110+0x0C))&0x03000000)==0x02000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR1,DMA Control Register 1" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" else group.long 0x0C++0x03 line.long 0x00 "DMA_DCR1,DMA Control Register 1" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,None,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" endif width 0x0B tree.end tree "CHANNEL 2" base ad:0x40008120 width 14. group.long 0x00++0x0B line.long 0x00 "DMA_SAR2,Source Address Register 2" line.long 0x04 "DMA_DAR2,Destination Address Register 2" line.long 0x08 "DMA_DSR_BCR2,DMA Status Register / Byte Count Register 2" rbitfld.long 0x08 30. " CE ,Configuration error" "No Error,Error" rbitfld.long 0x08 29. " BES ,Bus error on source" "No Error,Error" rbitfld.long 0x08 28. " BED ,Bus error on destination" "No Error,Error" textline " " rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested" rbitfld.long 0x08 25. " BSY ,Busy" "Inactive,Busy" eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed" textline " " hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter" if (((per.l(ad:0x40008120+0x0C))&0x03000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR2,DMA Control Register 2" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,Read/Write,Read/Write" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" elif (((per.l(ad:0x40008120+0x0C))&0x03000000)==0x02000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR2,DMA Control Register 2" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" else group.long 0x0C++0x03 line.long 0x00 "DMA_DCR2,DMA Control Register 2" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,None,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" endif width 0x0B tree.end tree "CHANNEL 3" base ad:0x40008130 width 14. group.long 0x00++0x0B line.long 0x00 "DMA_SAR3,Source Address Register 3" line.long 0x04 "DMA_DAR3,Destination Address Register 3" line.long 0x08 "DMA_DSR_BCR3,DMA Status Register / Byte Count Register 3" rbitfld.long 0x08 30. " CE ,Configuration error" "No Error,Error" rbitfld.long 0x08 29. " BES ,Bus error on source" "No Error,Error" rbitfld.long 0x08 28. " BED ,Bus error on destination" "No Error,Error" textline " " rbitfld.long 0x08 26. " REQ ,Request" "Not requested,Requested" rbitfld.long 0x08 25. " BSY ,Busy" "Inactive,Busy" eventfld.long 0x08 24. " DONE ,Transactions done" "Not completed,Completed" textline " " hexmask.long.tbyte 0x08 0.--23. 1. " BCR ,Bytes yet to be transferred counter" if (((per.l(ad:0x40008130+0x0C))&0x03000000)==0x00000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR3,DMA Control Register 3" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,Read/Write,Read/Write" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" elif (((per.l(ad:0x40008130+0x0C))&0x03000000)==0x02000000) group.long 0x0C++0x03 line.long 0x00 "DMA_DCR3,DMA Control Register 3" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,Read/Write,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" else group.long 0x0C++0x03 line.long 0x00 "DMA_DCR3,DMA Control Register 3" bitfld.long 0x00 31. " EINT ,Enable interrupt on completion of transfer" "Disabled,Enabled" bitfld.long 0x00 30. " ERQ ,Enable peripheral request" "Disabled,Enabled" bitfld.long 0x00 29. " CS ,Cycle steal" "Continuous,Single" textline " " bitfld.long 0x00 28. " AA ,Auto-align" "Disabled,Enabled" bitfld.long 0x00 26.--27. " CHACR ,Channel Access Control" "Read/Write,None,None,None" bitfld.long 0x00 24.--25. " UMNSM ,User Mode/Nonsecure Mode" "Current mode,Privileged-Secure/Error/Error,User-Secure/User-Secure/Error,User-Nonsecure/User-Nonsecure/User-Nonsecure" textline " " bitfld.long 0x00 23. " EADREQ ,Enable asynchronous DMA requests" "Disabled,Enabled" bitfld.long 0x00 22. " SINC ,Source increment" "Not Changed,Incremented" bitfld.long 0x00 20.--21. " SSIZE ,Source size" "32-bit,8-bit,16-bit,?..." textline " " bitfld.long 0x00 19. " DINC ,Destination increment" "Not Changed,Incremented" bitfld.long 0x00 17.--18. " DSIZE ,Destination size" "32-bit,8-bit,16-bit,?..." bitfld.long 0x00 16. " START ,Start transfer" "Inactive,Active" textline " " bitfld.long 0x00 12.--15. " SMOD ,Source address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 8.--11. " DMOD ,Destination address modulo" "Disabled,16bytes,32bytes,64bytes,128bytes,256bytes,512bytes,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB" bitfld.long 0x00 7. " D_REQ ,Disable request" "Not affected,Cleared" textline " " bitfld.long 0x00 4.--5. " LINKCC ,Link channel control" "No linking,LCH1-CycyleSteal;LCH2-BCR=0,LCH1-CycleSteal,LCH1-BCR=0" bitfld.long 0x00 2.--3. " LCH1 ,Link channel 1" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" bitfld.long 0x00 0.--1. " LCH2 ,Link channel 2" "DMA Channel 0,DMA Channel 1,DMA Channel 2,DMA Channel 3" endif width 0x0B tree.end tree.end tree "DMAMUX (Direct Memory Access Multiplexer)" base ad:0x40021000 width 15. sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") group.byte 0x00++0x00 line.byte 0x00 "DMAMUX0_CHCFG,Channel Configuration Register 0" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI0_Tx,SPI0_Rx,UART0_Tx,UART0_Rx,I2C0,XBAR,UART3_Tx,UART3_Rx,AFE_CH0,TMR_0,TMR_3,AFE_CH2,ADC,CMP0,PTE,PTA,Always Enabled,Always Enabled,?..." group.byte 0x1000++0x00 line.byte 0x00 "DMAMUX1_CHCFG,Channel Configuration Register 1" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI0_Tx,SPI0_Rx,UART1_Tx,UART1_Rx,I2C0,XBAR,UART3_Tx,UART3_Rx,AFE_CH0,TMR_0,TMR_3,AFE_CH2,PTE,CMP0,PTF,,Always Enabled,Always Enabled,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI0_Tx,SPI0_Rx,UART1_Tx,UART1_Rx,I2C0,XBAR,UART3_Tx,UART3_Rx,AFE_CH0,TMR_0,TMR_3,AFE_CH2,PTE,CMP0,PTF,PTB,Always Enabled,Always Enabled,?..." endif group.byte 0x2000++0x00 line.byte 0x00 "DMAMUX2_CHCFG,Channel Configuration Register 2" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(Slot)" "Disabled,SPI1_Tx,SPI1_Rx,UART1_Tx,UART1_Rx,I2C1,XBAR,UART2_Tx,UART2_Rx,AFE_CH1,TMR_2,TMR_1,AFE_CH3,PTI,CMP1,PTG,,Always Enabled,Always Enabled,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(Slot)" "Disabled,SPI1_Tx,SPI1_Rx,UART1_Tx,UART1_Rx,I2C1,XBAR,UART2_Tx,UART2_Rx,AFE_CH1,TMR_2,TMR_1,AFE_CH3,PTI,CMP1,PTG,PTC,Always Enabled,Always Enabled,?..." endif group.byte 0x3000++0x00 line.byte 0x00 "DMAMUX3_CHCFG,Channel Configuration Register 3" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI1_Tx,SPI1_Rx,UART0_Tx,UART0_Rx,I2C1,XBAR,UART2_Tx,UART2_Rx,AFE_CH1,TMR_2,TMR_1,AFE_CH3,ADC,CMP1,PTH,,Always Enabled,Always Enabled,?..." elif cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128CLH5*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI1_Tx,SPI1_Rx,UART0_Tx,UART0_Rx,I2C1,XBAR,UART2_Tx,UART2_Rx,AFE_CH1,TMR_2,TMR_1,AFE_CH3,ADC,CMP1,,PTD,Always Enabled,Always Enabled,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,SPI1_Tx,SPI1_Rx,UART0_Tx,UART0_Rx,I2C1,XBAR,UART2_Tx,UART2_Rx,AFE_CH1,TMR_2,TMR_1,AFE_CH3,ADC,CMP1,PTH,PTD,Always Enabled,Always Enabled,?..." endif else group.byte 0x00++0x00 line.byte 0x00 "DMAMUX0_CHCFG,Channel Configuration Register 0" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM34Z256VLQ7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,PORTJ,PORTK,PORTL,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,,,,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" endif group.byte 0x1000++0x00 line.byte 0x00 "DMAMUX1_CHCFG,Channel Configuration Register 1" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM34Z256VLQ7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,PORTJ,PORTK,PORTL,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,,,,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" endif group.byte 0x2000++0x00 line.byte 0x00 "DMAMUX2_CHCFG,Channel Configuration Register 2" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM34Z256VLQ7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,PORTJ,PORTK,PORTL,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,,,,,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" endif group.byte 0x3000++0x00 line.byte 0x00 "DMAMUX3_CHCFG,Channel Configuration Register 3" bitfld.byte 0x00 7. " ENBL ,DMA channel" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA channel trigger" "Disabled,Enabled" sif cpuis("MKM34Z256VLQ7") bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,PORTJ,PORTK,PORTL,PORTM,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source(slot)" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,,,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,QTMR_CH0,QTMR_CH1,QTMR_CH2,QTMR_CH3,XBAR_DMA0,XBAR_DMA1,XBAR_DMA2,XBAR_DMA3,AFE_CH0,AFE_CH1,AFE_CH2,AFE_CH3,,,,,SAR_ADC,,CMP0,CMP1,CMP2,,,MMAU,PDB,PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTG,PORTH,PORTI,LPUART0_Rx,LPUART0_Tx,Always enabled,Always enabled,Always enabled,Always enabled" endif endif width 0x0B tree.end tree "AIPS-Lite (Peripheral Bridge)" base ad:0x40000020 width 14. group.long 0x00++0x07 line.long 0x00 "AIPS_PACRA,Peripheral Access Control Register A" bitfld.long 0x00 31. " RO0 ,AC0 Lock Status" "Unlocked,Locked" bitfld.long 0x00 28.--30. " AC0 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x04 "AIPS_PACRB,Peripheral Access Control Register B" bitfld.long 0x04 31. " RO8 ,AC8 Lock Status" "Unlocked,Locked" bitfld.long 0x04 28.--30. " AC8 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x04 23. " RO10 ,AC10 Lock Status" "Unlocked,Locked" bitfld.long 0x04 20.--22. " AC10 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x04 3. " RO15 ,AC15 Lock Status" "Unlocked,Locked" bitfld.long 0x04 0.--2. " AC15 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" group.long 0x20++0x2F line.long 0x00 "AIPS_PACRE,Peripheral Access Control Register E" bitfld.long 0x00 31. " RO32 ,AC32 Lock Status" "Unlocked,Locked" bitfld.long 0x00 28.--30. " AC32 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x00 27. " RO33 ,AC33 Lock Status" "Unlocked,Locked" bitfld.long 0x00 24.--26. " AC33 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 23. " RO34 ,AC34 Lock Status" "Unlocked,Locked" bitfld.long 0x00 20.--22. " AC34 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x00 19. " RO35 ,AC35 Lock Status" "Unlocked,Locked" bitfld.long 0x00 16.--18. " AC35 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x00 15. " RO36 ,AC36 Lock Status" "Unlocked,Locked" bitfld.long 0x00 12.--14. " AC36 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" endif line.long 0x04 "AIPS_PACRF,Peripheral Access Control Register F" bitfld.long 0x04 27. " RO41 ,AC41 Lock Status" "Unlocked,Locked" bitfld.long 0x04 24.--26. " AC41 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x04 23. " RO42 ,AC42 Lock Status" "Unlocked,Locked" bitfld.long 0x04 20.--22. " AC42 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " endif bitfld.long 0x04 19. " RO43 ,AC43 Lock Status" "Unlocked,Locked" bitfld.long 0x04 16.--18. " AC43 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x04 11. " RO45 ,AC45 Lock Status" "Unlocked,Locked" bitfld.long 0x04 8.--10. " AC45 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x04 7. " RO46 ,AC46 Lock Status" "Unlocked,Locked" bitfld.long 0x04 4.--6. " AC46 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x08 "AIPS_PACRG,Peripheral Access Control Register G" bitfld.long 0x08 31. " RO48 ,AC48 Lock Status" "Unlocked,Locked" bitfld.long 0x08 28.--30. " AC48 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x08 15. " RO52 ,AC52 Lock Status" "Unlocked,Locked" bitfld.long 0x08 12.--14. " AC52 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x08 7. " RO54 ,AC54 Lock Status" "Unlocked,Locked" bitfld.long 0x08 4.--6. " AC54 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif !cpuis("MKM34Z256VLL7*") bitfld.long 0x08 3. " RO55 ,AC55 Lock Status" "Unlocked,Locked" bitfld.long 0x08 0.--2. " AC55 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" endif endif line.long 0x0C "AIPS_PACRH,Peripheral Access Control Register H" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") sif !cpuis("MKM34Z256VLL7*") bitfld.long 0x0C 31. " RO56 ,AC56 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 28.--30. " AC56 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x0C 27. " RO57 ,AC57 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 24.--26. " AC57 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " endif bitfld.long 0x0C 23. " RO58 ,AC58 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 20.--22. " AC58 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " endif bitfld.long 0x0C 15. " RO60 ,AC60 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 12.--14. " AC60 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x0C 7. " RO62 ,AC62 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 4.--6. " AC62 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x0C 3. " RO63 ,AC63 Lock Status" "Unlocked,Locked" bitfld.long 0x0C 0.--2. " AC63 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x10 "AIPS_PACRI,Peripheral Access Control Register I" bitfld.long 0x10 19. " RO67 ,AC67 Lock Status" "Unlocked,Locked" bitfld.long 0x10 16.--18. " AC67 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x10 7. " RO70 ,AC70 Lock Status" "Unlocked,Locked" bitfld.long 0x10 4.--6. " AC70 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM14Z128CHH5*") bitfld.long 0x10 3. " RO71 ,AC71 Lock Status" "Unlocked,Locked" bitfld.long 0x10 0.--2. " AC71 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" endif line.long 0x14 "AIPS_PACRJ,Peripheral Access Control Register J" sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM14Z128CHH5*") bitfld.long 0x14 31. " RO72 ,AC72 Lock Status" "Unlocked,Locked" bitfld.long 0x14 28.--30. " AC72 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x14 27. " RO73 ,AC73 Lock Status" "Unlocked,Locked" bitfld.long 0x14 24.--26. " AC73 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " endif bitfld.long 0x14 23. " RO74 ,AC74 Lock Status" "Unlocked,Locked" bitfld.long 0x14 20.--22. " AC74 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x14 19. " RO75 ,AC75 Lock Status" "Unlocked,Locked" bitfld.long 0x14 16.--18. " AC75 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x14 15. " RO76 ,AC76 Lock Status" "Unlocked,Locked" bitfld.long 0x14 12.--14. " AC76 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " sif !cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5") bitfld.long 0x14 11. " RO77 ,AC77 Lock Status" "Unlocked,Locked" bitfld.long 0x14 8.--10. " AC77 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " endif bitfld.long 0x14 7. " RO78 ,AC78 Lock Status" "Unlocked,Locked" bitfld.long 0x14 4.--6. " AC78 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x18 "AIPS_PACRK,Peripheral Access Control Register K" bitfld.long 0x18 31. " RO80 ,AC80 Lock Status" "Unlocked,Locked" bitfld.long 0x18 28.--30. " AC80 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x18 27. " RO81 ,AC81 Lock Status" "Unlocked,Locked" bitfld.long 0x18 24.--26. " AC81 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x18 19. " RO83 ,AC83 Lock Status" "Unlocked,Locked" bitfld.long 0x18 16.--18. " AC83 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x18 11. " RO85 ,AC85 Lock Status" "Unlocked,Locked" bitfld.long 0x18 8.--10. " AC85 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x18 3. " RO87 ,AC87 Lock Status" "Unlocked,Locked" bitfld.long 0x18 0.--2. " AC87 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x1C "AIPS_PACRL,Peripheral Access Control Register L" bitfld.long 0x1C 31. " RO88 ,AC88 Lock Status" "Unlocked,Locked" bitfld.long 0x1C 28.--30. " AC88 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x1C 27. " RO89 ,AC89 Lock Status" "Unlocked,Locked" bitfld.long 0x1C 24.--26. " AC89 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x1C 23. " RO90 ,AC90 Lock Status" "Unlocked,Locked" bitfld.long 0x1C 20.--22. " AC90 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x20 "AIPS_PACRM,Peripheral Access Control Register M" bitfld.long 0x20 27. " RO97 ,AC97 Lock Status" "Unlocked,Locked" bitfld.long 0x20 24.--26. " AC97 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x20 15. " RO100 ,AC100 Lock Status" "Unlocked,Locked" bitfld.long 0x20 12.--14. " AC100 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x20 7. " RO102 ,AC102 Lock Status" "Unlocked,Locked" bitfld.long 0x20 4.--6. " AC102 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x20 3. " RO103 ,AC103 Lock Status" "Unlocked,Locked" bitfld.long 0x20 0.--2. " AC103 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x24 "AIPS_PACRN,Peripheral Access Control Register N" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5") bitfld.long 0x24 31. " RO104 ,AC104 Lock Status" "Unlocked,Locked" bitfld.long 0x24 28.--30. " AC104 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x24 23. " RO106 ,AC106 Lock Status" "Unlocked,Locked" bitfld.long 0x24 20.--22. " AC106 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x24 19. " RO107 ,AC107 Lock Status" "Unlocked,Locked" bitfld.long 0x24 16.--18. " AC107 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x24 15. " RO108 ,AC108 Lock Status" "Unlocked,Locked" bitfld.long 0x24 12.--14. " AC108 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x24 11. " RO109 ,AC109 Lock Status" "Unlocked,Locked" bitfld.long 0x24 8.--10. " AC109 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x24 3. " RO111 ,AC111 Lock Status" "Unlocked,Locked" bitfld.long 0x24 0.--2. " AC111 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " elif (cpuis("MKM14Z64CHH5")) bitfld.long 0x24 31. " RO104 ,AC104 Lock Status" "Unlocked,Locked" bitfld.long 0x24 28.--30. " AC104 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x24 23. " RO106 ,AC106 Lock Status" "Unlocked,Locked" bitfld.long 0x24 20.--22. " AC106 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x24 19. " RO107 ,AC107 Lock Status" "Unlocked,Locked" bitfld.long 0x24 16.--18. " AC107 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x24 3. " RO111 ,AC111 Lock Status" "Unlocked,Locked" bitfld.long 0x24 0.--2. " AC111 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" endif line.long 0x28 "AIPS_PACRO,Peripheral Access Control Register O" bitfld.long 0x28 23. " RO114 ,AC114 Lock Status" "Unlocked,Locked" bitfld.long 0x28 20.--22. " AC114 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x28 11. " RO117 ,AC117 Lock Status" "Unlocked,Locked" bitfld.long 0x28 8.--10. " AC117 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x28 7. " RO118 ,AC118 Lock Status" "Unlocked,Locked" bitfld.long 0x28 4.--6. " AC118 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" line.long 0x2C "AIPS_PACRP,Peripheral Access Control Register P" bitfld.long 0x2C 19. " RO123 ,AC123 Lock Status" "Unlocked,Locked" bitfld.long 0x2C 16.--18. " AC123 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x2C 15. " RO124 ,AC124 Lock Status" "Unlocked,Locked" bitfld.long 0x2C 12.--14. " AC124 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" textline " " bitfld.long 0x2C 11. " RO125 ,AC125 Lock Status" "Unlocked,Locked" bitfld.long 0x2C 8.--10. " AC125 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" bitfld.long 0x2C 7. " RO126 ,AC126 Lock Status" "Unlocked,Locked" bitfld.long 0x2C 4.--6. " AC126 ,Attribute check (P-S/U-S/U-NS)" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "MPU (Memory Protection Unit)" base ad:0x4000A000 width 16. group.long 0x00++0x03 line.long 0x00 "CESR,Control/Error Status Register" eventfld.long 0x00 31. " SPERR ,Slave port 0 error" "No error,Error" eventfld.long 0x00 30. " SPERR ,Slave port 1 error" "No error,Error" newline sif cpuis("MKL82Z*") eventfld.long 0x00 29. " SPERR ,Slave port 2 error" "No error,Error" eventfld.long 0x00 28. " SPERR ,Slave port 3 error" "No error,Error" newline endif rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8 regions,12 regions,16 regions,?..." bitfld.long 0x00 0. " VLD ,Valid" "Disabled,Enabled" rgroup.long 0x10++0x0F line.long 0x00 "EAR0,Error Address Register 0, Slave Port 0" line.long 0x04 "EDR0,Error Detail Register 0, Slave Port 0" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKL82Z*") bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 4.--7. " EMN ,Error master number" ",Bus 0,Bus 2,,Bus 3,,,,Bus 4,?..." endif newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" line.long 0x08 "EAR1,Error Address Register 1, Slave Port 1" line.long 0x0C "EDR1,Error Detail Register 1, Slave Port 1" hexmask.long.word 0x0C 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x0C 8.--15. 1. " EPID ,Error process identification" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKL82Z*") bitfld.long 0x0C 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x0C 4.--7. " EMN ,Error master number" ",Bus 0,Bus 2,,Bus 3,,,,Bus 4,?..." endif newline bitfld.long 0x0C 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..." bitfld.long 0x0C 0. " ERW ,Error read/write" "Read,Write" sif cpuis("MKL82Z*") rgroup.long 0x20++0x17 line.long 0x00 "EAR2,Error Address Register 2, Slave Port 2" line.long 0x04 "EDR2,Error Detail Register 2, Slave Port 2" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..." bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" line.long 0x08 "EAR3,Error Address Register 3, Slave Port 3" line.long 0x0C "EDR3,Error Detail Register 3, Slave Port 3" hexmask.long.word 0x0C 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x0C 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x0C 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..." bitfld.long 0x0C 0. " ERW ,Error read/write" "Read,Write" line.long 0x10 "EAR4,Error Address Register 4, Slave Port 4" line.long 0x14 "EDR4,Error Detail Register 4, Slave Port 4" hexmask.long.word 0x14 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x14 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x14 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 1.--3. " EATTR ,Error attributes" "User-instruction,User-data,Supervisor-instruction,Supervisor-data,?..." bitfld.long 0x14 0. " ERW ,Error read/write" "Read,Write" endif group.long (0x400+0x0)++0x07 line.long 0x00 "RGD0_WORD0,Region Descriptor 0, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD0_WORD1,Region Descriptor 0, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x0)++0x07 line.long 0x00 "RGD0_WORD2,Region Descriptor 0, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD0_WORD3,Region Descriptor 0, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x10)++0x07 line.long 0x00 "RGD1_WORD0,Region Descriptor 1, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD1_WORD1,Region Descriptor 1, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x10)++0x07 line.long 0x00 "RGD1_WORD2,Region Descriptor 1, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD1_WORD3,Region Descriptor 1, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x20)++0x07 line.long 0x00 "RGD2_WORD0,Region Descriptor 2, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD2_WORD1,Region Descriptor 2, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x20)++0x07 line.long 0x00 "RGD2_WORD2,Region Descriptor 2, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD2_WORD3,Region Descriptor 2, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x30)++0x07 line.long 0x00 "RGD3_WORD0,Region Descriptor 3, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD3_WORD1,Region Descriptor 3, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x30)++0x07 line.long 0x00 "RGD3_WORD2,Region Descriptor 3, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD3_WORD3,Region Descriptor 3, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x40)++0x07 line.long 0x00 "RGD4_WORD0,Region Descriptor 4, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD4_WORD1,Region Descriptor 4, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x40)++0x07 line.long 0x00 "RGD4_WORD2,Region Descriptor 4, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD4_WORD3,Region Descriptor 4, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x50)++0x07 line.long 0x00 "RGD5_WORD0,Region Descriptor 5, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD5_WORD1,Region Descriptor 5, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x50)++0x07 line.long 0x00 "RGD5_WORD2,Region Descriptor 5, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD5_WORD3,Region Descriptor 5, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x60)++0x07 line.long 0x00 "RGD6_WORD0,Region Descriptor 6, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD6_WORD1,Region Descriptor 6, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x60)++0x07 line.long 0x00 "RGD6_WORD2,Region Descriptor 6, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD6_WORD3,Region Descriptor 6, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x400+0x70)++0x07 line.long 0x00 "RGD7_WORD0,Region Descriptor 7, Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD7_WORD1,Region Descriptor 7, Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" group.long (0x408+0x70)++0x07 line.long 0x00 "RGD7_WORD2,Region Descriptor 7, Word 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." line.long 0x04 "RGD7_WORD3,Region Descriptor 7, Word 3" hexmask.long.byte 0x04 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x04 16.--23. 1. " PIDMASK ,Process identifier mask" bitfld.long 0x04 0. " VLD ,Valid" "Invalid,Valid" group.long (0x800+0x0)++0x03 line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x4)++0x03 line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x8)++0x03 line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0xC)++0x03 line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x10)++0x03 line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x14)++0x03 line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x18)++0x03 line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." group.long (0x800+0x1C)++0x03 line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7" bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "r/w/x,r/x,r/w,M3UM" bitfld.long 0x00 18.--20. " M3UM ,Bus master 3 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "r/w/x,r/x,r/w,M2UM" bitfld.long 0x00 12.--14. " M2UM ,Bus master 2 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "r/w/x,r/x,r/w,M1UM" bitfld.long 0x00 6.--8. " M1UM ,Bus master 1 user mode access control" "Not allowed,Allowed,?..." bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "r/w/x,r/x,r/w,M0UM" bitfld.long 0x00 0.--2. " M0UM ,Bus master 0 user mode access control" "Not allowed,Allowed,?..." width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x2 line.byte 0x00 "LVDSC1,Low Voltage Detect Status And Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "No effect,Acknowledge" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip point,High trip point,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status And Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "No effect,Acknowledge" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip point,Mid1 trip point,Mid2 trip point,High trip point" line.byte 0x02 "REGSC,Regulator Status And Control Register" bitfld.byte 0x02 4. " BGEN ,Bandgap enable in VLPx operation" "Disabled,Enabled" eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Run state,Latch state" rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.byte 0x02 1. " BGBDS ,Bandgap buffer drive select" "Low,High" textline " " endif bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40053000 width 14. group.word 0x00++0x17 line.word 0x00 "WDOG_STCTRLH,Watchdog Status and Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,Watchdog Functional Test Mode Disable" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Byte Test Mode Select" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.word 0x00 11. " TESTSEL ,Test Select" "Quick,Byte" textline " " bitfld.word 0x00 10. " TESTWDOG ,Functional Test Mode" "Off,On" bitfld.word 0x00 6. " STOPEN ,Watchdog in Stop Mode" "Disabled,Enabled" bitfld.word 0x00 5. " DBGEN ,Watchdog in Debug Mode" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " ALLOWUPDATE ,Allow Watchdog's Write-Once Register" "Not allowed,Allowed" bitfld.word 0x00 3. " WINEN ,Enables Windowing mode" "Disabled,Enabled" bitfld.word 0x00 2. " IRQRSTEN ,Interrupt and Reset Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CLKSRC ,Watchdog Clock Source" "LPO,Alternate" bitfld.word 0x00 0. " WDOGEN ,Watchdog Operation" "Disabled,Enabled" line.word 0x02 "WDOG_STCTRLL,Watchdog Status and Control Register Low" eventfld.word 0x02 15. " INTFLG ,Interrupt flag" "No interrupt,Interrupt" line.word 0x04 "WDOG_TOVALH,Watchdog Time-out Value Register High" line.word 0x06 "WDOG_TOVALL,Watchdog Time-out Value Register Low" line.word 0x08 "WDOG_WINH,Watchdog Window Register High" line.word 0x0A "WDOG_WINL,Watchdog Window Register Low" line.word 0x0C "WDOG_REFRESH,Watchdog Refresh Register" line.word 0x0E "WDOG_UNLOCK,Watchdog Unlock Register" line.word 0x10 "WDOG_TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "WDOG_TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "WDOG_RSTCNT,Watchdog Reset Count Register" line.word 0x16 "WDOG_PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,Prescaler Value" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 10. group.byte 0x00++0x00 line.byte 0x00 "EWM_CTRL,Control Register" bitfld.byte 0x00 3. " INTEN ,Interrupt Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " INEN ,Input Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,EWM_in's Assertion State Select" "Non-Inverted,Inverted" textline " " bitfld.byte 0x00 0. " EWMEN , EWM Enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "EWM_SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "EWM_CMPL,Compare Low Register" line.byte 0x01 "EWM_CMPH,Compare High Register" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") width 18. group.byte 0x04++0x01 line.byte 0x00 "EWM_CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Clock source select" "Lpo_clk[0],Lpo_clk[1],Lpo_clk[2],Lpo_clk[3]" line.byte 0x01 "EWM_CLKPRESCALER,Clock Prescaler Register" endif width 0x0B tree.end tree "AFE (Analog Front End)" base ad:0x40030000 width 13. group.long 0x00++0x3B line.long 0x00 "AFE_CH0_CFR,Channel 0 Configuration Register" bitfld.long 0x00 29.--31. " DEC_OSR ,Decimator OverSampling Ratio Select" "64,128,256,512,1024,2048,?..." bitfld.long 0x00 24. " PGA_EN ,PGA Enable" "Disabled,Enabled" bitfld.long 0x00 19.--21. " PGA_GAIN_SEL ,PGA Gain Select" ",1x,2x,4x,8x,16x,32x,?..." textline " " bitfld.long 0x00 17. " BYP_MODE ,AFE Channel 0 Bypass Mode" "Normal,Bypass" bitfld.long 0x00 14. " SD_MOD_EN ,Sigma Delta Modulator Enable" "Disabled,Enabled" bitfld.long 0x00 13. " DEC_EN ,Decimation Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " CC ,Continuous Conversion/Single Conversion Mode Select" "Single,Continuous" bitfld.long 0x00 11. " DEC_CLK_EDGE_SEL ,Decimator Clock Edge Select" "Posedge,Negedge" bitfld.long 0x00 10. " DEC_CLK_INP_SEL ,Decimator Clock Input Select" "Internal,External" textline " " bitfld.long 0x00 9. " HW_TRG ,Hardware Trigger Select" "Software,Hardware" line.long 0x04 "AFE_CH1_CFR,Channel 1 Configuration Register" bitfld.long 0x04 29.--31. " DEC_OSR ,Decimator OverSampling Ratio Select" "64,128,256,512,1024,2048,?..." bitfld.long 0x04 24. " PGA_EN ,PGA Enable" "Disabled,Enabled" bitfld.long 0x04 19.--21. " PGA_GAIN_SEL ,PGA Gain Select" ",1x,2x,4x,8x,16x,32x,?..." textline " " bitfld.long 0x04 17. " BYP_MODE ,AFE Channel 1 Bypass Mode" "Normal,Bypass" bitfld.long 0x04 14. " SD_MOD_EN ,Sigma Delta Modulator Enable" "Disabled,Enabled" bitfld.long 0x04 13. " DEC_EN ,Decimation Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " CC ,Continuous Conversion/Single Conversion Mode Select" "Single,Continuous" bitfld.long 0x04 11. " DEC_CLK_EDGE_SEL ,Decimator Clock Edge Select" "Posedge,Negedge" bitfld.long 0x04 10. " DEC_CLK_INP_SEL ,Decimator Clock Input Select" "Internal,External" textline " " bitfld.long 0x04 9. " HW_TRG ,Hardware Trigger Select" "Software,Hardware" line.long 0x08 "AFE_CH2_CFR,Channel 2 Configuration Register" bitfld.long 0x08 29.--31. " DEC_OSR ,Decimator OverSampling Ratio Select" "64,128,256,512,1024,2048,?..." textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x08 24. " PGA_EN ,PGA Enable" "Disabled,Enabled" bitfld.long 0x08 19.--21. " PGA_GAIN_SEL ,PGA Gain Select" ",1x,2x,4x,8x,16x,32x,?..." textline " " endif bitfld.long 0x08 17. " BYP_MODE ,AFE Channel 2 Bypass Mode" "Normal,Bypass" bitfld.long 0x08 14. " SD_MOD_EN ,Sigma Delta Modulator Enable" "Disabled,Enabled" bitfld.long 0x08 13. " DEC_EN ,Decimation Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " CC ,Continuous Conversion/Single Conversion Mode Select" "Single,Continuous" bitfld.long 0x08 11. " DEC_CLK_EDGE_SEL ,Decimator Clock Edge Select" "Posedge,Negedge" bitfld.long 0x08 10. " DEC_CLK_INP_SEL ,Decimator Clock Input Select" "Internal,External" textline " " bitfld.long 0x08 9. " HW_TRG ,Hardware Trigger Select" "Software,Hardware" line.long 0x0C "AFE_CH3_CFR,Channel 3 Configuration Register" bitfld.long 0x0C 29.--31. " DEC_OSR ,Decimator OverSampling Ratio Select" "64,128,256,512,1024,2048,?..." textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.long 0x0C 24. " PGA_EN ,PGA Enable" "Disabled,Enabled" bitfld.long 0x0C 19.--21. " PGA_GAIN_SEL ,PGA Gain Select" ",1x,2x,4x,8x,16x,32x,?..." textline " " endif bitfld.long 0x0C 17. " BYP_MODE ,AFE Channel 3 Bypass Mode" "Normal,Bypass" bitfld.long 0x0C 14. " SD_MOD_EN ,Sigma Delta Modulator Enable" "Disabled,Enabled" bitfld.long 0x0C 13. " DEC_EN ,Decimation Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " CC ,Continuous Conversion/Single Conversion Mode Select" "Single,Continuous" bitfld.long 0x0C 11. " DEC_CLK_EDGE_SEL ,Decimator Clock Edge Select" "Posedge,Negedge" bitfld.long 0x0C 10. " DEC_CLK_INP_SEL ,Decimator Clock Input Select" "Internal,External" textline " " bitfld.long 0x0C 9. " HW_TRG ,Hardware Trigger Select" "Software,Hardware" line.long 0x18 "AFE_CR,Control Register" bitfld.long 0x18 31. " MSTR_EN ,AFE Master Enable" "Disabled,Enabled" bitfld.long 0x18 30. " SOFT_TRG0 ,Software Trigger0" "Disabled,Enabled" bitfld.long 0x18 29. " SOFT_TRG1 ,Software Trigger1" "Disabled,Enabled" textline " " bitfld.long 0x18 28. " SOFT_TRG2 ,Software Trigger2" "Disabled,Enabled" bitfld.long 0x18 27. " SOFT_TRG3 ,Software Trigger3" "Disabled,Enabled" bitfld.long 0x18 25. " LPM_EN ,Low Power Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 22. " RST_B ,Software Reset" "Reset,Not reset" bitfld.long 0x18 21. " DLY_OK ,Delay OK" ",OK" bitfld.long 0x18 18. " RESULT_FORMAT ,Result Format" "Left justified,Right justified" textline " " hexmask.long.byte 0x18 9.--15. 1. " STRTUP_CNT ,Start up count" line.long 0x1C "AFE_CKR,Clock Configuration Register" bitfld.long 0x1C 28.--31. " DIV ,Clock Divider Select" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/256,/256,/256,/256,/256,/256,/256" bitfld.long 0x1C 21.--22. " CLS ,Clock Source Select" "mod_clk0,mod_clk1,mod_clk2,mod_clk3" line.long 0x20 "AFE_DI,DMA and Interrupt Register" bitfld.long 0x20 31. " DMAEN0 ,DMA Enable 0" "Disabled,Enabled" bitfld.long 0x20 30. " DMAEN1 ,DMA Enable 1" "Disabled,Enabled" bitfld.long 0x20 29. " DMAEN2 ,DMA Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x20 28. " DMAEN3 ,DMA Enable 3" "Disabled,Enabled" bitfld.long 0x20 26. " INTEN0 ,Interrupt Enable 0" "Disabled,Enabled" bitfld.long 0x20 25. " INTEN1 ,Interrupt Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x20 24. " INTEN2 ,Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x20 23. " INTEN3 ,Interrupt Enable 3" "Disabled,Enabled" line.long 0x2C "AFE_CH0_DR,Channel 0 Delay Register" hexmask.long.word 0x2C 0.--10. 1. " DLY ,Delay" line.long 0x30 "AFE_CH1_DR,Channel 1 Delay Register" hexmask.long.word 0x30 0.--10. 1. " DLY ,Delay" line.long 0x34 "AFE_CH2_DR,Channel 2 Delay Register" hexmask.long.word 0x34 0.--10. 1. " DLY ,Delay" line.long 0x38 "AFE_CH3_DR,Channel 3 Delay Register" hexmask.long.word 0x38 0.--10. 1. " DLY ,Delay" hgroup.long 0x44++0x03 hide.long 0x00 "AFE_CH0_RR,Channel 0 Result Register" in hgroup.long 0x48++0x03 hide.long 0x00 "AFE_CH1_RR,Channel 1 Result Register" in hgroup.long 0x4C++0x03 hide.long 0x00 "AFE_CH2_RR,Channel 2 Result Register" in hgroup.long 0x50++0x03 hide.long 0x00 "AFE_CH3_RR,Channel 3 Result Register" in textline " " rgroup.long 0x5C++0x03 line.long 0x00 "AFE_SR,Status Register" bitfld.long 0x00 31. " COC0 ,Conversion Complete 0" "Not completed,Completed" bitfld.long 0x00 30. " COC1 ,Conversion Complete 1" "Not completed,Completed" bitfld.long 0x00 29. " COC2 ,Conversion Complete 2" "Not completed,Completed" textline " " bitfld.long 0x00 28. " COC3 ,Conversion Complete 3" "Not completed,Completed" textline " " bitfld.long 0x00 24. " OVR0 ,Overflow Flag 0" "Not overflowed,Overflowed" bitfld.long 0x00 23. " OVR1 ,Overflow Flag 1" "Not overflowed,Overflowed" bitfld.long 0x00 22. " OVR2 ,Overflow Flag 2" "Not overflowed,Overflowed" textline " " bitfld.long 0x00 21. " OVR3 ,Overflow Flag 3" "Not overflowed,Overflowed" textline " " bitfld.long 0x00 19. " RDY0 ,AFE Ready 0" "Not ready,Ready" bitfld.long 0x00 18. " RDY1 ,AFE Ready 1" "Not ready,Ready" bitfld.long 0x00 17. " RDY2 ,AFE Ready 2" "Not ready,Ready" textline " " bitfld.long 0x00 16. " RDY3 ,AFE Ready 3" "Not ready,Ready" width 0x0B tree.end tree "ADC (Analog-to-Digital Converter)" tree "COMMON" base ad:0x4002B010 width 10. group.long 0x10++0x07 line.long 0x00 "ADC_CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low Power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" textline " " bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "8-bit,10-bit,12-bit,16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus,Bus/2,ALTCLK,ADACK" line.long 0x04 "ADC_CFG2,ADC Configuration Register 2" bitfld.long 0x04 4. " MUXSEL ,ADC mux select" "ADxxa,ADxxb" bitfld.long 0x04 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x04 2. " ADHSC ,High-speed configuration" "Disabled,Enabled" textline " " bitfld.long 0x04 0.--1. " ADLSTS ,Long sample time select(extra/total)" "20/24,12/16,6/10,2/6" if ((per.l(ad:0x4002B010+0x10)&0x0C)==0x00) group.long 0x28++0x07 line.long 0x00 "ADC_CV1,Compare Value Registers 1" hexmask.long.byte 0x00 0.--7. 1. " CV0-7 ,8-bit single ended" line.long 0x04 "ADC_CV2,Compare Value Registers 2" hexmask.long.byte 0x04 0.--7. 1. " CV0-7 ,8-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x04) group.long 0x28++0x07 line.long 0x00 "ADC_CV1,Compare Value Registers 1" hexmask.long.word 0x00 0.--9. 1. " CV0-9 ,10-bit single ended" line.long 0x04 "ADC_CV2,Compare Value Registers 2" hexmask.long.word 0x04 0.--9. 1. " CV0-9 ,10-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x08) group.long 0x28++0x07 line.long 0x00 "ADC_CV1,Compare Value Registers 1" hexmask.long.word 0x00 0.--11. 1. " CV0-11 ,12-bit single ended" line.long 0x04 "ADC_CV1,Compare Value Registers 2" hexmask.long.word 0x04 0.--11. 1. " CV0-11 ,12-bit single ended" else group.long 0x28++0x07 line.long 0x00 "ADC_CV1,Compare Value Registers 1" hexmask.long.word 0x00 0.--15. 1. " CV0-15 ,16-bit single ended" line.long 0x04 "ADC_CV2,Compare Value Registers 2" hexmask.long.word 0x04 0.--15. 1. " CV0-15 ,16-bit single ended" endif group.long 0x30++0x3F line.long 0x00 "ADC_SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,Internal,?..." line.long 0x04 "ADC_SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration " "Completed,In progress" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Succeeded,Failed" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4samples,8samples,16samples,32samples" line.long 0x08 "ADC_OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 0x01 " OFS ,Offset error correction value" line.long 0x0C "ADC_PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x14 "ADC_CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "ADC_CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "ADC_CLP4,ADC Plus-Side General Calibration Value Register 4" hexmask.long.word 0x2C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x30 "ADC_CLP3,ADC Plus-Side General Calibration Value Register 3" hexmask.long.word 0x30 0.--8. 1. " CLP3 ,Calibration value" line.long 0x34 "ADC_CLP2,ADC Plus-Side General Calibration Value Register 2" hexmask.long.byte 0x34 0.--7. 1. " CLP2 ,Calibration value" line.long 0x38 "ADC_CLP1,ADC Plus-Side General Calibration Value Register 1" hexmask.long.byte 0x38 0.--6. 1. " CLP1 ,Calibration value" line.long 0x3C "ADC_CLP0,ADC Plus-Side General Calibration Value Register 0" bitfld.long 0x3C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "CHANNEL A" base ad:0x4002B000 width 10. group.long 0x00++0x03 line.long 0x00 "ADC_SC1A,ADC Status and Control Registers 1" rbitfld.long 0x00 7. " COCO , Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z256VLL7*")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,AD3,,,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6,,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" endif if ((per.l(ad:0x4002B010+0x10)&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "ADC_RA,ADC Data Result Register A" hexmask.long.byte 0x00 0.--7. 1. " D0-7 ,8-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "ADC_RA,ADC Data Result Register A" hexmask.long.word 0x00 0.--9. 1. " D0-9 ,10-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "ADC_RA,ADC Data Result Register A" hexmask.long.word 0x00 0.--11. 1. " D0-11 ,12-bit single ended" else group.long 0x18++0x03 line.long 0x00 "ADC_RA,ADC Data Result Register A" hexmask.long.word 0x00 0.--15. 1. " D0-15 ,16-bit single ended" endif width 0x0B tree.end tree "CHANNEL B" base ad:0x4002B004 width 10. group.long 0x00++0x03 line.long 0x00 "ADC_SC1B,ADC Status and Control Registers 1" rbitfld.long 0x00 7. " COCO , Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z256VLL7*")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,AD3,,,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6,,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" endif if ((per.l(ad:0x4002B010+0x10)&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "ADC_RB,ADC Data Result Register B" hexmask.long.byte 0x00 0.--7. 1. " D0-7 ,8-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "ADC_RB,ADC Data Result Register B" hexmask.long.word 0x00 0.--9. 1. " D0-9 ,10-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "ADC_RB,ADC Data Result Register B" hexmask.long.word 0x00 0.--11. 1. " D0-11 ,12-bit single ended" else group.long 0x18++0x03 line.long 0x00 "ADC_RB,ADC Data Result Register B" hexmask.long.word 0x00 0.--15. 1. " D0-15 ,16-bit single ended" endif width 0x0B tree.end tree "CHANNEL C" base ad:0x4002B008 width 10. group.long 0x00++0x03 line.long 0x00 "ADC_SC1C,ADC Status and Control Registers 1" rbitfld.long 0x00 7. " COCO , Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z256VLL7*")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,AD3,,,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6,,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" endif if ((per.l(ad:0x4002B010+0x10)&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "ADC_RC,ADC Data Result Register C" hexmask.long.byte 0x00 0.--7. 1. " D0-7 ,8-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "ADC_RC,ADC Data Result Register C" hexmask.long.word 0x00 0.--9. 1. " D0-9 ,10-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "ADC_RC,ADC Data Result Register C" hexmask.long.word 0x00 0.--11. 1. " D0-11 ,12-bit single ended" else group.long 0x18++0x03 line.long 0x00 "ADC_RC,ADC Data Result Register C" hexmask.long.word 0x00 0.--15. 1. " D0-15 ,16-bit single ended" endif width 0x0B tree.end tree "CHANNEL D" base ad:0x4002B00C width 10. group.long 0x00++0x03 line.long 0x00 "ADC_SC1D,ADC Status and Control Registers 1" rbitfld.long 0x00 7. " COCO , Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt Enable" "Disabled,Enabled" sif (cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM34Z256VLL7*")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,AD3,,,AD6,AD7,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" elif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" else bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,,,,AD6,,AD8,AD9,AD10,AD11,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,VREFSH-SC2[REFSEL],VREFSL-SC2[REFSEL],Disabled" endif if ((per.l(ad:0x4002B010+0x10)&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "ADC_RD,ADC Data Result Register D" hexmask.long.byte 0x00 0.--7. 1. " D0-7 ,8-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "ADC_RD,ADC Data Result Register D" hexmask.long.word 0x00 0.--9. 1. " D0-9 ,10-bit single ended" elif ((per.l(ad:0x4002B010+0x10)&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "ADC_RD,ADC Data Result Register D" hexmask.long.word 0x00 0.--11. 1. " D0-11 ,12-bit single ended" else group.long 0x18++0x03 line.long 0x00 "ADC_RD,ADC Data Result Register D" hexmask.long.word 0x00 0.--15. 1. " D0-15 ,16-bit single ended" endif width 0x0B tree.end tree.end tree "CMP (Comparator)" tree "CHANNEL 0" base ad:0x40072000 width 12. group.byte 0x00++0x05 line.byte 0x00 "CMP0_CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter Sample Count" "Disabled,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CMP0_CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing Enable" "Disabled,Enabled" bitfld.byte 0x01 5. " TRIGM ,Trigger Mode Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " PMODE ,Power Mode Select" "Low-Speed,High-Speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Non Inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator Output Select" "Unfiltered,Filtered" textline " " bitfld.byte 0x01 1. " OPE ,Comparator Output Pin Enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator Module Enable" "Disabled,Enabled" line.byte 0x02 "CMP0_FPR,CMP Filter Period Register" line.byte 0x03 "CMP0_SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA Enable Control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator Interrupt Enable Rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator Interrupt Enable Falling" "Disabled,Enabled" textline " " eventfld.byte 0x03 2. " CFR ,Analog Comparator Flag Rising" "Not detected,Detected" eventfld.byte 0x03 1. " CFF , Analog Comparator Flag Falling" "Not detected,Detected" rbitfld.byte 0x03 0. " COUT ,Analog Comparator Output" "0,1" line.byte 0x04 "CMP0_DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC Enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply Voltage Reference Source Select" "Vin1in,Vin2in" bitfld.byte 0x04 0.--5. " VOSEL ,DAC Output Voltage Select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "CMP0_MUXCR,MUX Control Register" sif cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" else bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree "CHANNEL 1" base ad:0x40072008 width 12. group.byte 0x00++0x05 line.byte 0x00 "CMP1_CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter Sample Count" "Disabled,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CMP1_CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing Enable" "Disabled,Enabled" bitfld.byte 0x01 5. " TRIGM ,Trigger Mode Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " PMODE ,Power Mode Select" "Low-Speed,High-Speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Non Inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator Output Select" "Unfiltered,Filtered" textline " " bitfld.byte 0x01 1. " OPE ,Comparator Output Pin Enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator Module Enable" "Disabled,Enabled" line.byte 0x02 "CMP1_FPR,CMP Filter Period Register" line.byte 0x03 "CMP1_SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA Enable Control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator Interrupt Enable Rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator Interrupt Enable Falling" "Disabled,Enabled" textline " " eventfld.byte 0x03 2. " CFR ,Analog Comparator Flag Rising" "Not detected,Detected" eventfld.byte 0x03 1. " CFF , Analog Comparator Flag Falling" "Not detected,Detected" rbitfld.byte 0x03 0. " COUT ,Analog Comparator Output" "0,1" line.byte 0x04 "CMP1_DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC Enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply Voltage Reference Source Select" "Vin1in,Vin2in" bitfld.byte 0x04 0.--5. " VOSEL ,DAC Output Voltage Select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "CMP1_MUXCR,MUX Control Register" sif cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" else bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") tree "CHANNEL 2" base ad:0x40072010 width 12. group.byte 0x00++0x05 line.byte 0x00 "CMP2_CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter Sample Count" "Disabled,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CMP2_CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample Enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing Enable" "Disabled,Enabled" bitfld.byte 0x01 5. " TRIGM ,Trigger Mode Enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " PMODE ,Power Mode Select" "Low-Speed,High-Speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Non Inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator Output Select" "Unfiltered,Filtered" textline " " bitfld.byte 0x01 1. " OPE ,Comparator Output Pin Enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator Module Enable" "Disabled,Enabled" line.byte 0x02 "CMP2_FPR,CMP Filter Period Register" line.byte 0x03 "CMP2_SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA Enable Control" "Disabled,Enabled" bitfld.byte 0x03 4. " IER ,Comparator Interrupt Enable Rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator Interrupt Enable Falling" "Disabled,Enabled" textline " " eventfld.byte 0x03 2. " CFR ,Analog Comparator Flag Rising" "Not detected,Detected" eventfld.byte 0x03 1. " CFF , Analog Comparator Flag Falling" "Not detected,Detected" rbitfld.byte 0x03 0. " COUT ,Analog Comparator Output" "0,1" line.byte 0x04 "CMP2_DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC Enable" "Disabled,Enabled" bitfld.byte 0x04 6. " VRSEL ,Supply Voltage Reference Source Select" "Vin1in,Vin2in" bitfld.byte 0x04 0.--5. " VOSEL ,DAC Output Voltage Select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "CMP2_MUXCR,MUX Control Register" sif cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,12-bit DAC,REF,,6-bit DAC" else bitfld.byte 0x05 3.--5. " PSEL ,Plus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus Input Mux Control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end endif tree.end tree "VREF (Voltage Reference)" base ad:0x4006F000 width 16. group.byte 0x00++0x02 line.byte 0x00 "VREF_VREFH_TRM,VREF Trim Register" bitfld.byte 0x00 6. " CHOPEN ,Chop oscillator enable" "Disabled,Enabled" bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max" line.byte 0x01 "VREF_VREFH_SC,VREF Status and Control Register" bitfld.byte 0x01 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled" bitfld.byte 0x01 6. " REGEN ,Regulator enable" "Disabled,Enabled" sif !cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*") bitfld.byte 0x01 5. " ICOMPEN ,Second order curvature compensation enable" "Disabled,Enabled" endif textline " " rbitfld.byte 0x01 2. " VREFST ,Internal voltage reference stable" "Not stable,Stable" bitfld.byte 0x01 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High power buffer,Low-power buffer,?..." line.byte 0x02 "VREF_VREFL_TRM,VREFL TRIM Register" bitfld.byte 0x02 4. " VREFL_SEL ,Voltage reference select" "Internal,External" bitfld.byte 0x02 3. " VREFL_EN ,Voltage reference buffer" "Disabled,Enabled" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7*") bitfld.byte 0x02 0.--2. " VREFL_TRIM ,Voltage reference trimmer" "370mV,380mV,390mV,400mV,410mV,420mV,?..." else bitfld.byte 0x02 0.--2. " VREFL_TRIM ,Voltage reference trimmer" "370mV,380mV,390mV,400mV,410mV,420mV,430mV,440mV" endif width 0x0B tree.end tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. if (((per.b(ad:0x40064000+0x001))&0x30)==0x00||((per.b(ad:0x40064000+0x00C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MK11DN512AVLK5*") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" ",Internal ref clk,External ref clk,?..." newline else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." newline endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK63FN1M0VLQ12")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0VMI18")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK66FN2M0VLQ18") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" elif cpuis("MK40D*Z*10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK??F*")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,?..." else bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" endif newline bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif !cpuis("MK20D*AB10")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" newline endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))||cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60D*") sif !cpuis("MK60D*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increased,Decreased" endif bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline else sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-39kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline elif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-40kHz,3MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline else bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "1kHz-32kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline endif bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline endif bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "FLL||PLL enabled,FLL||PLL disabled" bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x003))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20 - 25 MHz,24 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,Dco maximum frequency with 32.768 kHz reference" "40 - 50 MHz,48 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60 - 75 MHz,72 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80 - 100 MHz,96 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" endif sif !cpuis("MK02*") sif cpuis("MK??F*")||cpuis("MK60D*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. "PLLREFSEL0,PLL0 external reference select" "OSC0,OSC1" endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif !cpuis("MK21F*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK63FN1M0VLQ12R") newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*") bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "OSC0,OSC1" else bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "Disabled,Enabled" endif endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" sif CPUIS("MK20FN1M0VLQ12R") newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif cpuis("MK20F*")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." else newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" endif else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 7. " LOLIE ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*") sif !cpuis("MK20F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK70F*")&&!cpuis("MK8?FN256V*")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") newline bitfld.byte 0x00 0.--4. " CHGPMP_BIAS ,PLL charge pump current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif endif else group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif !cpuis("MK02*") bitfld.byte 0x00 7. " LOLS ,Loss of lock status" "Not lost,Lost" bitfld.byte 0x00 6. " LOCK ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,Out PLL" bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline else bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline endif bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" sif cpuis("MK20D*AB10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" elif cpuis("KK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else group.byte 0x08++0x00 line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" endif newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" else eventfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" endif endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5*")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 6.--7. " PLL32KREFSEL ,MCG PLL 32kHz reference clock select" "32kHz RTC,32kHz IRC,FLL FRDIV,?..." sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") newline bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" else newline bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." endif elif cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512CAP12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." else group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" endif sif !cpuis("MK70*")&&!cpuis("MK02*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK60FN1M0VLQ15") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" endif bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif !cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK30DX256VLL7R")&&!cpuis("MK02F*")&&!cpuis("MK63FN1M0VLQ12R") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rgroup.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 7. " COARSE_LOLS ,Coarse loss of lock status" "Not occurred,Occurred" bitfld.byte 0x00 6. " COARSE_LOCK ,Coarse lock status" "Unlocked,Locked" elif cpuis("MK66*")||cpuis("MK65*")||cpuis("KK65FN2M0CAC18R")||cpuis("MK63FN1M0VLQ12R") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Interrupt,Sys. reset" eventfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" elif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK10D*5")&&!cpuis("MK70*")&&!cpuis("MK11*")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R") hgroup.byte 0x0E++0x00 hide.byte 0x00 "C9,MCG Control 9 Register" endif sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*") sif cpuis("MK??F*")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("KK65FN2M0CAC18R") group.byte 0x0F++0x02 line.byte 0x00 "C10,MCG Control 10 Register" bitfld.byte 0x00 7. " LOCRE2 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 4.--5. " RANGE1 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO1 ,High gain oscillator select" "Low-power,High-gain" newline bitfld.byte 0x00 2. " EREFS1 ,External reference select" "Ext ref,Osc" line.byte 0x01 "C11,MCG Control 11 Register" sif cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "OSC0,OSC1" else bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "Disabled,Enabled" endif newline bitfld.byte 0x01 6. " PLLCLKEN1 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x01 5. " PLLSTEN1 ,PLL stop enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " PLLCS ,PLL clock select" "PLL0,PLL1" bitfld.byte 0x01 0.--2. " PRDIV1 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" line.byte 0x02 "C12,MCG Control 12 Register" bitfld.byte 0x02 7. " LOLIE1 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " CME2 ,Clock monitor enable" "Disabled,Enabled" newline sif !cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" else bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status Register" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" else eventfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" endif bitfld.byte 0x00 6. " LOCK1 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL1" newline bitfld.byte 0x00 1. " OSCINIT1 ,OSC initialization" "Not completed,Completed" bitfld.byte 0x00 0. " LOCS2 ,OSC1 loss of clock status" "No loss of OSC1,Loss of OSC1" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" endif elif cpuis("MK66*")||cpuis("MK65*") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" hgroup.byte 0x13++0x00 hide.byte 0x00 "T3,MCG Test 3 Register" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" elif cpuis("MK63FN1M0VLQ12R") hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" endif endif endif endif width 0x0B tree.end tree "OSC (Oscillator)" base ad:0x40066000 width 4. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKV5*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18*") width 9. newline group.byte 0x02++0x00 line.byte 0x00 "OSC_DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "IRTC (Independent Real Time Clock)" base ad:0x40050000 width 22. group.word 0x00++0x21 line.word 0x00 "RTC_YEARMON,RTC Year and Month Counters Register" hexmask.word.byte 0x00 8.--15. 1. " YROFST ,Year offset count value" bitfld.word 0x00 0.--3. " MON_CNT ,Months counter" "-,January,February,March,April,May,June,July,August,September,October,November,December,-,-,-" line.word 0x02 "RTC_DAYS,RTC Days and Day-of-Week Counters Register" bitfld.word 0x02 8.--10. " DOW ,Day of week counter value" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-" bitfld.word 0x02 0.--4. " DAY_CNT ,Days counter value" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x04 "RTC_HOURMIN,RTC Hours and Minutes Counters Register" bitfld.word 0x04 8.--12. " HOUR_CNT ,Hours counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" bitfld.word 0x04 0.--5. " MIN_CNT ,Minutes counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" line.word 0x06 "RTC_SECONDS,RTC Seconds Counters Register" bitfld.word 0x06 0.--5. " SEC_CNT ,Seconds counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" line.word 0x08 "RTC_ALM_YEARMON,RTC Year and Months Alarm Register" hexmask.word.byte 0x08 8.--15. 1. " ALM_YEAR ,Year value for alarm" bitfld.word 0x08 0.--3. " ALM_MON ,Months value for alarm" "-,January,February,March,April,May,June,July,August,September,October,November,December,-,-,-" line.word 0x0A "RTC_ALM_DAYS,RTC Days Alarm Register" bitfld.word 0x0A 0.--4. " ALM_DAY ,Days value for alarm" "-,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x0C "RTC_ALM_HOURMIN,RTC Hours and Minutes Alarm Register" bitfld.word 0x0C 8.--12. " ALM_HOUR ,Hours value for alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" bitfld.word 0x0C 0.--5. " ALM_MIN ,Minutes value for alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" line.word 0x0E "RTC_ALM_SECONDS,RTC Seconds Alarm Register" bitfld.word 0x0E 9. " INC_SEC ,Increment seconds counter by 1" ",Incremented" bitfld.word 0x0E 8. " DEC_SEC ,Decrement seconds counter by 1" ",Decremented" bitfld.word 0x0E 0.--5. " ALM_SEC ,Seconds value for alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,-,-,-,-" line.word 0x10 "RTC_CTRL,RTC Control Register" bitfld.word 0x10 13.--14. " CLKOUT ,RTC clock output selection" "No Output,Fine 1Hz,32.768Hz,Coarse 1Hz" bitfld.word 0x10 8. " SWR ,Software reset bit" "Not reset,Reset" bitfld.word 0x10 6. " DST_EN ,Daylight saving enable" "Disabled,Enabled" textline " " bitfld.word 0x10 4. " TIMER_STB_MASK ,Sampling timer clocks mask" "Not gated,Gated" bitfld.word 0x10 2.--3. " ALM_MATCH ,Alarm match bits" "hh:mm:ss,dd hh:mm:ss,MM-dd hh:mm:ss,yyyy-MM-dd hh:mm:ss" textline " " sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z128CLH5*") bitfld.word 0x10 1. " COMP_EN ,Compensation enable" "Disabled,Enabled" bitfld.word 0x10 0. " FINEEN ,Fine compensation" "Disabled,Enabled" textline " " else bitfld.word 0x10 0. " FINEEN ,Fine compensation" "Enabled,Disabled" endif line.word 0x12 "RTC_STATUS,RTC Status Register" eventfld.word 0x12 11. " CMP_DONE ,Compensation done" "Busy/Disabled,Completed" eventfld.word 0x12 8. " BUS_ERR ,Bus error" "No error,Error" bitfld.word 0x12 6.--7. " WE ,Write enable" "Disabled,Disabled,Disabled,Enabled" textline " " rbitfld.word 0x12 5. " CMP_INT ,Compensation interval" "0,1" rbitfld.word 0x12 3. " RST_SRC ,Reset source" "Standby Mode Exit,Power-On-Reset" rbitfld.word 0x12 2. " CPU_LOW_VOLT ,CPU low voltage warning status" "Normal,Below Normal" textline " " rbitfld.word 0x12 1. " WRITE_PROT_EN ,Write protect enable status" "Unlocked,Locked" rbitfld.word 0x12 0. " INVAL_BIT ,Invalidate CPU read/write access" "Valid,Invalid" line.word 0x14 "RTC_ISR,RTC Interrupt Status Register" eventfld.word 0x14 15. " IS_512HZ ,512 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 14. " IS_256HZ ,256 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 13. " IS_128HZ ,128 Hz interval interrupt status" "No interrupt,Interrupt" textline " " eventfld.word 0x14 12. " IS_64HZ ,64 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 11. " IS_32HZ ,32 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 10. " IS_16HZ ,16 Hz interval interrupt status" "No interrupt,Interrupt" textline " " eventfld.word 0x14 9. " IS_8HZ ,8 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 8. " IS_4HZ ,4 Hz interval interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 7. " IS_2HZ ,2 Hz interval interrupt status" "No interrupt,Interrupt" textline " " eventfld.word 0x14 6. " IS_1HZ ,1 Hz interval interrupt status" "No interrupt,Interrupt" textline " " sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") eventfld.word 0x14 5. " MIN_IS ,Minutes interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 4. " HOUR_IS ,Hours interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 3. " DAY_IS ,Days interrupt status" "No interrupt,Interrupt" textline " " else eventfld.word 0x14 4. " MIN_IS ,Minutes interrupt status" "No interrupt,Interrupt" eventfld.word 0x14 3. " DAY_IS ,Days interrupt status" "No interrupt,Interrupt" textline " " endif textline " " eventfld.word 0x14 2. " ALM_IS ,Alarm interrupt status" "No interrupt,Interrupt" bitfld.word 0x14 0. " TAMPER_IS ,Tamper interrupt status" "No interrupt,Interrupt" line.word 0x16 "RTC_IER,RTC Interrupt Enable Register" bitfld.word 0x16 15. " IE_512HZ ,512 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 14. " IE_256HZ ,256 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 13. " IE_128HZ ,128 Hz interval interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x16 12. " IE_64HZ ,64 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 11. " IE_32HZ ,32 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 10. " IE_16HZ ,16 Hz interval interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x16 9. " IE_8HZ ,8 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 8. " IE_4HZ ,4 Hz interval interrupt enable" "Disabled,Enabled" bitfld.word 0x16 7. " IE_2HZ ,2 Hz interval interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x16 6. " IE_1HZ ,1 Hz interval interrupt enable" "Disabled,Enabled" textline " " sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") bitfld.word 0x16 5. " MIN_IE ,Minutes interrupt enable" "Disabled,Enabled" bitfld.word 0x16 4. " HOUR_IE ,Hours interrupt enable" "Disabled,Enabled" bitfld.word 0x16 3. " DAY_IE ,Days interrupt enable" "Disabled,Enabled" textline " " else bitfld.word 0x16 4. " MIN_IE ,Minutes interrupt enable" "Disabled,Enabled" bitfld.word 0x16 3. " DAY_IE ,Days interrupt enable" "Disabled,Enabled" textline " " endif textline " " bitfld.word 0x16 2. " ALM_IE ,Alarm interrupt enable" "Disabled,Enabled" bitfld.word 0x16 0. " TAMPER_IE ,Tamper interrupt enable" "Disabled,Enabled" line.word 0x20 "RTC_GP_DATA_REG,RTC General Purpose Data Register" bitfld.word 0x20 7. " CFG7 ,Boot mode override" "VLPR,RUN" bitfld.word 0x20 4. " CFG4 ,Switched capacitor 16pf" "Disabled,Enabled" bitfld.word 0x20 3. " CFG3 ,Switched capacitor 8pf" "Disabled,Enabled" textline " " bitfld.word 0x20 2. " CFG2 ,Switched capacitor 4pf" "Disabled,Enabled" bitfld.word 0x20 1. " CFG1 ,Switched capacitor 2pf" "Disabled,Enabled" bitfld.word 0x20 0. " CFG0 ,32 kHz RTC OSC control" "Disabled,Enabled" if ((per.w(ad:0x40050000+0x10)&0x40)==0x40) rgroup.word 0x22++0x05 line.word 0x00 "RTC_DST_HOUR,RTC Daylight Saving Hour Register" bitfld.word 0x00 8.--12. " DST_START_HOUR ,Daylight saving time (DST) hours start value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" bitfld.word 0x00 0.--4. " DST_END_HOUR ,Daylight saving time (DST) hours end value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,-,-,-,-,-,-,-,-" line.word 0x02 "RTC_DST_MONTH,RTC Daylight Saving Month Register" bitfld.word 0x02 8.--11. " DST_START_MONTH ,Daylight saving time (DST) month start value" "-,January,February,March,April,May,June,July,August,September,October,November,December,-,-,-" bitfld.word 0x02 0.--3. " DST_END_MONTH ,Daylight saving time (DST) month end value" "-,January,February,March,April,May,June,July,August,September,October,November,December,-,-,-" line.word 0x04 "RTC_DST_DAY,RTC Daylight Saving Day Register" bitfld.word 0x04 8.--12. " DST_START_DAY ,Daylight saving time (DST) day start value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x04 0.--4. " DST_END_DAY ,Daylight saving time (DST) day end value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.word 0x22++0x05 line.word 0x00 "RTC_DST_HOUR,RTC Daylight Saving Hour Register" bitfld.word 0x00 8.--12. " DST_START_HOUR ,Daylight saving time (DST) hours start value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.word 0x00 0.--4. " DST_END_HOUR ,Daylight saving time (DST) hours end value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." line.word 0x02 "RTC_DST_MONTH,RTC Daylight Saving Month Register" bitfld.word 0x02 8.--11. " DST_START_MONTH ,Daylight saving time (DST) month start value" ",January,February,March,April,May,June,July,August,September,October,November,December,,," bitfld.word 0x02 0.--3. " DST_END_MONTH ,Daylight saving time (DST) month end value" ",January,February,March,April,May,June,July,August,September,October,November,December,,," line.word 0x04 "RTC_DST_DAY,RTC Daylight Saving Day Register" bitfld.word 0x04 8.--12. " DST_START_DAY ,Daylight saving time (DST) day start value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x04 0.--4. " DST_END_DAY ,Daylight saving time (DST) day end value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif if ((per.w(ad:0x40050000+0x10)&0x01)==0x00) group.word 0x28++0x01 line.word 0x00 "RTC_COMPEN,RTC Compensation Register" hexmask.word.byte 0x00 8.--15. 1. " COMPEN[15:8] ,Compensation interval" hexmask.word.byte 0x00 0.--7. 1. " COMPEN[7:0] ,Compensation/correction value" else group.word 0x28++0x01 line.word 0x00 "RTC_COMPEN,RTC Compensation Register" bitfld.word 0x00 12.--15. " COMPEN[15:12] ,Integral compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word.byte 0x00 0.--6. 1. " COMPEN[6:0] ,Fraction compensation value" endif sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") group.word 0x2C++0x03 line.word 0x00 "RTC_TAMPER_DIRECTION,Tamper Direction Register" bitfld.word 0x00 8.--11. " I_O_TAMP ,Defines the I/O capability of tamper pins" ",,,,,,,,TAMPER0_IN,TAMPER0_OUT,TAMPER1_IN,TAMPER1_OUT,TAMPER2_IN,TAMPER2_OUT,?..." bitfld.word 0x00 0.--3. " A_P_TAMP ,Defines the active/passive selection of the tamper pins" ",,,,,,,,TAMPER0_P,TAMPER0_A,TAMPER1_P,TAMPER1_A,TAMPER2_P,TAMPER2_A,?..." line.word 0x02 "RTC_TAMPER_QSCR,Tamper Queue Status and Control Register" bitfld.word 0x02 12.--15. " LFSR_DURATION ,LFSR Filter duration period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 8.--10. " LFSR_CLK_SEL ,Clock selection for LFSR module" "32kHz,512Hz,128Hz,64Hz,16Hz,8Hz,4Hz,2Hz" bitfld.word 0x02 2. " Q_CLEAR ,Tamper queue" ",Clear TQ" textline " " bitfld.word 0x02 1. " Q_FULL_INT_EN ,Queue full interrupt enable" "Disabled,Enabled" bitfld.word 0x02 0. " Q_FULL ,Tamper Queue full status" "Not full,Full" endif group.word 0x32++0x05 line.word 0x00 "RTC_TAMPER_SCR,RTC Tamper Status and Control Register" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") bitfld.word 0x00 8.--11. " TMPR_STS ,Tamper status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TMPR_EN ,Tamper control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " else bitfld.word 0x00 8.--11. " TMPR_STS ,Tamper status" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.word 0x00 0.--3. " TMPR_EN ,Tamper control" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" endif line.word 0x02 "RTC_FILTER01_CFG,RTC Tamper 01 Filter Configuration Register" bitfld.word 0x02 15. " POL0 ,Tamper detect input bit 0 polarity control" "Active High,Active Low" bitfld.word 0x02 12.--14. " CLK_SEL0 ,Tamper filter 0 clock select" "32 kHz clock,512 Hz clock,128 Hz clock,64 Hz clock,16 Hz clock,8 Hz clock,4 Hz clock,2 Hz clock" bitfld.word 0x02 8.--11. " FIL_DUR0 ,Tamper detect bit 0 filter duration" "Disabled,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" textline " " bitfld.word 0x02 7. " POL1 ,Tamper detect input bit 1 polarity control" "Active High,Active Low" bitfld.word 0x02 4.--6. " CLK_SEL1 ,Tamper filter 1 clock select" "32 kHz clock,512 Hz clock,128 Hz clock,64 Hz clock,16 Hz clock,8 Hz clock,4 Hz clock,2 Hz clock" bitfld.word 0x02 0.--3. " FIL_DUR1 ,Tamper detect bit 1 filter duration" "Disabled,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" line.word 0x04 "RTC_FILTER2_CFG,RTC Tamper 2 Filter Configuration Register" bitfld.word 0x04 15. " POL2 ,Tamper detect input bit 2 polarity control" "Active High,Active Low" bitfld.word 0x04 12.--14. " CLK_SEL2 ,Tamper filter 2 clock select" "32 kHz clock,512 Hz clock,128 Hz clock,64 Hz clock,16 Hz clock,8 Hz clock,4 Hz clock,2 Hz clock" bitfld.word 0x04 8.--11. " FIL_DUR2 ,Tamper detect bit 2 filter duration" "Disabled,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") rgroup.word 0x40++0x01 line.word 0x00 "RTC_TAMPER_QUEUE,Tamper Queue Register" endif group.word 0x42++0x01 line.word 0x00 "RTC_CTRL2,RTC Control 2 Register" bitfld.word 0x00 7. " WAKEUP_MODE ,Wakeup mode" "Disabled,Enabled" bitfld.word 0x00 5.--6. " WAKEUP_STATUS ,Wakeup status" "HiZ,Logic 0,Logic 1,?..." bitfld.word 0x00 0. " TAMP_CFG_OVER ,Tamper configuration over" "Disabled,Enabled" width 0x0B tree.end tree "LPTMR (Low-Power Timer)" base ad:0x4003C000 width 5. if (((per.l(ad:0x4003C000))&0x01)==0x00) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Enabled,Disabled" textline " " endif eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" textline " " bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" textline " " bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 8. " TDRE ,Timer DMA request enable" "Enabled,Disabled" textline " " endif eventfld.long 0x00 7. " TCF ,Timer compare flag" "No match,Match" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" textline " " rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Compare match,Free running" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" textline " " bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if (((per.l(ad:0x4003C000))&0x01)==0x00) if (((per.l(ad:0x4003C000))&0x2)==0x0) group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif else if (((per.l(ad:0x4003C000))&0x2)==0x0) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" else rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" "Disabled,2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "Clock 0,Clock 1,Clock 2,Clock 3" endif endif if (((per.l(ad:0x4003C000))&0x01)==0x00)||(((per.l(ad:0x4003C000))&0x81)==0x81) group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif else rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" sif !cpuis("K32W0?2S1M*") hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif endif sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5*")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z128ACLL5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKW*")||cpuis("MKV5*")) group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" elif cpuis("K32W0?2S1M*") group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree "PIT (Periodic Interrupt Timer)" tree "PIT 0" base ad:0x4002D000 width 17. group.long 0x00++0x03 line.long 0x00 "PIT0_MCR,PIT0 Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Run,Stopped" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rgroup.long 0xE0++0x07 line.long 0x00 "PIT0_LTMR64H,PIT0 Upper Lifetime Timer Register" line.long 0x04 "PIT0_LTMR64L,PIT0 Lower Lifetime Timer Register" endif group.long 0x100++0x03 line.long 0x00 "PIT0_LDVAL0,PIT0 Timer Load Value Register 0" rgroup.long 0x104++0x03 line.long 0x00 "PIT0_CVAL0,PIT0 Current Timer Value Register 0" group.long 0x108++0x07 line.long 0x00 "PIT0_TCTRL0,PIT0 Timer Control Register 0" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" textline " " endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "PIT0_TFLG0,Timer Flag Register 0" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" sif !(cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")) group.long 0x110++0x03 line.long 0x00 "PIT0_LDVAL1,PIT0 Timer Load Value Register 1" rgroup.long 0x114++0x03 line.long 0x00 "PIT0_CVAL1,PIT0 Current Timer Value Register 1" group.long 0x118++0x07 line.long 0x00 "PIT0_TCTRL1,PIT0 Timer Control Register 1" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "PIT0_TFLG1,Timer Flag Register 1" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" endif width 0x0B tree.end tree "PIT 1" base ad:0x4002E000 width 17. group.long 0x00++0x03 line.long 0x00 "PIT1_MCR,PIT1 Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Run,Stopped" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rgroup.long 0xE0++0x07 line.long 0x00 "PIT1_LTMR64H,PIT1 Upper Lifetime Timer Register" line.long 0x04 "PIT1_LTMR64L,PIT1 Lower Lifetime Timer Register" endif group.long 0x100++0x03 line.long 0x00 "PIT1_LDVAL0,PIT1 Timer Load Value Register 0" rgroup.long 0x104++0x03 line.long 0x00 "PIT1_CVAL0,PIT1 Current Timer Value Register 0" group.long 0x108++0x07 line.long 0x00 "PIT1_TCTRL0,PIT1 Timer Control Register 0" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" textline " " endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "PIT1_TFLG0,Timer Flag Register 0" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" sif !(cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")) group.long 0x110++0x03 line.long 0x00 "PIT1_LDVAL1,PIT1 Timer Load Value Register 1" rgroup.long 0x114++0x03 line.long 0x00 "PIT1_CVAL1,PIT1 Current Timer Value Register 1" group.long 0x118++0x07 line.long 0x00 "PIT1_TCTRL1,PIT1 Timer Control Register 1" bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" line.long 0x04 "PIT1_TFLG1,Timer Flag Register 1" eventfld.long 0x04 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" endif width 0x0B tree.end tree.end tree "TMR (Quad Timer)" tree "TIMER 0" base ad:0x40057000 width 14. group.word 0x00++0x0D line.word 0x00 "TMR0_COMP1,Timer Channel Compare Register 1" line.word 0x02 "TMR0_COMP2,Timer Channel Compare Register 2" line.word 0x04 "TMR0_CAPT,Timer Channel Capture Register" line.word 0x06 "TMR0_LOAD,Timer Channel Load Register" line.word 0x08 "TMR0_HOLD,Timer Channel Hold Register" line.word 0x0A "TMR0_CNTR,Timer Channel Counter Register" line.word 0x0C "TMR0_CTRL,Timer Channel Control Register" bitfld.word 0x0C 13.--15. " CM0 ,Count mode" "No operation,Rising edge(Primary),Rising && falling edges(Primary),Rising edge(Primary) - Input high active(Secondary),Quadrature,Rising edge(Primary)-Direction(Secondary),Secondary triggers primary,Cascaded" textline " " bitfld.word 0x0C 9.--12. " PCS0 ,Primary count source" "Input 0,Input 1,Input 2,Input 3,Output 0,Output 1,Output 2,Output 3,IPBus/1,IP Bus/2,IP Bus/4,IP Bus/8,IP Bus/16,IP Bus/32,IP Bus/64,IP Bus/128" bitfld.word 0x0C 7.--8. " SCS0 ,Secondary Count Source" "Input 0,Input 1,Input 2,Input 3" bitfld.word 0x0C 6. " ONCE0 ,Count once" "Disabled,Enabled" textline " " bitfld.word 0x0C 5. " LENGTH0 , Count length" "Roll over,Until compare" bitfld.word 0x0C 4. " DIR0 ,Count direction" "Up,Down" bitfld.word 0x0C 3. " COINIT0 ,Co-channel initialization" "Disabled,Enabled" textline " " bitfld.word 0x0C 0.--2. " OUTMODE0 ,Output mode" "Asserted(Active),Clear OFLAG,Set OFLAG,Toggle OFLAG,Toggle OFLAG(Alternating),Set on compare(Sec-InputEdge),Set on compare(RollOver),Gated clock" if (((per.l(ad:0x40057000+0x0E))&0x200)==0x000) group.word 0x0E++0x01 line.word 0x00 "TMR0_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF0 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE0 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF0 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE0 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF0 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE0 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS0 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT0 ,External Input Signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE0 ,Input capture mode" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR0 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF0 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL0 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE0 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS0 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN0 ,Output enable" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "TMR0_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF0 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE0 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF0 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE0 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF0 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE0 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS0 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT0 ,External input signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE0 ,Input capture mode" "Disabled,Falling edge,Rising edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR0 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF0 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL0 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE0 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS0 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN0 ,Output enable" "Disabled,Enabled" endif group.word 0x10++0x07 line.word 0x00 "TMR0_CMPLD1,Timer Channel Comparator Load Register 1" line.word 0x02 "TMR0_CMPLD2,Timer Channel Comparator Load Register 2" line.word 0x04 "TMR0_CSCTRL,Timer Channel Comparator Status and Control Register" bitfld.word 0x04 14.--15. " DBG_EN0 ,Debug actions enable" "Normal,Halt TMR,Force TMR Low,Halt and Force Low" bitfld.word 0x04 13. " FAULT0 ,Fault enable" "Disabled,Enabled" bitfld.word 0x04 12. " ALT_LOAD0 ,Alternative load enable" "LOAD,LOAD/CMPLD2" textline " " bitfld.word 0x04 11. " ROC0 ,Reload on capture" "Disabled,Enabled" bitfld.word 0x04 10. " TCI0 ,Triggered count initialization control" "Stop,Reload" rbitfld.word 0x04 9. " UP0 ,Counting direction indicator" "Down,Up" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rbitfld.word 0x04 8. " OFLAG0 ,Output flag" "Low,High" textline " " endif bitfld.word 0x04 7. " TCF2EN0 ,Timer compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " TCF1EN0 ,Timer compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 5. " TCF20 ,Timer compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x04 4. " TCF10 ,Timer compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x04 2.--3. " CL20 ,Compare load control 2" "Never preload,Load(COMP1),Load(COMP2),?..." bitfld.word 0x04 0.--1. " CL10 ,Compare load control 1" "Never preload,Load(COMP1),Load(COMP2),?..." line.word 0x06 "TMR0_FILT,Timer Channel Input Filter Register" bitfld.word 0x06 8.--10. " FILT_CNT0 ,Input filter sample count" "3-samples,4-samples,5-samples,6-samples,7-samples,8-samples,9-samples,10-samples" hexmask.word.byte 0x06 0.--7. 1. " FILT_PER0 ,Input filter sample period" group.word 0x1E++0x01 line.word 0x00 "TMR0_ENBL,Timer Channel Enable Register" bitfld.word 0x00 3. " ENBL3 ,Timer channel 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " ENBL2 ,Timer channel 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " ENBL1 ,Timer channel 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " ENBL0 ,Timer channel 0 enable" "Disabled,Enabled" width 0x0B tree.end tree "TIMER 1" base ad:0x40058000 width 14. group.word 0x00++0x0D line.word 0x00 "TMR1_COMP1,Timer Channel Compare Register 1" line.word 0x02 "TMR1_COMP2,Timer Channel Compare Register 2" line.word 0x04 "TMR1_CAPT,Timer Channel Capture Register" line.word 0x06 "TMR1_LOAD,Timer Channel Load Register" line.word 0x08 "TMR1_HOLD,Timer Channel Hold Register" line.word 0x0A "TMR1_CNTR,Timer Channel Counter Register" line.word 0x0C "TMR1_CTRL,Timer Channel Control Register" bitfld.word 0x0C 13.--15. " CM1 ,Count mode" "No operation,Rising edge(Primary),Rising && falling edges(Primary),Rising edge(Primary) - Input high active(Secondary),Quadrature,Rising edge(Primary)-Direction(Secondary),Secondary triggers primary,Cascaded" textline " " bitfld.word 0x0C 9.--12. " PCS1 ,Primary count source" "Input 0,Input 1,Input 2,Input 3,Output 0,Output 1,Output 2,Output 3,IPBus/1,IP Bus/2,IP Bus/4,IP Bus/8,IP Bus/16,IP Bus/32,IP Bus/64,IP Bus/128" bitfld.word 0x0C 7.--8. " SCS1 ,Secondary Count Source" "Input 0,Input 1,Input 2,Input 3" bitfld.word 0x0C 6. " ONCE1 ,Count once" "Disabled,Enabled" textline " " bitfld.word 0x0C 5. " LENGTH1 , Count length" "Roll over,Until compare" bitfld.word 0x0C 4. " DIR1 ,Count direction" "Up,Down" bitfld.word 0x0C 3. " COINIT1 ,Co-channel initialization" "Disabled,Enabled" textline " " bitfld.word 0x0C 0.--2. " OUTMODE1 ,Output mode" "Asserted(Active),Clear OFLAG,Set OFLAG,Toggle OFLAG,Toggle OFLAG(Alternating),Set on compare(Sec-InputEdge),Set on compare(RollOver),Gated clock" if (((per.l(ad:0x40058000+0x0E))&0x200)==0x000) group.word 0x0E++0x01 line.word 0x00 "TMR1_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF1 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE1 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF1 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE1 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF1 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE1 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS1 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT1 ,External Input Signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE1 ,Input capture mode" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR1 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF1 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL1 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE1 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS1 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN1 ,Output enable" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "TMR1_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF1 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE1 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF1 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE1 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF1 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE1 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS1 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT1 ,External input signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE1 ,Input capture mode" "Disabled,Falling edge,Rising edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR1 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF1 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL1 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE1 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS1 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN1 ,Output enable" "Disabled,Enabled" endif group.word 0x10++0x07 line.word 0x00 "TMR1_CMPLD1,Timer Channel Comparator Load Register 1" line.word 0x02 "TMR1_CMPLD2,Timer Channel Comparator Load Register 2" line.word 0x04 "TMR1_CSCTRL,Timer Channel Comparator Status and Control Register" bitfld.word 0x04 14.--15. " DBG_EN1 ,Debug actions enable" "Normal,Halt TMR,Force TMR Low,Halt and Force Low" bitfld.word 0x04 13. " FAULT1 ,Fault enable" "Disabled,Enabled" bitfld.word 0x04 12. " ALT_LOAD1 ,Alternative load enable" "LOAD,LOAD/CMPLD2" textline " " bitfld.word 0x04 11. " ROC1 ,Reload on capture" "Disabled,Enabled" bitfld.word 0x04 10. " TCI1 ,Triggered count initialization control" "Stop,Reload" rbitfld.word 0x04 9. " UP1 ,Counting direction indicator" "Down,Up" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rbitfld.word 0x04 8. " OFLAG1 ,Output flag" "Low,High" textline " " endif bitfld.word 0x04 7. " TCF2EN1 ,Timer compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " TCF1EN1 ,Timer compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 5. " TCF21 ,Timer compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x04 4. " TCF11 ,Timer compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x04 2.--3. " CL21 ,Compare load control 2" "Never preload,Load(COMP1),Load(COMP2),?..." bitfld.word 0x04 0.--1. " CL11 ,Compare load control 1" "Never preload,Load(COMP1),Load(COMP2),?..." line.word 0x06 "TMR1_FILT,Timer Channel Input Filter Register" bitfld.word 0x06 8.--10. " FILT_CNT1 ,Input filter sample count" "3-samples,4-samples,5-samples,6-samples,7-samples,8-samples,9-samples,10-samples" hexmask.word.byte 0x06 0.--7. 1. " FILT_PER1 ,Input filter sample period" group.word 0x1E++0x01 line.word 0x00 "TMR1_ENBL,Timer Channel Enable Register" bitfld.word 0x00 3. " ENBL3 ,Timer channel 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " ENBL2 ,Timer channel 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " ENBL1 ,Timer channel 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " ENBL0 ,Timer channel 0 enable" "Disabled,Enabled" width 0x0B tree.end tree "TIMER 2" base ad:0x40059000 width 14. group.word 0x00++0x0D line.word 0x00 "TMR2_COMP1,Timer Channel Compare Register 1" line.word 0x02 "TMR2_COMP2,Timer Channel Compare Register 2" line.word 0x04 "TMR2_CAPT,Timer Channel Capture Register" line.word 0x06 "TMR2_LOAD,Timer Channel Load Register" line.word 0x08 "TMR2_HOLD,Timer Channel Hold Register" line.word 0x0A "TMR2_CNTR,Timer Channel Counter Register" line.word 0x0C "TMR2_CTRL,Timer Channel Control Register" bitfld.word 0x0C 13.--15. " CM2 ,Count mode" "No operation,Rising edge(Primary),Rising && falling edges(Primary),Rising edge(Primary) - Input high active(Secondary),Quadrature,Rising edge(Primary)-Direction(Secondary),Secondary triggers primary,Cascaded" textline " " bitfld.word 0x0C 9.--12. " PCS2 ,Primary count source" "Input 0,Input 1,Input 2,Input 3,Output 0,Output 1,Output 2,Output 3,IPBus/1,IP Bus/2,IP Bus/4,IP Bus/8,IP Bus/16,IP Bus/32,IP Bus/64,IP Bus/128" bitfld.word 0x0C 7.--8. " SCS2 ,Secondary Count Source" "Input 0,Input 1,Input 2,Input 3" bitfld.word 0x0C 6. " ONCE2 ,Count once" "Disabled,Enabled" textline " " bitfld.word 0x0C 5. " LENGTH2 , Count length" "Roll over,Until compare" bitfld.word 0x0C 4. " DIR2 ,Count direction" "Up,Down" bitfld.word 0x0C 3. " COINIT2 ,Co-channel initialization" "Disabled,Enabled" textline " " bitfld.word 0x0C 0.--2. " OUTMODE2 ,Output mode" "Asserted(Active),Clear OFLAG,Set OFLAG,Toggle OFLAG,Toggle OFLAG(Alternating),Set on compare(Sec-InputEdge),Set on compare(RollOver),Gated clock" if (((per.l(ad:0x40059000+0x0E))&0x200)==0x000) group.word 0x0E++0x01 line.word 0x00 "TMR2_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF2 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE2 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF2 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE2 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF2 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE2 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS2 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT2 ,External Input Signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE2 ,Input capture mode" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR2 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF2 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL2 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE2 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS2 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN2 ,Output enable" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "TMR2_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF2 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE2 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF2 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE2 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF2 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE2 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS2 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT2 ,External input signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE2 ,Input capture mode" "Disabled,Falling edge,Rising edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR2 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF2 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL2 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE2 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS2 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN2 ,Output enable" "Disabled,Enabled" endif group.word 0x10++0x07 line.word 0x00 "TMR2_CMPLD1,Timer Channel Comparator Load Register 1" line.word 0x02 "TMR2_CMPLD2,Timer Channel Comparator Load Register 2" line.word 0x04 "TMR2_CSCTRL,Timer Channel Comparator Status and Control Register" bitfld.word 0x04 14.--15. " DBG_EN2 ,Debug actions enable" "Normal,Halt TMR,Force TMR Low,Halt and Force Low" bitfld.word 0x04 13. " FAULT2 ,Fault enable" "Disabled,Enabled" bitfld.word 0x04 12. " ALT_LOAD2 ,Alternative load enable" "LOAD,LOAD/CMPLD2" textline " " bitfld.word 0x04 11. " ROC2 ,Reload on capture" "Disabled,Enabled" bitfld.word 0x04 10. " TCI2 ,Triggered count initialization control" "Stop,Reload" rbitfld.word 0x04 9. " UP2 ,Counting direction indicator" "Down,Up" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rbitfld.word 0x04 8. " OFLAG2 ,Output flag" "Low,High" textline " " endif bitfld.word 0x04 7. " TCF2EN2 ,Timer compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " TCF1EN2 ,Timer compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 5. " TCF22 ,Timer compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x04 4. " TCF12 ,Timer compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x04 2.--3. " CL22 ,Compare load control 2" "Never preload,Load(COMP1),Load(COMP2),?..." bitfld.word 0x04 0.--1. " CL12 ,Compare load control 1" "Never preload,Load(COMP1),Load(COMP2),?..." line.word 0x06 "TMR2_FILT,Timer Channel Input Filter Register" bitfld.word 0x06 8.--10. " FILT_CNT2 ,Input filter sample count" "3-samples,4-samples,5-samples,6-samples,7-samples,8-samples,9-samples,10-samples" hexmask.word.byte 0x06 0.--7. 1. " FILT_PER2 ,Input filter sample period" group.word 0x1E++0x01 line.word 0x00 "TMR2_ENBL,Timer Channel Enable Register" bitfld.word 0x00 3. " ENBL3 ,Timer channel 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " ENBL2 ,Timer channel 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " ENBL1 ,Timer channel 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " ENBL0 ,Timer channel 0 enable" "Disabled,Enabled" width 0x0B tree.end tree "TIMER 3" base ad:0x4005A000 width 14. group.word 0x00++0x0D line.word 0x00 "TMR3_COMP1,Timer Channel Compare Register 1" line.word 0x02 "TMR3_COMP2,Timer Channel Compare Register 2" line.word 0x04 "TMR3_CAPT,Timer Channel Capture Register" line.word 0x06 "TMR3_LOAD,Timer Channel Load Register" line.word 0x08 "TMR3_HOLD,Timer Channel Hold Register" line.word 0x0A "TMR3_CNTR,Timer Channel Counter Register" line.word 0x0C "TMR3_CTRL,Timer Channel Control Register" bitfld.word 0x0C 13.--15. " CM3 ,Count mode" "No operation,Rising edge(Primary),Rising && falling edges(Primary),Rising edge(Primary) - Input high active(Secondary),Quadrature,Rising edge(Primary)-Direction(Secondary),Secondary triggers primary,Cascaded" textline " " bitfld.word 0x0C 9.--12. " PCS3 ,Primary count source" "Input 0,Input 1,Input 2,Input 3,Output 0,Output 1,Output 2,Output 3,IPBus/1,IP Bus/2,IP Bus/4,IP Bus/8,IP Bus/16,IP Bus/32,IP Bus/64,IP Bus/128" bitfld.word 0x0C 7.--8. " SCS3 ,Secondary Count Source" "Input 0,Input 1,Input 2,Input 3" bitfld.word 0x0C 6. " ONCE3 ,Count once" "Disabled,Enabled" textline " " bitfld.word 0x0C 5. " LENGTH3 , Count length" "Roll over,Until compare" bitfld.word 0x0C 4. " DIR3 ,Count direction" "Up,Down" bitfld.word 0x0C 3. " COINIT3 ,Co-channel initialization" "Disabled,Enabled" textline " " bitfld.word 0x0C 0.--2. " OUTMODE3 ,Output mode" "Asserted(Active),Clear OFLAG,Set OFLAG,Toggle OFLAG,Toggle OFLAG(Alternating),Set on compare(Sec-InputEdge),Set on compare(RollOver),Gated clock" if (((per.l(ad:0x4005A000+0x0E))&0x200)==0x000) group.word 0x0E++0x01 line.word 0x00 "TMR3_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF3 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE3 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF3 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE3 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF3 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE3 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS3 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT3 ,External Input Signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE3 ,Input capture mode" "Disabled,Rising edge,Falling edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR3 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF3 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL3 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE3 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS3 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN3 ,Output enable" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "TMR3_SCTRL,Timer Channel Status and Control Register" bitfld.word 0x00 15. " TCF3 ,Timer compare flag" "Not occurred,Occurred" bitfld.word 0x00 14. " TCFIE3 ,Timer compare flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 13. " TOF3 ,Timer overflow flag" "No overflow,Overflow" textline " " bitfld.word 0x00 12. " TOFIE3 ,Timer overflow flag interrupt enable" "Disabled,Enabled" bitfld.word 0x00 11. " IEF3 ,Input edge flag" "Not detected,Detected" bitfld.word 0x00 10. " IEFIE3 ,Input edge flag interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " IPS3 ,Input polarity select" "Normal,Inverted" rbitfld.word 0x00 8. " INPUT3 ,External input signal" "Low,High" bitfld.word 0x00 6.--7. " CAPTURE_MODE3 ,Input capture mode" "Disabled,Falling edge,Rising edge,Both edges" textline " " bitfld.word 0x00 5. " MSTR3 ,Master mode" "Disabled,Enabled" bitfld.word 0x00 4. " EEOF3 ,Enable external OFLAG force" "Disabled,Enabled" bitfld.word 0x00 3. " VAL3 ,Forced OFLAG value" "Low,High" textline " " bitfld.word 0x00 2. " FORCE3 ,Forced OFLAG output" ",Write to OFLAG" bitfld.word 0x00 1. " OPS3 ,Output polarity select" "Normal,Inverted" bitfld.word 0x00 0. " OEN3 ,Output enable" "Disabled,Enabled" endif group.word 0x10++0x07 line.word 0x00 "TMR3_CMPLD1,Timer Channel Comparator Load Register 1" line.word 0x02 "TMR3_CMPLD2,Timer Channel Comparator Load Register 2" line.word 0x04 "TMR3_CSCTRL,Timer Channel Comparator Status and Control Register" bitfld.word 0x04 14.--15. " DBG_EN3 ,Debug actions enable" "Normal,Halt TMR,Force TMR Low,Halt and Force Low" bitfld.word 0x04 13. " FAULT3 ,Fault enable" "Disabled,Enabled" bitfld.word 0x04 12. " ALT_LOAD3 ,Alternative load enable" "LOAD,LOAD/CMPLD2" textline " " bitfld.word 0x04 11. " ROC3 ,Reload on capture" "Disabled,Enabled" bitfld.word 0x04 10. " TCI3 ,Triggered count initialization control" "Stop,Reload" rbitfld.word 0x04 9. " UP3 ,Counting direction indicator" "Down,Up" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") rbitfld.word 0x04 8. " OFLAG3 ,Output flag" "Low,High" textline " " endif bitfld.word 0x04 7. " TCF2EN3 ,Timer compare 2 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 6. " TCF1EN3 ,Timer compare 1 interrupt enable" "Disabled,Enabled" bitfld.word 0x04 5. " TCF23 ,Timer compare 2 interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x04 4. " TCF13 ,Timer compare 1 interrupt flag" "No interrupt,Interrupt" bitfld.word 0x04 2.--3. " CL23 ,Compare load control 2" "Never preload,Load(COMP1),Load(COMP2),?..." bitfld.word 0x04 0.--1. " CL13 ,Compare load control 1" "Never preload,Load(COMP1),Load(COMP2),?..." line.word 0x06 "TMR3_FILT,Timer Channel Input Filter Register" bitfld.word 0x06 8.--10. " FILT_CNT3 ,Input filter sample count" "3-samples,4-samples,5-samples,6-samples,7-samples,8-samples,9-samples,10-samples" hexmask.word.byte 0x06 0.--7. 1. " FILT_PER3 ,Input filter sample period" group.word 0x1E++0x01 line.word 0x00 "TMR3_ENBL,Timer Channel Enable Register" bitfld.word 0x00 3. " ENBL3 ,Timer channel 3 enable" "Disabled,Enabled" bitfld.word 0x00 2. " ENBL2 ,Timer channel 2 enable" "Disabled,Enabled" bitfld.word 0x00 1. " ENBL1 ,Timer channel 1 enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " ENBL0 ,Timer channel 0 enable" "Disabled,Enabled" width 0x0B tree.end tree.end sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") tree "PDB (Programmable Delay Block)" base ad:0x40036000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "MULT,MULT*2,MULT*4,MULT*8,MULT*16,MULT*32,MULT*64,MULT*128" newline sif cpuis("MK20DN512*AB10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif (cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,FTM0,FTM1,FTM2,FTM3,RTC alarm,RTC seconds,LPTMR output,Software trigger" elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,CMP 1,CMP 2,PIT0 Ch 0 output,PIT0 Ch 1 output,PIT1 Ch 0 output,PIT1 Ch 1 output,,,,LPTMR output,RTC alarm,RTC clock out,XBAR out 39,Software trigger" elif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External trigger,CMP 0,,,PIT Ch 0 output,PIT Ch 1 output,PIT Ch 2 output,PIT Ch 3 output,TPM0 overflow,TPM1 overflow,TPM2 overflow,,RTC alarm,RTC seconds,LPTMR output,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif newline bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" newline width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" elif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " BB[6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " BB[5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " BB[4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " BB[3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " BB[2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " TOS[6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " TOS[5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " TOS[4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " TOS[3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " TOS[2] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " EN[6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " EN[5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " EN[4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " EN[3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " EN[2] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" else bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " BB[0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " TOS[0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN[0] ,PDB channel pre-trigger enable" "Disabled,Enabled" endif line.long 0x04 "CH0_S,Channel 0 Status Register" sif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " CF[6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " CF[5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " CF[4] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 19. " CF[3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " CF[2] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " CF[0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " ERR[6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " ERR[5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " ERR[4] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 3. " ERR[3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " ERR[2] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " ERR[0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") group.long (0x10+0x20)++0x07 line.long 0x00 "CH0_DLY2,Channel 0 Delay 2 Register" hexmask.long.word 0x00 0.--15. 1. " DLY ,PDB channel delay" line.long 0x04 "CH0_DLY3,Channel 0 Delay 3 Register" hexmask.long.word 0x04 0.--15. 1. " DLY ,PDB channel delay" endif tree.end newline sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 0. " POEN[0] ,PDB pulse out enable" "Disabled,Enabled" sif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" elif cpuis("KK26FN2M0CAC18R") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x03 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" else group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" endif width 0x0B tree.end endif tree "I2C (Inter-Integrated Circuit)" tree "I2C 0" base ad:0x40067000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" textline " " bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" textline " " bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C0 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" textline " " eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" textline " " eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C0 Data I/O Register" in if ((per.b(ad:0x40067000+0x5)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" textline " " bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" textline " " bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x5 line.byte 0x00 "FLT,I2C0 Programmable Input Glitch Filter Register" sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))) bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")) bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C0 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" textline " " eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "No start,Start" bitfld.byte 0x00 0.--3. " FLT ,I2C0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C0 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C0 address enable" "Disabled,Enabled" textline " " bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" textline " " eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C0 SCL Low Timeout Low Register" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") group.byte 0x0C++0x00 line.byte 0x00 "S2,I2C0 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Error flag" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Empty flag" "Not empty,Empty" endif width 0x0B tree.end sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "I2C 1" base ad:0x40068000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,I2C1 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD[7:1] ,Slave address bits [7:1]" line.byte 0x01 "F,I2C1 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (SCL divider/SDA hold/SCL hold start/SCL hold stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,I2C1 Control Register 1" bitfld.byte 0x02 7. " IICEN ,I2C1 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,I2C1 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" textline " " bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Acknowledged,Not acknowledged" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" textline " " bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S1,I2C1 Status Register 1" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" textline " " eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" textline " " eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" hgroup.byte 0x04++0x00 hide.byte 0x00 "D,I2C1 Data I/O Register" in if ((per.b(ad:0x40068000+0x5)&0x40)==0x40) group.byte 0x05++0x0 line.byte 0x00 "C2,I2C1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" textline " " bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" hexmask.byte 0x00 0.--2. 0x01 " AD[10:8] ,Slave address bits [10:8]" else group.byte 0x05++0x0 line.byte 0x00 "C2,I2C1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,General call address enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Address extension" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,High drive select" "Normal,High" textline " " bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master's,Independent" bitfld.byte 0x00 3. " RMEN ,Range address matching enable" "Disabled,Enabled" endif group.byte 0x06++0x5 line.byte 0x00 "FLT,I2C1 Programmable Input Glitch Filter Register" sif ((cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))) bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC1 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " STOPIE ,I2C bus stop interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (cpuis("MKW21D256VHA5")||cpuis("MKW21D512VHA5")||cpuis("MKW22D512VHA5")||cpuis("MKW24D512VHA5")) bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,I2C1 bus stop detect flag" "Not stopped,Stopped" bitfld.byte 0x00 5. " SSIE ,I2C bus stop interrupt enable" "Disabled,Enabled" textline " " eventfld.byte 0x00 4. " STARTF , I2C bus start detect flag" "No start,Start" bitfld.byte 0x00 0.--3. " FLT ,I2C1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.byte 0x01 "RA,I2C1 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,I2C1 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK,ACK->0TXAK/NACK->1TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second I2C1 address enable" "Disabled,Enabled" textline " " bitfld.byte 0x02 4. " TCKSEL , Timeout counter clock select" "Bus clock / 64 freq,Bus clock freq" eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" textline " " eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,I2C1 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,I2C1 SCL Low Timeout High Register" line.byte 0x05 "SLTL,I2C1 SCL Low Timeout Low Register" sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") group.byte 0x0C++0x00 line.byte 0x00 "S2,I2C1 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Error flag" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Empty flag" "Not empty,Empty" endif width 0x0B tree.end endif tree.end tree "SPI (Serial Peripheral Interface)" tree "SPI 0" base ad:0x40075000 width 14. sif (cpuis("MKW01Z128*")) group.byte 0x00++0x00 line.byte 0x00 "SPI0_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI0_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" endif group.byte 0x01++0x01 line.byte 0x00 "SPI0_BR,SPI Baud Rate Register" bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..." line.byte 0x01 "SPI0_C2,SPI Control Register 2" bitfld.byte 0x01 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit" bitfld.byte 0x01 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled" bitfld.byte 0x01 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled" bitfld.byte 0x01 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped" bitfld.byte 0x01 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode" group.byte 0x03++0x00 line.byte 0x00 "SPI0_C1,SPI Control Register 1" bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled" bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low" bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start" textline " " bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled" bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB" if (((per.b(ad:0x40075000+0x02))&0x40)==0x40) group.byte 0x04++0x03 line.byte 0x00 "SPI0_ML,SPI Match Register Low" line.byte 0x01 "SPI0_MH,SPI Match Register High" line.byte 0x02 "SPI0_DL,SPI Data Register Low" line.byte 0x03 "SPI0_DH,SPI Data Register High" else group.byte 0x04++0x00 line.byte 0x00 "SPI0_ML,SPI Match Register Low" group.byte 0x06++0x00 line.byte 0x00 "SPI0_DL,SPI Data Register Low" endif sif (cpuis("MKW01Z128*")) hgroup.byte 0x0A++0x00 hide.byte 0x00 "SPI0_CI,SPI Clear Interrupt" in group.byte 0x0B++0x00 line.byte 0x00 "SPI0_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" else if ("0"=="1") if (((per.b(ad:0x40075000+0x0B))&0x08)==0x00) rgroup.byte 0x0A++0x00 line.byte 0x00 "SPI0_CI,SPI Clear Interrupt" bitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error" bitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error" bitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error" textline " " bitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error" elif (((per.b(ad:0x40075000+0x0B))&0x08)==0x08) group.byte 0x0A++0x00 line.byte 0x00 "SPI0_CI,SPI Clear Interrupt" rbitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error" rbitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error" rbitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error" textline " " rbitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error" bitfld.byte 0x00 3. " TNEAREFCI ,Transmit FIFO nearly empty flag clear interrupt" "No effect,Clear" bitfld.byte 0x00 2. " RNFULLFCI ,Receive FIFO nearly full empty flag clear interrupt" "No effect,Clear" textline " " bitfld.byte 0x00 1. " SPTEFCI ,Transmit FIFO empty flag clear interrupt" "No effect,Clear" bitfld.byte 0x00 0. " SPRFCI ,Receive FIFO full flag clear interrupt" "No effect,Clear" endif sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x40075000+0x0B))&0x01)==0x01) group.byte 0x0B++0x00 line.byte 0x00 "SPI0_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" else group.byte 0x0B++0x00 line.byte 0x00 "SPI0_C3,SPI Control Register 3" rbitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" rbitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" rbitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " rbitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" endif else group.byte 0x0B++0x00 line.byte 0x00 "SPI0_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" endif endif endif width 0x0B tree.end tree "SPI 1" base ad:0x40076000 width 14. if (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x0B))&0x20)==0x00)&&(((per.b(ad:0x40076000+0x0B))&0x10)==0x00) sif (cpuis("MKW01Z128*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48" rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits" textline " " rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48" bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits" textline " " bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" endif elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x0B))&0x20)==0x20)&&(((per.b(ad:0x40076000+0x0B))&0x10)==0x00) sif (cpuis("MKW01Z128*")) group.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48" rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits" textline " " rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 48 bits,Equal to or greater than 48" bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits" textline " " bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" endif elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x0B))&0x20)==0x00)&&(((per.b(ad:0x40076000+0x0B))&0x10)==0x10) sif (cpuis("MKW01Z128*")) group.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32" rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits" textline " " rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32" bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 16 bits,Equal to or less than 16 bits" textline " " bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" endif elif (((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x0B))&0x20)==0x20)&&(((per.b(ad:0x40076000+0x0B))&0x10)==0x10) sif (cpuis("MKW01Z128*")) group.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" rbitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32" rbitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits" textline " " rbitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" rbitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read FIFO FULL flag" "Not full,Full" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit FIFO empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" bitfld.byte 0x00 3. " RNFULLF ,Receive FIFO nearly full flag" "Less than 32 bits,Equal to or greater than 32" bitfld.byte 0x00 2. " TNEAREF ,Transmit FIFO nearly empty flag" "More than 32 bits,Equal to or less than 32 bits" textline " " bitfld.byte 0x00 1. " TXFULLF ,Transmit FIFO full flag" "Less than 8 bytes,8 bytes" bitfld.byte 0x00 0. " RFIFOEF ,SPI read FIFO empty flag" "Not empty,Empty" endif else sif (cpuis("MKW01Z128*")) group.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" rbitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" rbitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty" textline " " rbitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" else rgroup.byte 0x00++0x00 line.byte 0x00 "SPI1_S,SPI Status Register" bitfld.byte 0x00 7. " SPRF ,SPI read buffer full flag" "No available,Available" eventfld.byte 0x00 6. " SPMF ,SPI match flag" "No match,Match" bitfld.byte 0x00 5. " SPTEF ,SPI transmit buffer empty flag" "Not empty,Empty" textline " " bitfld.byte 0x00 4. " MODF ,Master mode fault flag" "No error,Error" endif endif group.byte 0x01++0x01 line.byte 0x00 "SPI1_BR,SPI Baud Rate Register" bitfld.byte 0x00 4.--6. " SPPR[2:0] ,SPI baud rate prescale divisor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.byte 0x00 0.--3. " SPR[3:0] ,SPI baud rate divisor" "/2,/4,/8,/16,/32,/64,/128,/256,/512,?..." line.byte 0x01 "SPI1_C2,SPI Control Register 2" bitfld.byte 0x01 7. " SPMIE ,SPI match interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " SPIMODE ,SPI 8-bit or 16-bit mode" "8-bit,16-bit" bitfld.byte 0x01 5. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " MODFEN ,Master mode-fault function enable" "Disabled,Enabled" bitfld.byte 0x01 3. " BIDIROE ,Bidirectional mode output enable" "Disabled,Enabled" bitfld.byte 0x01 2. " RXDMAE ,Receive DMA enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " SPISWAI ,SPI stop in wait mode" "Not stopped,Stopped" bitfld.byte 0x01 0. " SPC0 ,SPI pin control 0" "Normal mode,Bidirectional mode" if ((((per.b(ad:0x40076000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x00)) group.byte 0x03++0x00 line.byte 0x00 "SPI1_C1,SPI Control Register 1" bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled" bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low" bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start" textline " " bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB" elif ((((per.b(ad:0x40076000+0x0B))&0x01)==0x00)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)) group.byte 0x03++0x00 line.byte 0x00 "SPI1_C1,SPI Control Register 1" bitfld.byte 0x00 7. " SPIE ,SPI receive buffer full interrupt and mode fault" "Disabled,Enabled" bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low" bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start" textline " " bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled" bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB" elif ((((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x00)) group.byte 0x03++0x00 line.byte 0x00 "SPI1_C1,SPI Control Register 1" bitfld.byte 0x00 7. " SPIE ,SPI receive FIFO full interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SPTIE ,SPI transmit FIFO empty interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low" bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start" textline " " bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB" elif ((((per.b(ad:0x40076000+0x0B))&0x01)==0x01)&&(((per.b(ad:0x40076000+0x03))&0x10)==0x10)) group.byte 0x03++0x00 line.byte 0x00 "SPI1_C1,SPI Control Register 1" bitfld.byte 0x00 7. " SPIE ,SPI receive FIFO full interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " SPE ,SPI system enable" "Disabled,Enabled" bitfld.byte 0x00 5. " SPTIE ,SPI transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.byte 0x00 3. " CPOL ,Clock polarity" "Active-high,Active-low" bitfld.byte 0x00 2. " CPHA ,Clock phase (Of the first cycle)" "Middle,Start" textline " " bitfld.byte 0x00 1. " SSOE ,Slave select output enable" "Disabled,Enabled" bitfld.byte 0x00 0. " LSBFE ,LSB first (Shifter direction)" "MSB,LSB" endif if (((per.b(ad:0x40076000+0x02))&0x40)==0x40) group.byte 0x04++0x03 line.byte 0x00 "SPI1_ML,SPI Match Register Low" line.byte 0x01 "SPI1_MH,SPI Match Register High" line.byte 0x02 "SPI1_DL,SPI Data Register Low" line.byte 0x03 "SPI1_DH,SPI Data Register High" else group.byte 0x04++0x00 line.byte 0x00 "SPI1_ML,SPI Match Register Low" group.byte 0x06++0x00 line.byte 0x00 "SPI1_DL,SPI Data Register Low" endif sif (cpuis("MKW01Z128*")) hgroup.byte 0x0A++0x00 hide.byte 0x00 "SPI1_CI,SPI Clear Interrupt" in group.byte 0x0B++0x00 line.byte 0x00 "SPI1_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" else if ("1"=="1") if (((per.b(ad:0x40076000+0x0B))&0x08)==0x00) rgroup.byte 0x0A++0x00 line.byte 0x00 "SPI1_CI,SPI Clear Interrupt" bitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error" bitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error" bitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error" textline " " bitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error" elif (((per.b(ad:0x40076000+0x0B))&0x08)==0x08) group.byte 0x0A++0x00 line.byte 0x00 "SPI1_CI,SPI Clear Interrupt" rbitfld.byte 0x00 7. " TXFERR ,Transmit FIFO error flag" "No error,Error" rbitfld.byte 0x00 6. " RXFERR ,Receive FIFO error flag" "No error,Error" rbitfld.byte 0x00 5. " TXFOF ,Transmit FIFO overflow flag" "No error,Error" textline " " rbitfld.byte 0x00 4. " RXFOF ,Receive FIFO overflow flag" "No error,Error" bitfld.byte 0x00 3. " TNEAREFCI ,Transmit FIFO nearly empty flag clear interrupt" "No effect,Clear" bitfld.byte 0x00 2. " RNFULLFCI ,Receive FIFO nearly full empty flag clear interrupt" "No effect,Clear" textline " " bitfld.byte 0x00 1. " SPTEFCI ,Transmit FIFO empty flag clear interrupt" "No effect,Clear" bitfld.byte 0x00 0. " SPRFCI ,Receive FIFO full flag clear interrupt" "No effect,Clear" endif sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x40076000+0x0B))&0x01)==0x01) group.byte 0x0B++0x00 line.byte 0x00 "SPI1_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" else group.byte 0x0B++0x00 line.byte 0x00 "SPI1_C3,SPI Control Register 3" rbitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" rbitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" rbitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " rbitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" endif else group.byte 0x0B++0x00 line.byte 0x00 "SPI1_C3,SPI Control Register 3" bitfld.byte 0x00 5. " TNEAREF_MARK ,Transmit FIFO nearly empty watermark" "16 bits or less,32 bits or less" bitfld.byte 0x00 4. " RNFULLF_MARK ,Receive FIFO nearly full watermark" "48 bits or more,32 bits or more" bitfld.byte 0x00 3. " INTCLR ,Interrupt clearing mechanism" "Clear flags,Write CI bits" textline " " bitfld.byte 0x00 2. " TNEARIEN ,Transmit FIFO nearly empty interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " RNFULLIEN ,Receive FIFO nearly full interrupt watermark" "Disabled,Enabled" bitfld.byte 0x00 0. " FIFOMODE ,FIFO mode enable" "Disabled,Enabled" endif endif endif width 0x0B tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" tree "MODULE 0" base ad:0x4006A000 width 16. tree "UART 0 Standard Features Registers" group.byte 0x00++0x01 line.byte 0x00 "UART0_BDH,UART Baud Rate Register High" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low" if (((per.b(ad:0x4006A000+0x03)&0x0C)==0x0C)) group.byte 0x02++0x00 line.byte 0x00 "UART0_C1,UART Control Register 1" bitfld.byte 0x00 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" else group.byte 0x02++0x00 line.byte 0x00 "UART0_C1,UART Control Register 1" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" endif group.byte 0x03++0x00 line.byte 0x00 "UART0_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART0_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x0 hide.byte 0x00 "UART0_D,UART Data Register" in group.byte 0x08++0x3 line.byte 0x00 "UART0_MA1,UART Match Address Register 1" line.byte 0x01 "UART0_MA2,UART Match Address Register 2" line.byte 0x02 "UART0_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART0_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART0_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x00 line.byte 0x00 "UART0_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 0 FIFO Registers" width 17. if (((per.b(ad:0x4006A000+0x03)&0x0C)==0x00))&&(((per.b(ad:0x4006A000+0x12)&0xC0)==0xC0)) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" if (((per.b(ad:0x4006A000+0x03)&0x08)==0x00)) group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006A000+0x03)&0x04)==0x00)) group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count" tree.end width 19. tree "UART 0 ISO7816 Registers" tree.end width 0x0B tree.end tree "MODULE 1" base ad:0x4006B000 width 16. tree "UART 1 Standard Features Registers" group.byte 0x00++0x01 line.byte 0x00 "UART1_BDH,UART Baud Rate Register High" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low" if (((per.b(ad:0x4006B000+0x03)&0x0C)==0x0C)) group.byte 0x02++0x00 line.byte 0x00 "UART1_C1,UART Control Register 1" bitfld.byte 0x00 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" else group.byte 0x02++0x00 line.byte 0x00 "UART1_C1,UART Control Register 1" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" endif group.byte 0x03++0x00 line.byte 0x00 "UART1_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART1_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x0 hide.byte 0x00 "UART1_D,UART Data Register" in group.byte 0x08++0x3 line.byte 0x00 "UART1_MA1,UART Match Address Register 1" line.byte 0x01 "UART1_MA2,UART Match Address Register 2" line.byte 0x02 "UART1_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART1_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART1_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x00 line.byte 0x00 "UART1_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 1 FIFO Registers" width 17. if (((per.b(ad:0x4006B000+0x03)&0x0C)==0x00))&&(((per.b(ad:0x4006B000+0x12)&0xC0)==0xC0)) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" if (((per.b(ad:0x4006B000+0x03)&0x08)==0x00)) group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006B000+0x03)&0x04)==0x00)) group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count" tree.end width 19. tree "UART 1 ISO7816 Registers" if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) group.byte 0x18++0x00 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" rbitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" rbitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" rbitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " rbitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" else group.byte 0x18++0x00 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" endif group.byte 0x19++0x01 line.byte 0x00 "UART1_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x00 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x01 "UART1_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x01 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x01 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.byte 0x01 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt" textline " " endif eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z128CLH5*") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" endif else if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" endif endif endif if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) rgroup.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.b(ad:0x4006B000+0x03)&0x08)==0x08)) if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else rgroup.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif else if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif endif textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) rgroup.byte 0x3A++0x03 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART1_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x03 "UART1_WP7816B_T0,UART 7816 Wait Parameter Register B" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in rgroup.byte 0x3C++0x03 line.byte 0x00 "UART1_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART1_WP7816B_T1,UART 7816 Wait Parameter Register B" line.byte 0x02 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) group.byte 0x3A++0x03 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART1_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x03 "UART1_WP7816B_T0,UART 7816 Wait Parameter Register B" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in group.byte 0x3C++0x03 line.byte 0x00 "UART1_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART1_WP7816B_T1,UART 7816 Wait Parameter Register B" line.byte 0x02 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif endif tree.end width 0x0B tree.end tree "MODULE 2" base ad:0x4006C000 width 16. tree "UART 2 Standard Features Registers" group.byte 0x00++0x01 line.byte 0x00 "UART2_BDH,UART Baud Rate Register High" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low" if (((per.b(ad:0x4006C000+0x03)&0x0C)==0x0C)) group.byte 0x02++0x00 line.byte 0x00 "UART2_C1,UART Control Register 1" bitfld.byte 0x00 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" else group.byte 0x02++0x00 line.byte 0x00 "UART2_C1,UART Control Register 1" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" endif group.byte 0x03++0x00 line.byte 0x00 "UART2_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART2_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART2_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x0 hide.byte 0x00 "UART2_D,UART Data Register" in group.byte 0x08++0x3 line.byte 0x00 "UART2_MA1,UART Match Address Register 1" line.byte 0x01 "UART2_MA2,UART Match Address Register 2" line.byte 0x02 "UART2_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART2_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART2_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x00 line.byte 0x00 "UART2_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 2 FIFO Registers" width 17. if (((per.b(ad:0x4006C000+0x03)&0x0C)==0x00))&&(((per.b(ad:0x4006C000+0x12)&0xC0)==0xC0)) group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART2_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART2_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" if (((per.b(ad:0x4006C000+0x03)&0x08)==0x00)) group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006C000+0x03)&0x04)==0x00)) group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count" tree.end width 19. tree "UART 2 ISO7816 Registers" tree.end width 0x0B tree.end tree "MODULE 3" base ad:0x4006D000 width 16. tree "UART 3 Standard Features Registers" group.byte 0x00++0x01 line.byte 0x00 "UART3_BDH,UART Baud Rate Register High" bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART3_BDL,UART Baud Rate Register Low" if (((per.b(ad:0x4006D000+0x03)&0x0C)==0x0C)) group.byte 0x02++0x00 line.byte 0x00 "UART3_C1,UART Control Register 1" bitfld.byte 0x00 7. " LOOPS ,Loop mode select" "Not selected,Selected" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" else group.byte 0x02++0x00 line.byte 0x00 "UART3_C1,UART Control Register 1" bitfld.byte 0x00 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x00 4. " M ,9-bit or 8-bit mode select" "Normal 8 bits+stop,Use 9 bits+stop" textline " " bitfld.byte 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.byte 0x00 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x00 1. " PE ,Parity enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " PT ,Parity type" "Even,Odd" endif group.byte 0x03++0x00 line.byte 0x00 "UART3_C2,UART Control Register 2" bitfld.byte 0x00 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x00 0. " SBK ,Send break" "Normal,Break" rgroup.byte 0x04++0x00 line.byte 0x00 "UART3_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" group.byte 0x05++0x01 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" line.byte 0x01 "UART3_C3,UART Control Register 3" rbitfld.byte 0x01 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x01 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x01 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x01 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x01 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x0 hide.byte 0x00 "UART3_D,UART Data Register" in group.byte 0x08++0x3 line.byte 0x00 "UART3_MA1,UART Match Address Register 1" line.byte 0x01 "UART3_MA2,UART Match Address Register 2" line.byte 0x02 "UART3_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x03 "UART3_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART3_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x00 line.byte 0x00 "UART3_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" tree.end tree "UART 3 FIFO Registers" width 17. if (((per.b(ad:0x4006D000+0x03)&0x0C)==0x00))&&(((per.b(ad:0x4006D000+0x12)&0xC0)==0xC0)) group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART3_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART3_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" if (((per.b(ad:0x4006D000+0x03)&0x08)==0x00)) group.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART3_TCFIFO,UART FIFO Transmit Count" if (((per.b(ad:0x4006D000+0x03)&0x04)==0x00)) group.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART3_RCFIFO,UART FIFO Receive Count" tree.end width 19. tree "UART 3 ISO7816 Registers" if (((per.b(ad:0x4006D000+0x18)&0x01)==0x01)) group.byte 0x18++0x00 line.byte 0x00 "UART3_C7816,UART 7816 Control Register" rbitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" rbitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" rbitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " rbitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" else group.byte 0x18++0x00 line.byte 0x00 "UART3_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" endif group.byte 0x19++0x01 line.byte 0x00 "UART3_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x00 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x01 "UART3_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x01 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x01 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.byte 0x01 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt" textline " " endif eventfld.byte 0x01 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x01 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z128CLH5*") if (((per.b(ad:0x4006D000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006D000+0x18))&0x02)==0x00) rgroup.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.b(ad:0x4006D000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006D000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006D000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" endif else if (((per.b(ad:0x4006D000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" endif endif endif if (((per.b(ad:0x4006D000+0x18)&0x01)==0x01)) rgroup.byte 0x1C++0x02 line.byte 0x00 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x1C++0x02 line.byte 0x00 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.b(ad:0x4006D000+0x03)&0x08)==0x08)) if (((per.b(ad:0x4006D000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else rgroup.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif else if (((per.b(ad:0x4006D000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif endif textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006D000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006D000+0x18))&0x2)==0x00) rgroup.byte 0x3A++0x03 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART3_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x03 "UART3_WP7816B_T0,UART 7816 Wait Parameter Register B" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in rgroup.byte 0x3C++0x03 line.byte 0x00 "UART3_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART3_WP7816B_T1,UART 7816 Wait Parameter Register B" line.byte 0x02 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else if (((per.b(ad:0x4006D000+0x18))&0x2)==0x00) group.byte 0x3A++0x03 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART3_WP7816A_T0,UART 7816 Wait Parameter Register A" line.byte 0x03 "UART3_WP7816B_T0,UART 7816 Wait Parameter Register B" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in group.byte 0x3C++0x03 line.byte 0x00 "UART3_WP7816A_T1,UART 7816 Wait Parameter Register A" line.byte 0x01 "UART3_WP7816B_T1,UART 7816 Wait Parameter Register B" line.byte 0x02 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif endif tree.end width 0x0B tree.end tree.end sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "Low-Power Universal Asynchronous Receiver/Transmitter (LPUART)" base ad:0x4002A000 width 7. if (((per.l(ad:0x4002A000+0x08))&0xC0000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" bitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4002A000+0x08))&0x80000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" bitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" elif (((per.l(ad:0x4002A000+0x08))&0x40000)==0x0) group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" else group.long 0x00++0x07 line.long 0x00 "BAUD,LPUART0 Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Normal,Automatic" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Normal,Automatic" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8 bit/9 bit,10 bit" newline rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " MATCFG ,Match configuration" "Address Match,Idle Match,Match On/Off,RWU Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Rising,Both" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 stop bit,2 stop bits" newline hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" line.long 0x04 "STAT,LPUART0 Status Register" eventfld.long 0x04 31. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.long 0x04 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not occurred,Occurred" rbitfld.long 0x04 29. " MSBF ,MSB first" "LSB first,MSB first" newline bitfld.long 0x04 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" rbitfld.long 0x04 27. " RWUID ,Receive wake up idle detect" "Not detected,Detected" rbitfld.long 0x04 26. " BRK13 ,Break character generation length" "10/11/12/13 bit,13/14/15/16 bit" newline bitfld.long 0x04 25. " LBKDE ,LIN break detection enable" "10/11/12/13 bit,11/12/14/15 bit" rbitfld.long 0x04 24. " RAF ,Receiver active flag" "Idle,Active" rbitfld.long 0x04 23. " TDRE ,Transmit data register empty flag" "Full,Empty" newline rbitfld.long 0x04 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x04 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x04 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x04 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x04 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x04 17. " FE ,Framing error flag" "No error,Error" newline eventfld.long 0x04 16. " PF ,Parity error flag" "No error,Error" eventfld.long 0x04 15. " MA1F ,Match 1 flag" "Not equal,Equal" eventfld.long 0x04 14. " MA2F ,Match 2 flag" "Not equal,Equal" endif if (((per.l(ad:0x4002A000+0x08))&0xC0000)==0x0) if ((per.b(ad:0x4002A000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline bitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" bitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline bitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif else if ((per.b(ad:0x4002A000+0x8)&0x80)==0x80) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 5. " RSRC ,Receiver source select" "Disconnected,Connected" rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" newline rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART0 Control Register" rbitfld.long 0x00 31. " R8T9 ,Receive bit 8 / transmit bit 9" "Low,High" rbitfld.long 0x00 30. " R9T8 ,Receive bit 9 / transmit bit 8" "Low,High" rbitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in Single-Wire mode" "Input,Output" newline rbitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" rbitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" rbitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal,Standby" newline rbitfld.long 0x00 16. " SBK ,Send break" "Normal,Send break" rbitfld.long 0x00 15. " MA1IE ,Match 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 14. " MA2IE ,Match 2 interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 8.--10. " IDLECFG ,Idle configuration" "1 char,2 chars,4 chars,8 chars,16 chars,32 chars,64 chars,128 chars" rbitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal,Loop" rbitfld.long 0x00 6. " DOZEEN ,Doze enable" "LPUART enabled,LPUART disabled" newline rbitfld.long 0x00 4. " M ,9-bit or 8-bit mode select" "8 bit,9 bit" rbitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" rbitfld.long 0x00 2. " ILT ,Idle line type select" "Start bit,Stop bit" newline rbitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" rbitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" endif endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART0 Data Register" in newline sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x4002A000)&0xC0000000)==0xC0000000)) rgroup.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif else group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART0 Match Address Register" hexmask.long.word 0x00 16.--25. 1. " MA2 ,Match address 2" hexmask.long.word 0x00 0.--9. 1. " MA1 ,Match address 1" endif group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART0 Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") newline hexmask.long.byte 0x00 8.--15. 1. " RTSWATER ,Receive RTS Configuration" endif newline bitfld.long 0x00 5. " TXCTSSRC ,Transmit CTS source" "LPUART_CTS,Inverted Receiver Match" newline bitfld.long 0x00 4. " TXCTSC ,Transmit CTS configuration" "At start,At idle" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Low,High" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((((per.l(ad:0x4002A000+0x08))&0xC0000)==0x00)&&(((per.l(ad:0x4002A000+0x18))&0x800000)==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART0 FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART0 FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive Buffer/FIFO Empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter Buffer Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver Buffer Underflow Flag" "No underfow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer Flush" "No effect,Flush" bitfld.long 0x00 10.--12. " RXIDEN ,Receiver Idle Empty Enable. Enable RDRF assertion due to partially filled FIFO when receiver is idle for defined number of characters" "Disabled,1,2,4,8,16,32,64" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " RXUFE ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TXFE ,Transmit FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" bitfld.long 0x00 3. " RXFE ,Receive FIFO Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer Depth (datawords)" "1,4,8,16,32,64,128,256" endif if (((per.l(ad:0x4002A000+0x08))&0x80000)==0x80000) rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART0 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART0 Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive Counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive Watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit Counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit Watermark" endif endif width 0x0B tree.end tree "MMCAU (Memory Mapped Cryptographic Acceleration Unit)" base ad:0xF0005000 width 6. group.long 0x00++0x03 line.long 0x00 "CASR,Status Register" rbitfld.long 0x00 28.--31. " VER ,CAU version" ",Initial CAU version,Second version(with SHA-256 algorithm),?..." bitfld.long 0x00 1. " DPE ,DES parity error" "No error,Error" bitfld.long 0x00 0. " IC ,Illegal command" "Not issued,Issued" group.long 0x01++0x03 line.long 0x00 "CAA,Accumulator" sif cpuis("MK24FN*") group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" else group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" group.long 0x8++0x03 line.long 0x00 "CA6,General Purpose Register" group.long 0x9++0x03 line.long 0x00 "CA7,General Purpose Register" group.long 0xA++0x03 line.long 0x00 "CA8,General Purpose Register" endif width 0x0B tree.end endif tree "CRC (Cyclic Redundancy Check)" base ad:0x40034000 width 7. if (((per.l(ad:0x40034000+0x08)&0x1000000)==0x1000000)) group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" else group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" endif group.long 0x04++0x07 line.long 0x00 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,High polynomial half-word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Low polynomial half-word" line.long 0x04 "CTRL,CRC Control Register" bitfld.long 0x04 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x04 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x04 26. " FXOR ,Complement read of CRC data register" "No XOR,Inverted/Complemented" bitfld.long 0x04 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x04 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" width 0x0B tree.end tree "RNGA (Random Number Generator Accelerator)" base ad:0x40029000 width 5. sif (cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) rgroup.long 0x00++0x03 line.long 0x00 "VER,RNGB Version ID Register" bitfld.long 0x00 28.--31. " TYPE ,Random number generator type" "RNGA,RNGB,RNGC,?..." hexmask.long.byte 0x00 8.--15. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,Minor version number" group.long 0x04++0x07 line.long 0x00 "CMD,RNGB Command Register" bitfld.long 0x00 6. " SR ,Software reset" "No reset,Reset" bitfld.long 0x00 5. " CE ,Clear error" "No clear,Clear" bitfld.long 0x00 4. " CI ,Clear interrupt" "No clear,Clear" newline bitfld.long 0x00 1. " GS ,Generate seed" "Disabled,Enabled" bitfld.long 0x00 0. " ST ,Self test" "Disabled,Enabled" line.long 0x04 "CR,RNGB Control Register" bitfld.long 0x04 6. " MASKERR ,Mask error interrupt" "Not masked,Masked" bitfld.long 0x04 5. " MASKDONE ,Mask done interrupt" "Not masked,Masked" bitfld.long 0x04 4. " AR ,Auto-reseed enable" "Disabled,Enabled" newline bitfld.long 0x04 0.--1. " FUFMOD ,FIFO underflow response mode" "Return all zeros and set RNG_ESR[FUFE],Return all zeros and set RNG_ESR[FUFE],Generate bus transfer error,Generate interrupt and return all zeros" rgroup.long 0x0C++0x0B line.long 0x00 "SR,RNGB Status Register" bitfld.long 0x00 31. " STATPF[7] ,Long run test pass/fail" "Passed,Failed" bitfld.long 0x00 30. " [6] ,Length 6+ run test pass/fail" "Passed,Failed" bitfld.long 0x00 29. " [5] ,Length 5 run test pass/fail" "Passed,Failed" newline bitfld.long 0x00 28. " [4] ,Length 4 run test pass/fail" "Passed,Failed" bitfld.long 0x00 27. " [3] ,Length 3 run test pass/fail" "Passed,Failed" bitfld.long 0x00 26. " [2] ,Length 2 run test pass/fail" "Passed,Failed" newline bitfld.long 0x00 25. " [1] ,Length 1 run test pass/fail" "Passed,Failed" bitfld.long 0x00 24. " [0] ,Mon-obit test pass/fail" "Passed,Failed" newline bitfld.long 0x00 23. " ST_PF[2] ,TRNG self test pass/fail" "Passed,Failed" bitfld.long 0x00 22. " [1] ,PRNG self test pass/fail" "Passed,Failed" bitfld.long 0x00 21. " [0] ,RESEED self test pass/fail" "Passed,Failed" newline bitfld.long 0x00 16. " ERR ,Error was detected in the RNGB" "No error,Error" bitfld.long 0x00 12.--15. " FIFO_SIZE ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FIFO_LVL ,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. " NSDN ,New seed done" "Not done,Done" bitfld.long 0x00 5. " SDN ,Seed done" "Not done,Done" bitfld.long 0x00 4. " STDN ,Self test done" "Not done,Done" newline bitfld.long 0x00 3. " RS ,Reseed needed" "Not needed,Needed" bitfld.long 0x00 2. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 1. " BUSY ,State of RNGB" "Not busy,Busy" line.long 0x04 "ESR,RNGB Error Status Register" bitfld.long 0x04 4. " FUFE ,FIFO underflow error" "Not occurred,Occurred" bitfld.long 0x04 3. " SATE ,Statistical test error" "Not occurred,Occurred" bitfld.long 0x04 2. " STE ,Self test error" "Not occurred,Occurred" newline bitfld.long 0x04 1. " OSCE ,Oscillator error" "Not occurred,Occurred" bitfld.long 0x04 0. " LFE ,Linear feedback shift register (LFSR) error" "Not occurred,Occurred" line.long 0x08 "OUT,RNGB Output FIFO" elif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("K26P169M180SF5RM")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") width 8. group.long 0x00++0x03 line.long 0x00 "CR,RNGA Control Register" bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " CLRI ,Clear interrupt" "No effect,Clear" bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 1. " HA ,High assurance enable" "Disabled,Enabled" bitfld.long 0x00 0. " GO ,Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SR,RNGA Status Register" hexmask.long.byte 0x00 16.--23. " OREG_SIZE ,Output register size" hexmask.long.byte 0x00 8.--15. " OREG_LVL ,Indicates the number of random-data words that are in OR[RANDOUT]" newline bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " ERRI ,Error interrupt" "Not occurred,Occurred" bitfld.long 0x00 2. " ORU ,Output register underflow" "No underflow,Underflow" newline bitfld.long 0x00 1. " LRS ,Last read status" "No underflow,Underflow" bitfld.long 0x00 0. " SECV ,Security violation" "Not occurred,Occurred" wgroup.long 0x08++0x03 line.long 0x00 "ER,RNGA Entropy Register" rgroup.long 0x0C++0x03 line.long 0x00 "OR,RNGA Output Register" else width 8. group.long 0x00++0x03 line.long 0x00 "CR,RNGA Control Register" bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " CLRI ,Clear interrupt" "No effect,Clear" bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 1. " HA ,High assurance enable" "Disabled,Enabled" bitfld.long 0x00 0. " GO ,Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled" "Disabled,Enabled" newline hgroup.long 0x04++0x03 hide.long 0x00 "SR,RNGA Status Register" in wgroup.long 0x08++0x03 line.long 0x00 "ER,RNGA Entropy Register" hgroup.long 0x0C++0x03 hide.long 0x00 "OR,RNGA Output Register" in endif width 0x0B tree.end sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "SLCD (LCD Controller)" base ad:0x40043000 width 5. sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") if (((per.l(ad:0x40043000))&0x80)==0x80) if (((per.l(ad:0x40043000))&0x800000)==0x000000) group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "2000pF,2000pF,8000pF,8000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/64,/256,/512" else textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" endif textline " " bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Disabled,Enabled" bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" else group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "8000pF,4000pF,2000pF,1000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/64,/256,/512" else textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" endif textline " " bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Disabled,Enabled" bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" rbitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" endif else if (((per.l(ad:0x40043000))&0x800000)==0x000000) group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "2000pF,2000pF,8000pF,8000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/64,/256,/512" else textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" endif textline " " bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Disabled,Enabled" bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" else group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "8000pF,4000pF,2000pF,1000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" textline " " sif !cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" sif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/64,/256,/512" else textline " " bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" endif textline " " bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Disabled,Enabled" bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" endif endif else if (((per.l(ad:0x40043000))&0x800000)==0x000000) group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "2000pF,2000pF,8000pF,8000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Enabled,Disabled" textline " " else bitfld.long 0x00 22. " HREFSEL ,High reference select " "Vireg = 1.0 for 3V glass,Vireg = 1.67 for 5V glass" textline " " bitfld.long 0x00 20.--21. " LADJ ,Load adjust (Adjust the resistor bias network for different LCD glass capacitance)" "2000pF,2000pF,8000pF,8000pF" textline " " bitfld.long 0x00 16.--17. " VSUPPLY ,Voltage supply control" "Vll2 internally from Vdd,Vll3 internally from Vdd,,Vll3 externally from Vdd/Vll1 internally from Vireg" textline " " bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" textline " " bitfld.long 0x00 9. " LCDWAIT ,LCD driver/charge pump/resistor bias network/voltage regulator stop while in wait mode" "Allowed,Not allowed" textline " " endif bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" else group.long 0x00++0x03 line.long 0x00 "GCR,LCD General Control Register" bitfld.long 0x00 31. " RVEN ,Regulated voltage enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " RVTRIM ,Regulated voltage trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " CPSEL ,Charge pump or resistor bias select" "Resistor network,Charge pump" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")) bitfld.long 0x00 21.--22. " LADJ ,Load adjust" "8000pF,4000pF,2000pF,1000pF" bitfld.long 0x00 17. " VSUPPLY ,Voltage supply control" "Int. Vdd,Ext. Vdd/Int. Vireg" bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" bitfld.long 0x00 9. " LCDDOZE ,LCD doze enable" "Enabled,Disabled" textline " " else bitfld.long 0x00 22. " HREFSEL ,High reference select " "Vireg = 1.0 for 3 V glass,Vireg =1.67 for 5V glass" textline " " bitfld.long 0x00 20.--21. " LADJ ,Load adjust (Adjust the clock source for the charge pump)" "8000pF,6000pF,4000pF,2000pF" textline " " bitfld.long 0x00 16.--17. " VSUPPLY ,Voltage supply control" "Vll2 internally from Vdd,Vll3 internally from Vdd,,Vll3 externally from Vdd/Vll1 internally from Vireg" textline " " bitfld.long 0x00 15. " LCDIEN ,LCD frame frequency interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " FDCIEN ,LCD fault detection complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " ALTDIV ,LCD alternate clock divider" "/1,/8,/64,/512" textline " " bitfld.long 0x00 9. " LCDWAIT ,LCD driver/charge pump/resistor bias network/and voltage regulator stop while in wait mode" "Allowed,Not allowed" textline " " endif bitfld.long 0x00 8. " LCDSTP ,LCD driver/charge pump/resistor bias network/and voltage regulator while in stop mode" "Allowed,Not allowed" bitfld.long 0x00 7. " LCDEN ,LCD driver enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SOURCE ,LCD clock source select" "Default,Alternate" bitfld.long 0x00 3.--5. " LCLK ,LCD clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DUTY ,LCD duty select" "1 BP,2 BP,3 BP,4 BP,5 BP,6 BP,7 BP,8 BP" endif endif textline " " width 6. group.long 0x04++0x0B line.long 0x00 "AR,LCD Auxiliary Register" sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) eventfld.long 0x00 15. " LCDIF ,LCD frame frequency interrupt flag" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 7. " BLINK ,Blink command" "Stop blinking,Start blinking" bitfld.long 0x00 6. " ALT ,Alternate display mode" "Normal,Alternate" bitfld.long 0x00 5. " BLANK ,Blank display mode" "Normal,Blank" textline " " bitfld.long 0x00 3. " BMODE ,Blink mode" "Blank,Alternate" bitfld.long 0x00 0.--2. " BRATE ,Blink-rate configuration" "0,1,2,3,4,5,6,7" line.long 0x04 "FDCR,LCD Fault Detect Control Register" bitfld.long 0x04 12.--14. " FDPRS ,Fault detect clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x04 9.--11. " FDSWW ,Fault detect sample window width" "4,8,16,32,64,128,256,512" bitfld.long 0x04 7. " FDEN ,Fault detect enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " FDBPEN ,Fault detect backplane enable" "Disabled,Enabled" textline " " sif ((cpuis("MKM34Z128CLL5"))||(cpuis("MKM33Z64CLL5"))||(cpuis("MKM33Z128CLL5"))||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,LCD_P39,LCD_P40,LCD_P41,LCD_P42,LCD_P43,?..." elif ((cpuis("MKM33Z128CLH5*"))||(cpuis("MKM33Z64CLH5"))||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,,,,,,,,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,,LCD_P27,LCD_P28,LCD_P29,LCD_P30,,,,,,,,LCD_P38,LCD_P39,LCD_P40,LCD_P41,LCD_P42,?..." elif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,,,,,,,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,,,,,,,,,,,,,,,LCD_P27,LCD_P28,LCD_P29,LCD_P30,?..." elif ((cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10")) bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,LCD_P39,LCD_P40,LCD_P41,LCD_P42,LCD_P43,LCD_P44,LCD_P45,LCD_P46,LCD_P47,?..." elif cpuis("MKM34Z256VLL7*") bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,LCD_P39,LCD_P40,LCD_P41,LCD_P42,LCD_P43,,,,,,,,,,,,,,,,,LCD_P60,LCD_P61,LCD_P62,LCD_P63" elif (cpuis("MKM34Z256VLQ7")) bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,LCD_P39,LCD_P40,LCD_P41,LCD_P42,LCD_P43,LCD_P44,LCD_P45,LCD_P46,LCD_P47,LCD_P48,LCD_P49,LCD_P50,LCD_P51,LCD_P52,LCD_P53,LCD_P54,LCD_P55,LCD_P56,LCD_P57,LCD_P58,LCD_P59,LCD_P60,LCD_P61,LCD_P62,LCD_P63" elif (cpu()=="MK40DN512ZVLL10")||cpuis("MK51DN512ZCLL10") bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,,,,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,,,,,LCD_P36,LCD_P37,LCD_P38,,LCD_P40,LCD_P41,LCD_P42,LCD_P43,LCD_P44,LCD_P45,LCD_P46,LCD_P47,?..." elif cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,,,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,,LCD_P40,LCD_P41,LCD_P42,LCD_P43,LCD_P44,LCD_P45,LCD_P46,LCD_P47,?..." elif cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "LCD_P0,LCD_P1,LCD_P2,LCD_P3,LCD_P4,LCD_P5,LCD_P6,LCD_P7,LCD_P8,LCD_P9,LCD_P10,LCD_P11,LCD_P12,LCD_P13,LCD_P14,LCD_P15,LCD_P16,LCD_P17,LCD_P18,LCD_P19,LCD_P20,LCD_P21,LCD_P22,LCD_P23,LCD_P24,LCD_P25,LCD_P26,LCD_P27,LCD_P28,LCD_P29,LCD_P30,LCD_P31,LCD_P32,LCD_P33,LCD_P34,LCD_P35,LCD_P36,LCD_P37,LCD_P38,,LCD_P40,LCD_P41,LCD_P42,LCD_P43,LCD_P44,LCD_P45,LCD_P46,LCD_P47,?..." else bitfld.long 0x04 0.--5. " FDPINID ,Fault detect pin ID" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15,P16,P17,P18,P19,P20,P21,P22,P23,P24,P25,P26,P27,P28,P29,P30,P31,P32,P33,P34,P35,P36,P37,P38,P39,P40,P41,P42,P43,P44,P45,P46,P47,P48,P49,P50,P51,P52,P53,P54,P55,P56,P57,P58,P59,P60,P61,P62,P63" endif line.long 0x08 "FDSR,LCD Fault Detect Status Register" eventfld.long 0x08 15. " FDCF ,Fault detection complete flag" "Not completed,Completed" hexmask.long.byte 0x08 0.--7. 1. " FDCNT ,Fault detect counter" textline " " width 14. sif ((cpuis("MKM34Z128CLL5"))||(cpuis("MKM33Z64CLL5"))||(cpuis("MKM33Z128CLL5"))||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) group.long 0x10++0x0F line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 31. " PEN_31 ,LCD pin 31" "Disabled,Enabled" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 26. " PEN_26 ,LCD pin 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" bitfld.long 0x00 20. " PEN_20 ,LCD pin 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PEN_19 ,LCD pin 19" "Disabled,Enabled" bitfld.long 0x00 18. " PEN_18 ,LCD pin 18" "Disabled,Enabled" bitfld.long 0x00 17. " PEN_17 ,LCD pin 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PEN_16 ,LCD pin 16" "Disabled,Enabled" bitfld.long 0x00 15. " PEN_15 ,LCD pin 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN_14 ,LCD pin 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN_6 ,LCD pin 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN_5 ,LCD pin 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEN_4 ,LCD pin 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" bitfld.long 0x04 11. " PEN_43 ,LCD pin 43" "Disabled,Enabled" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" bitfld.long 0x04 7. " PEN_39 ,LCD pin 39" "Disabled,Enabled" bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " PEN_37 ,LCD pin 37" "Disabled,Enabled" bitfld.long 0x04 4. " PEN_36 ,LCD pin 36" "Disabled,Enabled" bitfld.long 0x04 3. " PEN_35 ,LCD pin 35" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PEN_34 ,LCD pin 34" "Disabled,Enabled" bitfld.long 0x04 1. " PEN_33 ,LCD pin 33" "Disabled,Enabled" bitfld.long 0x04 0. " PEN_32 ,LCD pin 32" "Disabled,Enabled" line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 31. " BPEN_31 ,Back plane pin 31" "Front,Back" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" textline " " bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 26. " BPEN_26 ,Back plane pin 26" "Front,Back" textline " " bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" textline " " bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back Plane Pin 21" "Front,Back" bitfld.long 0x08 20. " BPEN_20 ,Back Plane Pin 20" "Front,Back" textline " " bitfld.long 0x08 19. " BPEN_19 ,Back plane pin 19" "Front,Back" bitfld.long 0x08 18. " BPEN_18 ,Back plane pin 18" "Front,Back" bitfld.long 0x08 17. " BPEN_17 ,Back plane pin 17" "Front,Back" textline " " bitfld.long 0x08 16. " BPEN_16 ,Back plane pin 16" "Front,Back" bitfld.long 0x08 15. " BPEN_15 ,Back plane pin 15" "Front,Back" bitfld.long 0x08 14. " BPEN_14 ,Back plane pin 14" "Front,Back" textline " " bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" textline " " bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" bitfld.long 0x08 6. " BPEN_6 ,Back plane pin 6" "Front,Back" bitfld.long 0x08 5. " BPEN_5 ,Back plane pin 5" "Front,Back" textline " " bitfld.long 0x08 4. " BPEN_4 ,Back plane pin 4" "Front,Back" bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" textline " " bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" bitfld.long 0x0C 11. " BPEN_43 ,Back plane pin 43" "Front,Back" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" textline " " bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" bitfld.long 0x0C 7. " BPEN_39 ,Back plane pin 39" "Front,Back" bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" textline " " bitfld.long 0x0C 5. " BPEN_37 ,Back plane pin 37" "Front,Back" bitfld.long 0x0C 4. " BPEN_36 ,Back plane pin 36" "Front,Back" bitfld.long 0x0C 3. " BPEN_35 ,Back plane pin 35" "Front,Back" textline " " bitfld.long 0x0C 2. " BPEN_34 ,Back plane pin 34" "Front,Back" bitfld.long 0x0C 1. " BPEN_33 ,Back plane pin 33" "Front,Back" bitfld.long 0x0C 0. " BPEN_32 ,Back plane pin 32" "Front,Back" textline " " sif cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*") group.long 0x20++0x2B line.long 0x00 "LCD_WF3TO0,LCD Waveform Register" bitfld.long 0x00 31. " WF3[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF2[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF1[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF0[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF7TO4,LCD Waveform Register" bitfld.long 0x04 31. " WF7[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 23. " WF6[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF5[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF4[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x08 "LCD_WF11TO8,LCD Waveform Register" bitfld.long 0x08 31. " WF11[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 23. " WF10[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 15. " WF9[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 7. " WF8[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x0C "LCD_WF15TO12,LCD Waveform Register" bitfld.long 0x0C 31. " WF15[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 23. " WF14[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 15. " WF13[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 7. " WF12[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x0C 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x0C 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x10 "LCD_WF19TO16,LCD Waveform Register" bitfld.long 0x10 31. " WF19[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 23. " WF18[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 15. " WF17[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 7. " WF16[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x14 "LCD_WF23TO20,LCD Waveform Register" bitfld.long 0x14 31. " WF23[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 23. " WF22[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 15. " WF21[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 7. " WF20[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x18 "LCD_WF27TO24,LCD Waveform Register" bitfld.long 0x18 31. " WF27[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 23. " WF26[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 15. " WF25[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 7. " WF24[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x1C "LCD_WF31TO28,LCD Waveform Register" bitfld.long 0x1C 31. " WF31[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 23. " WF30[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 15. " WF29[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 7. " WF28[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x20 "LCD_WF35TO32,LCD Waveform Register" bitfld.long 0x20 31. " WF35[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 23. " WF34[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 15. " WF33[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 7. " WF32[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x24 "LCD_WF39TO36,LCD Waveform Register" bitfld.long 0x24 31. " WF39[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 23. " WF38[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 15. " WF37[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 7. " WF36[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x28 "LCD_WF43TO40,LCD Waveform Register" bitfld.long 0x28 31. " WF43[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 23. " WF42[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 15. " WF41[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 7. " WF40[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " else group.long 0x20++0x2B line.long 0x00 "LCD_WF3TO0,LCD Waveform Register" hexmask.long.byte 0x00 24.--31. 1. " WF3 ,Waveform pin 3" hexmask.long.byte 0x00 16.--23. 1. " WF2 ,Waveform pin 2" hexmask.long.byte 0x00 8.--15. 1. " WF1 ,Waveform pin 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " WF0 ,Waveform pin 0" line.long 0x04 "LCD_WF7TO4,LCD Waveform Register" hexmask.long.byte 0x04 24.--31. 1. " WF7 ,Waveform pin 7" hexmask.long.byte 0x04 16.--23. 1. " WF6 ,Waveform pin 6" hexmask.long.byte 0x04 8.--15. 1. " WF5 ,Waveform pin 5" textline " " hexmask.long.byte 0x04 0.--7. 1. " WF4 ,Waveform pin 4" line.long 0x08 "LCD_WF11TO8,LCD Waveform Register" hexmask.long.byte 0x08 24.--31. 1. " WF11 ,Waveform pin 11" hexmask.long.byte 0x08 16.--23. 1. " WF10 ,Waveform pin 10" hexmask.long.byte 0x08 8.--15. 1. " WF9 ,Waveform pin 9" textline " " hexmask.long.byte 0x08 0.--7. 1. " WF8 ,Waveform pin 8" line.long 0x0C "LCD_WF15TO12,LCD Waveform Register" hexmask.long.byte 0x0C 24.--31. 1. " WF15 ,Waveform pin 15" hexmask.long.byte 0x0C 16.--23. 1. " WF14 ,Waveform pin 14" hexmask.long.byte 0x0C 8.--15. 1. " WF13 ,Waveform pin 13" textline " " hexmask.long.byte 0x0C 0.--7. 1. " WF12 ,Waveform pin 12" line.long 0x10 "LCD_WF19TO16,LCD Waveform Register" hexmask.long.byte 0x10 24.--31. 1. " WF19 ,Waveform pin 19" hexmask.long.byte 0x10 16.--23. 1. " WF18 ,Waveform pin 18" hexmask.long.byte 0x10 8.--15. 1. " WF17 ,Waveform pin 17" textline " " hexmask.long.byte 0x10 0.--7. 1. " WF16 ,Waveform pin 16" line.long 0x14 "LCD_WF23TO20,LCD Waveform Register" hexmask.long.byte 0x14 24.--31. 1. " WF23 ,Waveform pin 23" hexmask.long.byte 0x14 16.--23. 1. " WF22 ,Waveform pin 22" hexmask.long.byte 0x14 8.--15. 1. " WF21 ,Waveform pin 21" textline " " hexmask.long.byte 0x14 0.--7. 1. " WF20 ,Waveform pin 20" line.long 0x18 "LCD_WF27TO24,LCD Waveform Register" hexmask.long.byte 0x18 24.--31. 1. " WF27 ,Waveform pin 27" hexmask.long.byte 0x18 16.--23. 1. " WF26 ,Waveform pin 26" hexmask.long.byte 0x18 8.--15. 1. " WF25 ,Waveform pin 25" textline " " hexmask.long.byte 0x18 0.--7. 1. " WF24 ,Waveform pin 24" line.long 0x1C "LCD_WF31TO28,LCD Waveform Register" hexmask.long.byte 0x1C 24.--31. 1. " WF31 ,Waveform pin 31" hexmask.long.byte 0x1C 16.--23. 1. " WF30 ,Waveform pin 30" hexmask.long.byte 0x1C 8.--15. 1. " WF29 ,Waveform pin 29" textline " " hexmask.long.byte 0x1C 0.--7. 1. " WF28 ,Waveform pin 28" line.long 0x20 "LCD_WF35TO32,LCD Waveform Register" hexmask.long.byte 0x20 24.--31. 1. " WF35 ,Waveform pin 35" hexmask.long.byte 0x20 16.--23. 1. " WF34 ,Waveform pin 34" hexmask.long.byte 0x20 8.--15. 1. " WF33 ,Waveform pin 33" textline " " hexmask.long.byte 0x20 0.--7. 1. " WF32 ,Waveform pin 32" line.long 0x24 "LCD_WF39TO36,LCD Waveform Register" hexmask.long.byte 0x24 24.--31. 1. " WF39 ,Waveform pin 39" hexmask.long.byte 0x24 16.--23. 1. " WF38 ,Waveform pin 38" hexmask.long.byte 0x24 8.--15. 1. " WF37 ,Waveform pin 37" textline " " hexmask.long.byte 0x24 0.--7. 1. " WF36 ,Waveform pin 36" line.long 0x28 "LCD_WF43TO40,LCD Waveform Register" hexmask.long.byte 0x28 24.--31. 1. " WF43 ,Waveform pin 43" hexmask.long.byte 0x28 16.--23. 1. " WF42 ,Waveform pin 42" hexmask.long.byte 0x28 8.--15. 1. " WF41 ,Waveform pin 41" textline " " hexmask.long.byte 0x28 0.--7. 1. " WF40 ,Waveform pin 40" endif elif ((cpuis("MKM33Z128CLH5*"))||(cpuis("MKM33Z64CLH5"))) group.long 0x10++0x33 line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN_6 ,LCD pin 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN_5 ,LCD pin 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEN_4 ,LCD pin 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " PEN_39 ,LCD pin 39" "Disabled,Enabled" bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" textline " " bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" textline " " bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back plane pin 21" "Front,Back" textline " " bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" textline " " bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" bitfld.long 0x08 6. " BPEN_6 ,Back plane pin 6" "Front,Back" bitfld.long 0x08 5. " BPEN_5 ,Back plane pin 5" "Front,Back" textline " " bitfld.long 0x08 4. " BPEN_4 ,Back plane pin 4" "Front,Back" bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" textline " " bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" textline " " bitfld.long 0x0C 7. " BPEN_39 ,Back plane pin 39" "Front,Back" bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" line.long 0x10 "LCD_WF3TO0,LCD Waveform Register" hexmask.long.byte 0x10 24.--31. 1. " WF3 ,Waveform pin 3" hexmask.long.byte 0x10 16.--23. 1. " WF2 ,Waveform pin 2" hexmask.long.byte 0x10 8.--15. 1. " WF1 ,Waveform pin 1" textline " " hexmask.long.byte 0x10 0.--7. 1. " WF0 ,Waveform pin 0" line.long 0x14 "LCD_WF7TO4,LCD Waveform Register" hexmask.long.byte 0x14 24.--31. 1. " WF7 ,Waveform pin 7" hexmask.long.byte 0x14 16.--23. 1. " WF6 ,Waveform pin 6" hexmask.long.byte 0x14 8.--15. 1. " WF5 ,Waveform pin 5" textline " " hexmask.long.byte 0x14 0.--7. 1. " WF4 ,Waveform pin 4" line.long 0x18 "LCD_WF11TO8,LCD Waveform Register" hexmask.long.byte 0x18 24.--31. 1. " WF11 ,Waveform pin 11" hexmask.long.byte 0x18 16.--23. 1. " WF10 ,Waveform pin 10" hexmask.long.byte 0x18 8.--15. 1. " WF9 ,Waveform pin 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " WF8 ,Waveform pin 8" line.long 0x1C "LCD_WF15TO12,LCD Waveform Register" hexmask.long.byte 0x1C 8.--15. 1. " WF13 ,Waveform pin 13" hexmask.long.byte 0x1C 0.--7. 1. " WF12 ,Waveform pin 12" line.long 0x20 "LCD_WF23TO20,LCD Waveform Register" hexmask.long.byte 0x20 24.--31. 1. " WF23 ,Waveform pin 23" hexmask.long.byte 0x20 16.--23. 1. " WF22 ,Waveform pin 22" hexmask.long.byte 0x20 8.--15. 1. " WF21 ,Waveform pin 21" line.long 0x24 "LCD_WF27TO24,LCD Waveform Register" hexmask.long.byte 0x24 24.--31. 1. " WF27 ,Waveform pin 27" hexmask.long.byte 0x24 8.--15. 1. " WF25 ,Waveform pin 25" hexmask.long.byte 0x24 0.--7. 1. " WF24 ,Waveform pin 24" line.long 0x28 "LCD_WF31TO28,LCD Waveform Register" hexmask.long.byte 0x28 16.--23. 1. " WF30 ,Waveform pin 30" hexmask.long.byte 0x28 8.--15. 1. " WF29 ,Waveform pin 29" hexmask.long.byte 0x28 0.--7. 1. " WF28 ,Waveform pin 28" line.long 0x2C "LCD_WF39TO36,LCD Waveform Register" hexmask.long.byte 0x2C 24.--31. 1. " WF39 ,Waveform pin 39" hexmask.long.byte 0x2C 16.--23. 1. " WF38 ,Waveform pin 38" line.long 0x30 "LCD_WF43TO40,LCD Waveform Register" hexmask.long.byte 0x30 16.--23. 1. " WF42 ,Waveform pin 42" hexmask.long.byte 0x30 8.--15. 1. " WF41 ,Waveform pin 41" hexmask.long.byte 0x30 0.--7. 1. " WF40 ,Waveform pin 40" elif (cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) group.long 0x10++0x1F line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN_6 ,LCD pin 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN_5 ,LCD pin 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEN_4 ,LCD pin 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " PEN_39 ,LCD pin 39" "Disabled,Enabled" bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" textline " " bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" textline " " bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back plane pin 21" "Front,Back" textline " " bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" textline " " bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" bitfld.long 0x08 6. " BPEN_6 ,Back plane pin 6" "Front,Back" bitfld.long 0x08 5. " BPEN_5 ,Back plane pin 5" "Front,Back" textline " " bitfld.long 0x08 4. " BPEN_4 ,Back plane pin 4" "Front,Back" bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" textline " " bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" textline " " bitfld.long 0x0C 7. " BPEN_39 ,Back plane pin 39" "Front,Back" bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" textline " " line.long 0x10 "LCD_WF3TO0,LCD Waveform Register" bitfld.long 0x10 31. " WF3[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 23. " WF2[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 15. " WF1[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 7. " WF0[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x14 "LCD_WF7TO4,LCD Waveform Register" bitfld.long 0x14 31. " WF7[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 23. " WF6[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 15. " WF5[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 7. " WF4[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x18 "LCD_WF11TO8,LCD Waveform Register" bitfld.long 0x18 31. " WF11[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 23. " WF10[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 15. " WF9[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 7. " WF8[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x1C "LCD_WF15TO12,LCD Waveform Register" bitfld.long 0x1C 15. " WF13[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 7. " WF12[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x34++0x0B line.long 0x00 "LCD_WF23TO20,LCD Waveform Register" bitfld.long 0x00 31. " WF23[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF22[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF21[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF27TO24,LCD Waveform Register" bitfld.long 0x04 31. " WF27[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF25[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF24[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x08 "LCD_WF31TO28,LCD Waveform Register" bitfld.long 0x08 23. " WF30[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 15. " WF29[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 7. " WF28[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x44++0x07 line.long 0x00 "LCD_WF39TO36,LCD Waveform Register" bitfld.long 0x00 31. " WF39[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF38[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF43TO40,LCD Waveform Register" bitfld.long 0x04 23. " WF42[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF41[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF40[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " elif (cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) group.long 0x10++0x03 line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x00 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x00 29. " BPEN_29 ,Back plane pin 29" "Front,Back" bitfld.long 0x00 28. " BPEN_28 ,Back plane pin 28" "Front,Back" textline " " bitfld.long 0x00 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x00 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x00 11. " BPEN_11 ,Back plane pin 11" "Front,Back" textline " " bitfld.long 0x00 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x00 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x00 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x00 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x00 0. " BPEN_0 ,Back plane pin 0" "Front,Back" textline " " group.long 0x20++0x03 line.long 0x00 "LCD_WF3TO0,LCD Waveform Register" bitfld.long 0x00 15. " WF1[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF0[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x28++0x07 line.long 0x00 "LCD_WF11TO8,LCD Waveform Register" bitfld.long 0x00 31. " WF11[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF10[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF9[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF8[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF15TO12,LCD Waveform Register" bitfld.long 0x04 7. " WF12[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x38++0x07 line.long 0x00 "LCD_WF27TO24,LCD Waveform Register" bitfld.long 0x00 31. " WF27[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF31TO28,LCD Waveform Register" bitfld.long 0x04 23. " WF30[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF29[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF28[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " elif (cpuis("MKM34Z256VLQ7")||cpuis("MKM34Z256VLL7*")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) group.long 0x10++0x2F line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 31. " PEN_31 ,LCD pin 31" "Disabled,Enabled" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 26. " PEN_26 ,LCD pin 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" bitfld.long 0x00 20. " PEN_20 ,LCD pin 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PEN_19 ,LCD pin 19" "Disabled,Enabled" bitfld.long 0x00 18. " PEN_18 ,LCD pin 18" "Disabled,Enabled" bitfld.long 0x00 17. " PEN_17 ,LCD pin 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PEN_16 ,LCD pin 16" "Disabled,Enabled" bitfld.long 0x00 15. " PEN_15 ,LCD pin 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN_14 ,LCD pin 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x00 6. " PEN_6 ,LCD pin 6" "Disabled,Enabled" textline " " sif !cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x00 5. " PEN_5 ,LCD pin 5" "Disabled,Enabled" bitfld.long 0x00 4. " PEN_4 ,LCD pin 4" "Disabled,Enabled" textline " " endif endif bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x04 31. " PEN_63 ,LCD pin 63" "Disabled,Enabled" bitfld.long 0x04 30. " PEN_62 ,LCD pin 62" "Disabled,Enabled" bitfld.long 0x04 29. " PEN_61 ,LCD pin 61" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " PEN_60 ,LCD pin 60" "Disabled,Enabled" textline " " endif sif !cpuis("MKM34Z256VLL7*") sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x04 27. " PEN_59 ,LCD pin 59" "Disabled,Enabled" bitfld.long 0x04 26. " PEN_58 ,LCD pin 58" "Disabled,Enabled" bitfld.long 0x04 25. " PEN_57 ,LCD pin 57" "Disabled,Enabled" textline " " bitfld.long 0x04 24. " PEN_56 ,LCD pin 56" "Disabled,Enabled" bitfld.long 0x04 23. " PEN_55 ,LCD pin 55" "Disabled,Enabled" bitfld.long 0x04 22. " PEN_54 ,LCD pin 54" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " PEN_53 ,LCD pin 53" "Disabled,Enabled" bitfld.long 0x04 20. " PEN_52 ,LCD pin 52" "Disabled,Enabled" bitfld.long 0x04 19. " PEN_51 ,LCD pin 51" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " PEN_50 ,LCD pin 50" "Disabled,Enabled" bitfld.long 0x04 17. " PEN_49 ,LCD pin 49" "Disabled,Enabled" bitfld.long 0x04 16. " PEN_48 ,LCD pin 48" "Disabled,Enabled" textline " " endif bitfld.long 0x04 15. " PEN_47 ,LCD pin 47" "Disabled,Enabled" bitfld.long 0x04 14. " PEN_46 ,LCD pin 46" "Disabled,Enabled" bitfld.long 0x04 13. " PEN_45 ,LCD pin 45" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " PEN_44 ,LCD pin 44" "Disabled,Enabled" textline " " endif bitfld.long 0x04 11. " PEN_43 ,LCD pin 43" "Disabled,Enabled" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x04 7. " PEN_39 ,LCD pin 39" "Disabled,Enabled" textline " " endif bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" bitfld.long 0x04 5. " PEN_37 ,LCD pin 37" "Disabled,Enabled" bitfld.long 0x04 4. " PEN_36 ,LCD pin 36" "Disabled,Enabled" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x04 3. " PEN_35 ,LCD pin 35" "Disabled,Enabled" bitfld.long 0x04 2. " PEN_34 ,LCD pin 34" "Disabled,Enabled" bitfld.long 0x04 1. " PEN_33 ,LCD pin 33" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " PEN_32 ,LCD pin 32" "Disabled,Enabled" endif line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 31. " BPEN_31 ,Back plane pin 31" "Front,Back" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" textline " " bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 26. " BPEN_26 ,Back plane pin 26" "Front,Back" textline " " bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" textline " " bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back plane pin 21" "Front,Back" bitfld.long 0x08 20. " BPEN_20 ,Back plane pin 20" "Front,Back" textline " " bitfld.long 0x08 19. " BPEN_19 ,Back plane pin 19" "Front,Back" bitfld.long 0x08 18. " BPEN_18 ,Back plane pin 18" "Front,Back" bitfld.long 0x08 17. " BPEN_17 ,Back plane pin 17" "Front,Back" textline " " bitfld.long 0x08 16. " BPEN_16 ,Back plane pin 16" "Front,Back" bitfld.long 0x08 15. " BPEN_15 ,Back plane pin 15" "Front,Back" bitfld.long 0x08 14. " BPEN_14 ,Back plane pin 14" "Front,Back" textline " " bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" textline " " bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x08 6. " BPEN_6 ,Back plane pin 6" "Front,Back" textline " " sif !cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x08 5. " BPEN_5 ,Back plane pin 5" "Front,Back" bitfld.long 0x08 4. " BPEN_4 ,Back plane pin 4" "Front,Back" textline " " endif endif bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" textline " " bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x0C 31. " BPEN_63 ,Back plane pin 63" "Front,Back" bitfld.long 0x0C 30. " BPEN_62 ,Back plane pin 62" "Front,Back" bitfld.long 0x0C 29. " BPEN_61 ,Back plane pin 61" "Front,Back" textline " " bitfld.long 0x0C 28. " BPEN_60 ,Back plane pin 60" "Front,Back" textline " " endif sif !cpuis("MKM34Z256VLL7*") sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x0C 27. " BPEN_59 ,Back plane pin 59" "Front,Back" bitfld.long 0x0C 26. " BPEN_58 ,Back plane pin 58" "Front,Back" bitfld.long 0x0C 25. " BPEN_57 ,Back plane pin 57" "Front,Back" textline " " bitfld.long 0x0C 24. " BPEN_56 ,Back plane pin 56" "Front,Back" bitfld.long 0x0C 23. " BPEN_55 ,Back plane pin 55" "Front,Back" bitfld.long 0x0C 22. " BPEN_54 ,Back plane pin 54" "Front,Back" textline " " bitfld.long 0x0C 21. " BPEN_53 ,Back plane pin 53" "Front,Back" bitfld.long 0x0C 20. " BPEN_52 ,Back plane pin 52" "Front,Back" bitfld.long 0x0C 19. " BPEN_51 ,Back plane pin 51" "Front,Back" textline " " bitfld.long 0x0C 18. " BPEN_50 ,Back plane pin 50" "Front,Back" bitfld.long 0x0C 17. " BPEN_49 ,Back plane pin 49" "Front,Back" bitfld.long 0x0C 16. " BPEN_48 ,Back plane pin 48" "Front,Back" textline " " endif bitfld.long 0x0C 15. " BPEN_47 ,Back plane pin 47" "Front,Back" bitfld.long 0x0C 14. " BPEN_46 ,Back plane pin 46" "Front,Back" bitfld.long 0x0C 13. " BPEN_45 ,Back plane pin 45" "Front,Back" textline " " bitfld.long 0x0C 12. " BPEN_44 ,Back plane pin 44" "Front,Back" textline " " endif bitfld.long 0x0C 11. " BPEN_43 ,Back plane pin 43" "Front,Back" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" textline " " bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x0C 7. " BPEN_39 ,Back plane pin 39" "Front,Back" textline " " endif bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" bitfld.long 0x0C 5. " BPEN_37 ,Back plane pin 37" "Front,Back" bitfld.long 0x0C 4. " BPEN_36 ,Back plane pin 36" "Front,Back" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x0C 3. " BPEN_35 ,Back plane pin 35" "Front,Back" bitfld.long 0x0C 2. " BPEN_34 ,Back plane pin 34" "Front,Back" bitfld.long 0x0C 1. " BPEN_33 ,Back plane pin 33" "Front,Back" textline " " bitfld.long 0x0C 0. " BPEN_32 ,Back plane pin 32" "Front,Back" endif line.long 0x10 "LCD_WF3TO0,LCD Waveform Register" bitfld.long 0x10 31. " WF3[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 23. " WF2[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 15. " WF1[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 7. " WF0[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x10 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x10 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x14 "LCD_WF7TO4,LCD Waveform Register" bitfld.long 0x14 31. " WF7[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x14 23. " WF6[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " sif !cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") bitfld.long 0x14 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 15. " WF5[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 7. " WF4[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x14 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x14 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" endif endif line.long 0x18 "LCD_WF11TO8,LCD Waveform Register" bitfld.long 0x18 31. " WF11[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 23. " WF10[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 15. " WF9[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 7. " WF8[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x18 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x18 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x1C "LCD_WF15TO12,LCD Waveform Register" bitfld.long 0x1C 31. " WF15[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 23. " WF14[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 15. " WF13[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 7. " WF12[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x1C 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x1C 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x20 "LCD_WF19TO16,LCD Waveform Register" bitfld.long 0x20 31. " WF19[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 23. " WF18[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 15. " WF17[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 7. " WF16[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x20 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x20 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x24 "LCD_WF23TO20,LCD Waveform Register" bitfld.long 0x24 31. " WF23[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 23. " WF22[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 15. " WF21[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 7. " WF20[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x24 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x24 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x28 "LCD_WF27TO24,LCD Waveform Register" bitfld.long 0x28 31. " WF27[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 23. " WF26[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 15. " WF25[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 7. " WF24[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x28 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x28 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x2C "LCD_WF31TO28,LCD Waveform Register" bitfld.long 0x2C 31. " WF31[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 23. " WF30[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 15. " WF29[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 7. " WF28[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x2C 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x2C 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" sif !cpuis("MK51DN512ZCLL10") group.long 0x40++0x03 line.long 0x00 "LCD_WF35TO32,LCD Waveform Register" bitfld.long 0x00 31. " WF35[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF34[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF33[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF32[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" endif group.long 0x44++0x07 line.long 0x00 "LCD_WF39TO36,LCD Waveform Register" sif !cpuis("MK51DN512ZCLL10") bitfld.long 0x00 31. " WF39[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " endif bitfld.long 0x00 23. " WF38[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF37[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF36[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF43TO40,LCD Waveform Register" bitfld.long 0x04 31. " WF43[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 23. " WF42[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF41[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF40[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" sif !cpuis("MKM34Z256VLL7*") group.long 0x4C++0x03 line.long 0x00 "LCD_WF47TO44,LCD Waveform Register" bitfld.long 0x00 31. " WF47[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF46[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF45[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF44[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10") group.long 0x50++0x0B line.long 0x00 "LCD_WF51TO48,LCD Waveform Register" bitfld.long 0x00 31. " WF51[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF50[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF49[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF48[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x04 "LCD_WF55TO52,LCD Waveform Register" bitfld.long 0x04 31. " WF55[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 23. " WF54[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 15. " WF53[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 7. " WF52[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x04 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x04 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" line.long 0x08 "LCD_WF59TO56,LCD Waveform Register" bitfld.long 0x08 31. " WF59[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 23. " WF58[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 15. " WF57[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 7. " WF56[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x08 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x08 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" endif endif sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10") group.long 0x5C++0x03 line.long 0x00 "LCD_WF59TO56,LCD Waveform Register" bitfld.long 0x00 31. " WF63[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 28. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 27. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 25. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 23. " WF62[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 22. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 16. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 15. " WF61[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 13. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 11. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 10. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF60[7] ,Segment H backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " [6] ,Segment G backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " [5] ,Segment F backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 4. " [4] ,Segment E backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 3. " [3] ,Segment D backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " [2] ,Segment C backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 1. " [1] ,Segment B backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " [0] ,Segment A backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " endif elif (cpu()=="MK40DN512ZVLQ10")||(cpu()=="MK40DN512ZVMD10")||(cpu()=="MK40DX128ZVLQ10")||(cpu()=="MK40DX256ZVLQ10")||(cpu()=="MK40DX256ZVMD10") group.long 0x10++0x3F line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 31. " PEN_31 ,LCD pin 31" "Disabled,Enabled" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 26. " PEN_26 ,LCD pin 26" "Disabled,Enabled" bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" bitfld.long 0x00 20. " PEN_20 ,LCD pin 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PEN_19 ,LCD pin 19" "Disabled,Enabled" bitfld.long 0x00 18. " PEN_18 ,LCD pin 18" "Disabled,Enabled" bitfld.long 0x00 17. " PEN_17 ,LCD pin 17" "Disabled,Enabled" bitfld.long 0x00 16. " PEN_16 ,LCD pin 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " PEN_15 ,LCD pin 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN_14 ,LCD pin 14" "Disabled,Enabled" bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN_6 ,LCD pin 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN_5 ,LCD pin 5" "Disabled,Enabled" bitfld.long 0x00 4. " PEN_4 ,LCD pin 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" bitfld.long 0x04 15. " PEN_47 ,LCD pin 47" "Disabled,Enabled" bitfld.long 0x04 14. " PEN_46 ,LCD pin 46" "Disabled,Enabled" bitfld.long 0x04 13. " PEN_45 ,LCD pin 45" "Disabled,Enabled" bitfld.long 0x04 12. " PEN_44 ,LCD pin 44" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " PEN_43 ,LCD pin 43" "Disabled,Enabled" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" bitfld.long 0x04 5. " PEN_37 ,LCD pin 37" "Disabled,Enabled" bitfld.long 0x04 4. " PEN_36 ,LCD pin 36" "Disabled,Enabled" bitfld.long 0x04 3. " PEN_35 ,LCD pin 35" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " PEN_34 ,LCD pin 34" "Disabled,Enabled" bitfld.long 0x04 1. " PEN_33 ,LCD pin 33" "Disabled,Enabled" bitfld.long 0x04 0. " PEN_32 ,LCD pin 32" "Disabled,Enabled" line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 31. " BPEN_31 ,Back plane pin 31" "Front,Back" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" textline " " bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 26. " BPEN_26 ,Back plane pin 26" "Front,Back" bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" textline " " bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back plane pin 21" "Front,Back" bitfld.long 0x08 20. " BPEN_20 ,Back plane pin 20" "Front,Back" textline " " bitfld.long 0x08 19. " BPEN_19 ,Back plane pin 19" "Front,Back" bitfld.long 0x08 18. " BPEN_18 ,Back plane pin 18" "Front,Back" bitfld.long 0x08 17. " BPEN_17 ,Back plane pin 17" "Front,Back" bitfld.long 0x08 16. " BPEN_16 ,Back plane pin 16" "Front,Back" textline " " bitfld.long 0x08 15. " BPEN_15 ,Back plane pin 15" "Front,Back" bitfld.long 0x08 14. " BPEN_14 ,Back plane pin 14" "Front,Back" bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" textline " " bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" textline " " bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" bitfld.long 0x08 6. " BPEN_6 ,Back plane pin 6" "Front,Back" bitfld.long 0x08 5. " BPEN_5 ,Back plane pin 5" "Front,Back" bitfld.long 0x08 4. " BPEN_4 ,Back plane pin 4" "Front,Back" textline " " bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" bitfld.long 0x0C 15. " BPEN_47 ,Back plane pin 47" "Front,Back" bitfld.long 0x0C 14. " BPEN_46 ,Back plane pin 46" "Front,Back" bitfld.long 0x0C 13. " BPEN_45 ,Back plane pin 45" "Front,Back" bitfld.long 0x0C 12. " BPEN_44 ,Back plane pin 44" "Front,Back" textline " " bitfld.long 0x0C 11. " BPEN_43 ,Back plane pin 43" "Front,Back" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" textline " " bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" bitfld.long 0x0C 5. " BPEN_37 ,Back plane pin 37" "Front,Back" bitfld.long 0x0C 4. " BPEN_36 ,Back plane pin 36" "Front,Back" bitfld.long 0x0C 3. " BPEN_35 ,Back plane pin 35" "Front,Back" textline " " bitfld.long 0x0C 2. " BPEN_34 ,Back plane pin 34" "Front,Back" bitfld.long 0x0C 1. " BPEN_33 ,Back plane pin 33" "Front,Back" bitfld.long 0x0C 0. " BPEN_32 ,Back plane pin 32" "Front,Back" line.long 0x10 "LCD_WF3TO0,LCD Waveform Register" hexmask.long.byte 0x10 24.--31. 1. " WF3 ,Waveform pin 3" hexmask.long.byte 0x10 16.--23. 1. " WF2 ,Waveform pin 2" hexmask.long.byte 0x10 8.--15. 1. " WF1 ,Waveform pin 1" hexmask.long.byte 0x10 0.--7. 1. " WF0 ,Waveform pin 0" line.long 0x14 "LCD_WF7TO4,LCD Waveform Register" hexmask.long.byte 0x14 24.--31. 1. " WF7 ,Waveform pin 7" hexmask.long.byte 0x14 16.--23. 1. " WF6 ,Waveform pin 6" hexmask.long.byte 0x14 8.--15. 1. " WF5 ,Waveform pin 5" hexmask.long.byte 0x14 0.--7. 1. " WF4 ,Waveform pin 4" line.long 0x18 "LCD_WF11TO8,LCD Waveform Register" hexmask.long.byte 0x18 24.--31. 1. " WF11 ,Waveform pin 11" hexmask.long.byte 0x18 16.--23. 1. " WF10 ,Waveform pin 10" hexmask.long.byte 0x18 8.--15. 1. " WF9 ,Waveform pin 9" hexmask.long.byte 0x18 0.--7. 1. " WF8 ,Waveform pin 8" line.long 0x1C "LCD_WF15TO12,LCD Waveform Register" hexmask.long.byte 0x1C 24.--31. 1. " WF15 ,Waveform pin 15" hexmask.long.byte 0x1C 16.--23. 1. " WF14 ,Waveform pin 14" hexmask.long.byte 0x1C 8.--15. 1. " WF13 ,Waveform pin 13" hexmask.long.byte 0x1C 0.--7. 1. " WF12 ,Waveform pin 12" line.long 0x20 "LCD_WF19TO16,LCD Waveform Register" hexmask.long.byte 0x20 24.--31. 1. " WF19 ,Waveform pin 19" hexmask.long.byte 0x20 16.--23. 1. " WF18 ,Waveform pin 18" hexmask.long.byte 0x20 8.--15. 1. " WF17 ,Waveform pin 17" hexmask.long.byte 0x20 0.--7. 1. " WF16 ,Waveform pin 16" line.long 0x24 "LCD_WF23TO20,LCD Waveform Register" hexmask.long.byte 0x24 24.--31. 1. " WF23 ,Waveform pin 23" hexmask.long.byte 0x24 16.--23. 1. " WF22 ,Waveform pin 22" hexmask.long.byte 0x24 8.--15. 1. " WF21 ,Waveform pin 21" hexmask.long.byte 0x24 0.--7. 1. " WF20 ,Waveform pin 20" line.long 0x28 "LCD_WF27TO24,LCD Waveform Register" hexmask.long.byte 0x28 24.--31. 1. " WF27 ,Waveform pin 27" hexmask.long.byte 0x28 16.--23. 1. " WF26 ,Waveform pin 26" hexmask.long.byte 0x28 8.--15. 1. " WF25 ,Waveform pin 25" hexmask.long.byte 0x28 0.--7. 1. " WF24 ,Waveform pin 24" line.long 0x2C "LCD_WF31TO28,LCD Waveform Register" hexmask.long.byte 0x2C 24.--31. 1. " WF31 ,Waveform pin 31" hexmask.long.byte 0x2C 16.--23. 1. " WF30 ,Waveform pin 30" hexmask.long.byte 0x2C 8.--15. 1. " WF29 ,Waveform pin 29" hexmask.long.byte 0x2C 0.--7. 1. " WF28 ,Waveform pin 28" line.long 0x30 "LCD_WF35TO32,LCD Waveform Register" hexmask.long.byte 0x30 24.--31. 1. " WF35 ,Waveform pin 35" hexmask.long.byte 0x30 16.--23. 1. " WF34 ,Waveform pin 34" hexmask.long.byte 0x30 8.--15. 1. " WF33 ,Waveform pin 33" hexmask.long.byte 0x30 0.--7. 1. " WF32 ,Waveform pin 32" line.long 0x34 "LCD_WF39TO36,LCD Waveform Register" hexmask.long.byte 0x34 24.--31. 1. " WF39 ,Waveform pin 39" hexmask.long.byte 0x34 16.--23. 1. " WF38 ,Waveform pin 38" hexmask.long.byte 0x34 8.--15. 1. " WF37 ,Waveform pin 37" hexmask.long.byte 0x34 0.--7. 1. " WF36 ,Waveform pin 36" line.long 0x38 "LCD_WF43TO40,LCD Waveform Register" hexmask.long.byte 0x38 24.--31. 1. " WF43 ,Waveform pin 43" hexmask.long.byte 0x38 16.--23. 1. " WF42 ,Waveform pin 42" hexmask.long.byte 0x38 8.--15. 1. " WF41 ,Waveform pin 41" hexmask.long.byte 0x38 0.--7. 1. " WF40 ,Waveform pin 40" line.long 0x3C "LCD_WF47TO44,LCD Waveform Register" hexmask.long.byte 0x3C 24.--31. 1. " WF47 ,Waveform pin 47" hexmask.long.byte 0x3C 16.--23. 1. " WF46 ,Waveform pin 46" hexmask.long.byte 0x3C 8.--15. 1. " WF45 ,Waveform pin 45" hexmask.long.byte 0x3C 0.--7. 1. " WF44 ,Waveform pin 44" textline " " elif (cpu()=="MK40DN512ZVLL10") group.long 0x10++0x3F line.long 0x00 "LCD_PENL,LCD Pin Enable Register Low" bitfld.long 0x00 31. " PEN_31 ,LCD pin 31" "Disabled,Enabled" bitfld.long 0x00 30. " PEN_30 ,LCD pin 30" "Disabled,Enabled" bitfld.long 0x00 28. " PEN_28 ,LCD pin 28" "Disabled,Enabled" bitfld.long 0x00 29. " PEN_29 ,LCD pin 29" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PEN_27 ,LCD pin 27" "Disabled,Enabled" bitfld.long 0x00 26. " PEN_26 ,LCD pin 26" "Disabled,Enabled" bitfld.long 0x00 25. " PEN_25 ,LCD pin 25" "Disabled,Enabled" bitfld.long 0x00 24. " PEN_24 ,LCD pin 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " PEN_23 ,LCD pin 23" "Disabled,Enabled" bitfld.long 0x00 22. " PEN_22 ,LCD pin 22" "Disabled,Enabled" bitfld.long 0x00 21. " PEN_21 ,LCD pin 21" "Disabled,Enabled" bitfld.long 0x00 20. " PEN_20 ,LCD pin 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PEN_19 ,LCD pin 19" "Disabled,Enabled" bitfld.long 0x00 18. " PEN_18 ,LCD pin 18" "Disabled,Enabled" bitfld.long 0x00 17. " PEN_17 ,LCD pin 17" "Disabled,Enabled" bitfld.long 0x00 16. " PEN_16 ,LCD pin 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " PEN_15 ,LCD pin 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN_14 ,LCD pin 14" "Disabled,Enabled" bitfld.long 0x00 13. " PEN_13 ,LCD pin 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN_12 ,LCD pin 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " PEN_11 ,LCD pin 11" "Disabled,Enabled" bitfld.long 0x00 10. " PEN_10 ,LCD pin 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_9 ,LCD pin 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN_8 ,LCD pin 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN_7 ,LCD pin 7" "Disabled,Enabled" bitfld.long 0x00 3. " PEN_3 ,LCD pin 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN_2 ,LCD pin 2" "Disabled,Enabled" bitfld.long 0x00 1. " PEN_1 ,LCD pin 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PEN_0 ,LCD pin 0" "Disabled,Enabled" line.long 0x04 "LPC_PENH,LCD Pin Enable Register High" bitfld.long 0x04 15. " PEN_47 ,LCD pin 47" "Disabled,Enabled" bitfld.long 0x04 14. " PEN_46 ,LCD pin 46" "Disabled,Enabled" bitfld.long 0x04 13. " PEN_45 ,LCD pin 45" "Disabled,Enabled" bitfld.long 0x04 12. " PEN_44 ,LCD pin 44" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " PEN_43 ,LCD pin 43" "Disabled,Enabled" bitfld.long 0x04 10. " PEN_42 ,LCD pin 42" "Disabled,Enabled" bitfld.long 0x04 9. " PEN_41 ,LCD pin 41" "Disabled,Enabled" bitfld.long 0x04 8. " PEN_40 ,LCD pin 40" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " PEN_38 ,LCD pin 38" "Disabled,Enabled" bitfld.long 0x04 5. " PEN_37 ,LCD pin 37" "Disabled,Enabled" bitfld.long 0x04 4. " PEN_36 ,LCD pin 36" "Disabled,Enabled" line.long 0x08 "LCD_BPENL,LCD Back Plane Enable Register Low" bitfld.long 0x08 31. " BPEN_31 ,Back plane pin 31" "Front,Back" bitfld.long 0x08 30. " BPEN_30 ,Back plane pin 30" "Front,Back" bitfld.long 0x08 29. " BPEN_29 ,Back plane pin 29" "Front,Back" bitfld.long 0x08 28. " BPEN_28 ,Back plane pin 28" "Front,Back" textline " " bitfld.long 0x08 27. " BPEN_27 ,Back plane pin 27" "Front,Back" bitfld.long 0x08 26. " BPEN_26 ,Back plane pin 26" "Front,Back" bitfld.long 0x08 25. " BPEN_25 ,Back plane pin 25" "Front,Back" bitfld.long 0x08 24. " BPEN_24 ,Back plane pin 24" "Front,Back" textline " " bitfld.long 0x08 23. " BPEN_23 ,Back plane pin 23" "Front,Back" bitfld.long 0x08 22. " BPEN_22 ,Back plane pin 22" "Front,Back" bitfld.long 0x08 21. " BPEN_21 ,Back plane pin 21" "Front,Back" textline " " bitfld.long 0x08 20. " BPEN_20 ,Back plane pin 20" "Front,Back" bitfld.long 0x08 19. " BPEN_19 ,Back plane pin 19" "Front,Back" bitfld.long 0x08 18. " BPEN_18 ,Back plane pin 18" "Front,Back" bitfld.long 0x08 17. " BPEN_17 ,Back plane pin 17" "Front,Back" textline " " bitfld.long 0x08 16. " BPEN_16 ,Back plane pin 16" "Front,Back" bitfld.long 0x08 15. " BPEN_15 ,Back plane pin 15" "Front,Back" bitfld.long 0x08 14. " BPEN_14 ,Back plane pin 14" "Front,Back" bitfld.long 0x08 13. " BPEN_13 ,Back plane pin 13" "Front,Back" textline " " bitfld.long 0x08 12. " BPEN_12 ,Back plane pin 12" "Front,Back" bitfld.long 0x08 11. " BPEN_11 ,Back plane pin 11" "Front,Back" bitfld.long 0x08 10. " BPEN_10 ,Back plane pin 10" "Front,Back" bitfld.long 0x08 9. " BPEN_9 ,Back plane pin 9" "Front,Back" textline " " bitfld.long 0x08 8. " BPEN_8 ,Back plane pin 8" "Front,Back" bitfld.long 0x08 7. " BPEN_7 ,Back plane pin 7" "Front,Back" bitfld.long 0x08 3. " BPEN_3 ,Back plane pin 3" "Front,Back" bitfld.long 0x08 2. " BPEN_2 ,Back plane pin 2" "Front,Back" textline " " bitfld.long 0x08 1. " BPEN_1 ,Back plane pin 1" "Front,Back" bitfld.long 0x08 0. " BPEN_0 ,Back plane pin 0" "Front,Back" line.long 0x0C "LCD_BPENH,LCD Back Plane Enable Register High" bitfld.long 0x0C 15. " BPEN_47 ,Back plane pin 47" "Front,Back" bitfld.long 0x0C 14. " BPEN_46 ,Back plane pin 46" "Front,Back" bitfld.long 0x0C 13. " BPEN_45 ,Back plane pin 45" "Front,Back" bitfld.long 0x0C 12. " BPEN_44 ,Back plane pin 44" "Front,Back" textline " " bitfld.long 0x0C 11. " BPEN_43 ,Back plane pin 43" "Front,Back" bitfld.long 0x0C 10. " BPEN_42 ,Back plane pin 42" "Front,Back" bitfld.long 0x0C 9. " BPEN_41 ,Back plane pin 41" "Front,Back" bitfld.long 0x0C 8. " BPEN_40 ,Back plane pin 40" "Front,Back" textline " " bitfld.long 0x0C 6. " BPEN_38 ,Back plane pin 38" "Front,Back" bitfld.long 0x0C 5. " BPEN_37 ,Back plane pin 37" "Front,Back" bitfld.long 0x0C 4. " BPEN_36 ,Back plane pin 36" "Front,Back" line.long 0x10 "LCD_WF3TO0,LCD Waveform Register" hexmask.long.byte 0x10 24.--31. 1. " WF3 ,Waveform pin 3" hexmask.long.byte 0x10 16.--23. 1. " WF2 ,Waveform pin 2" hexmask.long.byte 0x10 8.--15. 1. " WF1 ,Waveform pin 1" hexmask.long.byte 0x10 0.--7. 1. " WF0 ,Waveform pin 0" line.long 0x14 "LCD_WF7TO4,LCD Waveform Register" hexmask.long.byte 0x14 24.--31. 1. " WF7 ,Waveform pin 7" line.long 0x18 "LCD_WF11TO8,LCD Waveform Register" hexmask.long.byte 0x18 24.--31. 1. " WF11 ,Waveform pin 11" hexmask.long.byte 0x18 16.--23. 1. " WF10 ,Waveform pin 10" hexmask.long.byte 0x18 8.--15. 1. " WF9 ,Waveform pin 9" hexmask.long.byte 0x18 0.--7. 1. " WF8 ,Waveform pin 8" line.long 0x1C "LCD_WF15TO12,LCD Waveform Register" hexmask.long.byte 0x1C 24.--31. 1. " WF15 ,Waveform pin 15" hexmask.long.byte 0x1C 16.--23. 1. " WF14 ,Waveform pin 14" hexmask.long.byte 0x1C 8.--15. 1. " WF13 ,Waveform pin 13" hexmask.long.byte 0x1C 0.--7. 1. " WF12 ,Waveform pin 12" line.long 0x20 "LCD_WF19TO16,LCD Waveform Register" hexmask.long.byte 0x20 24.--31. 1. " WF19 ,Waveform pin 19" hexmask.long.byte 0x20 16.--23. 1. " WF18 ,Waveform pin 18" hexmask.long.byte 0x20 8.--15. 1. " WF17 ,Waveform pin 17" hexmask.long.byte 0x20 0.--7. 1. " WF16 ,Waveform pin 16" line.long 0x24 "LCD_WF23TO20,LCD Waveform Register" hexmask.long.byte 0x24 24.--31. 1. " WF23 ,Waveform pin 23" hexmask.long.byte 0x24 16.--23. 1. " WF22 ,Waveform pin 22" hexmask.long.byte 0x24 8.--15. 1. " WF21 ,Waveform pin 21" hexmask.long.byte 0x24 0.--7. 1. " WF20 ,Waveform pin 20" line.long 0x28 "LCD_WF27TO24,LCD Waveform Register" hexmask.long.byte 0x28 24.--31. 1. " WF27 ,Waveform pin 27" hexmask.long.byte 0x28 16.--23. 1. " WF26 ,Waveform pin 26" hexmask.long.byte 0x28 8.--15. 1. " WF25 ,Waveform pin 25" hexmask.long.byte 0x28 0.--7. 1. " WF24 ,Waveform pin 24" line.long 0x2C "LCD_WF31TO28,LCD Waveform Register" hexmask.long.byte 0x2C 24.--31. 1. " WF31 ,Waveform pin 31" hexmask.long.byte 0x2C 16.--23. 1. " WF30 ,Waveform pin 30" hexmask.long.byte 0x2C 8.--15. 1. " WF29 ,Waveform pin 29" hexmask.long.byte 0x2C 0.--7. 1. " WF28 ,Waveform pin 28" group.long 0x44++0x0B line.long 0x00 "LCD_WF39TO36,LCD Waveform Register" hexmask.long.byte 0x00 16.--23. 1. " WF38 ,Waveform pin 38" hexmask.long.byte 0x00 8.--15. 1. " WF37 ,Waveform pin 37" hexmask.long.byte 0x00 0.--7. 1. " WF36 ,Waveform pin 36" line.long 0x04 "LCD_WF43TO40,LCD Waveform Register" hexmask.long.byte 0x04 24.--31. 1. " WF43 ,Waveform pin 43" hexmask.long.byte 0x04 16.--23. 1. " WF42 ,Waveform pin 42" hexmask.long.byte 0x04 8.--15. 1. " WF41 ,Waveform pin 41" hexmask.long.byte 0x04 0.--7. 1. " WF40 ,Waveform pin 40" line.long 0x08 "LCD_WF47TO44,LCD Waveform Register" hexmask.long.byte 0x08 24.--31. 1. " WF47 ,Waveform pin 47" hexmask.long.byte 0x08 16.--23. 1. " WF46 ,Waveform pin 46" hexmask.long.byte 0x08 8.--15. 1. " WF45 ,Waveform pin 45" hexmask.long.byte 0x08 0.--7. 1. " WF44 ,Waveform pin 44" textline " " else width 7. group.long 0x10++0x0F line.long 0x00 "PENL,LCD Pin Enable Low Register" bitfld.long 0x00 31. " PEN31 ,LCD pin 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PEN30 ,LCD pin 30 enable" "Disabled,Enabled" bitfld.long 0x00 29. " PEN29 ,LCD pin 29 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " PEN28 ,LCD pin 28 enable" "Disabled,Enabled" bitfld.long 0x00 27. " PEN27 ,LCD pin 27 enable" "Disabled,Enabled" bitfld.long 0x00 26. " PEN26 ,LCD pin 26 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " PEN25 ,LCD pin 25 enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEN24 ,LCD pin 24 enable" "Disabled,Enabled" bitfld.long 0x00 23. " PEN23 ,LCD pin 23 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " PEN22 ,LCD pin 22 enable" "Disabled,Enabled" bitfld.long 0x00 21. " PEN21 ,LCD pin 21 enable" "Disabled,Enabled" bitfld.long 0x00 20. " PEN20 ,LCD pin 20 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PEN19 ,LCD pin 19 enable" "Disabled,Enabled" bitfld.long 0x00 18. " PEN18 ,LCD pin 18 enable" "Disabled,Enabled" bitfld.long 0x00 17. " PEN17 ,LCD pin 17 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " PEN16 ,LCD pin 16 enable" "Disabled,Enabled" bitfld.long 0x00 15. " PEN15 ,LCD pin 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,LCD pin 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " PEN13 ,LCD pin 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,LCD pin 12 enable" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,LCD pin 11 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " PEN10 ,LCD pin 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,LCD pin 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,LCD pin 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " PEN7 ,LCD pin 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,LCD pin 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,LCD pin 5 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PEN4 ,LCD pin 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,LCD pin 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,LCD pin 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PEN1 ,LCD pin 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,LCD pin 0 enable" "Disabled,Enabled" line.long 0x04 "PENH,LCD Pin Enable High Register" bitfld.long 0x04 31. " PEN63 ,LCD pin 63 enable" "Disabled,Enabled" bitfld.long 0x04 30. " PEN62 ,LCD pin 62 enable" "Disabled,Enabled" bitfld.long 0x04 29. " PEN61 ,LCD pin 61 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " PEN60 ,LCD pin 60 enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEN59 ,LCD pin 59 enable" "Disabled,Enabled" bitfld.long 0x04 26. " PEN58 ,LCD pin 58 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " PEN57 ,LCD pin 57 enable" "Disabled,Enabled" bitfld.long 0x04 24. " PEN56 ,LCD pin 56 enable" "Disabled,Enabled" bitfld.long 0x04 23. " PEN55 ,LCD pin 55 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " PEN54 ,LCD pin 54 enable" "Disabled,Enabled" bitfld.long 0x04 21. " PEN53 ,LCD pin 53 enable" "Disabled,Enabled" bitfld.long 0x04 20. " PEN52 ,LCD pin 52 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " PEN51 ,LCD pin 51 enable" "Disabled,Enabled" bitfld.long 0x04 18. " PEN50 ,LCD pin 50 enable" "Disabled,Enabled" bitfld.long 0x04 17. " PEN49 ,LCD pin 49 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " PEN48 ,LCD pin 48 enable" "Disabled,Enabled" bitfld.long 0x04 15. " PEN47 ,LCD pin 47 enable" "Disabled,Enabled" bitfld.long 0x04 14. " PEN46 ,LCD pin 46 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " PEN45 ,LCD pin 45 enable" "Disabled,Enabled" bitfld.long 0x04 12. " PEN44 ,LCD pin 44 enable" "Disabled,Enabled" bitfld.long 0x04 11. " PEN43 ,LCD pin 43 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " PEN42 ,LCD pin 42 enable" "Disabled,Enabled" bitfld.long 0x04 9. " PEN41 ,LCD pin 41 enable" "Disabled,Enabled" bitfld.long 0x04 8. " PEN40 ,LCD pin 40 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " PEN39 ,LCD pin 39 enable" "Disabled,Enabled" bitfld.long 0x04 6. " PEN38 ,LCD pin 38 enable" "Disabled,Enabled" bitfld.long 0x04 5. " PEN37 ,LCD pin 37 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " PEN36 ,LCD pin 36 enable" "Disabled,Enabled" bitfld.long 0x04 3. " PEN35 ,LCD pin 35 enable" "Disabled,Enabled" bitfld.long 0x04 2. " PEN34 ,LCD pin 34 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " PEN33 ,LCD pin 33 enable" "Disabled,Enabled" bitfld.long 0x04 0. " PEN32 ,LCD pin 32 enable" "Disabled,Enabled" line.long 0x08 "BPENL,LCD Backplane Enable Low Register" bitfld.long 0x08 31. " BPEN31 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 30. " BPEN30 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 29. " BPEN29 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " BPEN28 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 27. " BPEN27 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 26. " BPEN26 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 25. " BPEN25 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 24. " BPEN24 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 23. " BPEN23 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 22. " BPEN22 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 21. " BPEN21 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 20. " BPEN20 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " BPEN19 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 18. " BPEN18 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 17. " BPEN17 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " BPEN16 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 15. " BPEN15 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 14. " BPEN14 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " BPEN13 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 12. " BPEN12 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 11. " BPEN11 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 10. " BPEN10 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 9. " BPEN9 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 8. " BPEN8 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " BPEN7 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 6. " BPEN6 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 5. " BPEN5 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " BPEN4 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 3. " BPEN3 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 2. " BPEN2 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " BPEN1 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x08 0. " BPEN0 ,Backplane enable" "Disabled,Enabled" line.long 0x0C "BPENH,LCD Backplane Enable High Register" bitfld.long 0x0C 31. " BPEN63 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 30. " BPEN62 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BPEN61 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " BPEN60 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 27. " BPEN59 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 26. " BPEN58 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 25. " BPEN57 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 24. " BPEN56 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 23. " BPEN55 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 22. " BPEN54 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 21. " BPEN53 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 20. " BPEN52 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " BPEN51 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 18. " BPEN50 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 17. " BPEN49 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " BPEN48 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 15. " BPEN47 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 14. " BPEN46 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 13. " BPEN45 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 12. " BPEN44 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 11. " BPEN43 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " BPEN42 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 9. " BPEN41 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 8. " BPEN40 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " BPEN39 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 6. " BPEN38 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 5. " BPEN37 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " BPEN36 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 3. " BPEN35 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 2. " BPEN34 ,Backplane enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " BPEN33 ,Backplane enable" "Disabled,Enabled" bitfld.long 0x0C 0. " BPEN32 ,Backplane enable" "Disabled,Enabled" width 10. textline " " tree "LCD Waveform Registers" group.long 0x20++0x03 line.long 0x00 "WF3TO0,LCD waveform register" bitfld.long 0x00 31. " WF3[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF3[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF3[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF3[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF3[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF3[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF3[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF3[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF2[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF2[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF2[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF2[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF2[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF2[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF2[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF2[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF1[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF1[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF1[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF1[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF1[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF1[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF1[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF1[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF0[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF0[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF0[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF0[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF0[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF0[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF0[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF0[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x24++0x03 line.long 0x00 "WF7TO4,LCD waveform register" bitfld.long 0x00 31. " WF7[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF7[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF7[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF7[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF7[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF7[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF7[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF7[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF6[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF6[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF6[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF6[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF6[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF6[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF6[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF6[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF5[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF5[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF5[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF5[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF5[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF5[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF5[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF5[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF4[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF4[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF4[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF4[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF4[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF4[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF4[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF4[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x28++0x03 line.long 0x00 "WF11TO8,LCD waveform register" bitfld.long 0x00 31. " WF11[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF11[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF11[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF11[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF11[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF11[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF11[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF11[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF10[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF10[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF10[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF10[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF10[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF10[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF10[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF10[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF9[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF9[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF9[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF9[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF9[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF9[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF9[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF9[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF8[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF8[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF8[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF8[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF8[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF8[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF8[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF8[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x2C++0x03 line.long 0x00 "WF15TO12,LCD waveform register" bitfld.long 0x00 31. " WF15[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF15[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF15[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF15[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF15[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF15[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF15[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF15[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF14[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF14[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF14[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF14[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF14[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF14[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF14[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF14[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF13[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF13[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF13[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF13[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF13[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF13[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF13[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF13[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF12[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF12[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF12[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF12[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF12[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF12[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF12[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF12[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x30++0x03 line.long 0x00 "WF19TO16,LCD waveform register" bitfld.long 0x00 31. " WF19[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF19[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF19[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF19[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF19[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF19[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF19[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF19[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF18[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF18[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF18[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF18[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF18[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF18[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF18[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF18[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF17[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF17[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF17[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF17[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF17[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF17[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF17[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF17[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF16[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF16[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF16[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF16[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF16[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF16[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF16[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF16[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x34++0x03 line.long 0x00 "WF23TO20,LCD waveform register" bitfld.long 0x00 31. " WF23[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF23[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF23[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF23[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF23[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF23[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF23[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF23[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF22[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF22[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF22[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF22[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF22[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF22[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF22[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF22[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF21[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF21[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF21[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF21[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF21[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF21[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF21[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF21[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF20[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF20[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF20[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF20[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF20[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF20[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF20[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF20[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x38++0x03 line.long 0x00 "WF27TO24,LCD waveform register" bitfld.long 0x00 31. " WF27[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF27[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF27[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF27[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF27[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF27[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF27[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF27[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF26[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF26[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF26[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF26[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF26[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF26[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF26[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF26[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF25[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF25[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF25[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF25[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF25[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF25[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF25[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF25[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF24[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF24[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF24[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF24[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF24[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF24[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF24[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF24[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x3C++0x03 line.long 0x00 "WF31TO28,LCD waveform register" bitfld.long 0x00 31. " WF31[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF31[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF31[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF31[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF31[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF31[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF31[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF31[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF30[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF30[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF30[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF30[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF30[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF30[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF30[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF30[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF29[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF29[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF29[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF29[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF29[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF29[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF29[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF29[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF28[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF28[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF28[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF28[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF28[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF28[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF28[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF28[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x40++0x03 line.long 0x00 "WF35TO32,LCD waveform register" bitfld.long 0x00 31. " WF35[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF35[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF35[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF35[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF35[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF35[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF35[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF35[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF34[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF34[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF34[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF34[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF34[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF34[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF34[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF34[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF33[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF33[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF33[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF33[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF33[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF33[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF33[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF33[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF32[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF32[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF32[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF32[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF32[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF32[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF32[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF32[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x44++0x03 line.long 0x00 "WF39TO36,LCD waveform register" bitfld.long 0x00 31. " WF39[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF39[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF39[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF39[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF39[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF39[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF39[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF39[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF38[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF38[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF38[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF38[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF38[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF38[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF38[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF38[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF37[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF37[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF37[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF37[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF37[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF37[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF37[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF37[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF36[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF36[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF36[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF36[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF36[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF36[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF36[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF36[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x48++0x03 line.long 0x00 "WF43TO40,LCD waveform register" bitfld.long 0x00 31. " WF43[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF43[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF43[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF43[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF43[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF43[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF43[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF43[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF42[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF42[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF42[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF42[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF42[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF42[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF42[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF42[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF41[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF41[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF41[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF41[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF41[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF41[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF41[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF41[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF40[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF40[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF40[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF40[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF40[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF40[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF40[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF40[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x4C++0x03 line.long 0x00 "WF47TO44,LCD waveform register" bitfld.long 0x00 31. " WF47[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF47[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF47[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF47[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF47[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF47[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF47[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF47[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF46[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF46[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF46[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF46[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF46[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF46[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF46[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF46[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF45[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF45[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF45[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF45[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF45[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF45[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF45[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF45[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF44[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF44[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF44[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF44[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF44[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF44[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF44[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF44[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x50++0x03 line.long 0x00 "WF51TO48,LCD waveform register" bitfld.long 0x00 31. " WF51[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF51[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF51[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF51[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF51[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF51[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF51[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF51[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF50[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF50[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF50[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF50[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF50[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF50[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF50[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF50[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF49[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF49[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF49[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF49[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF49[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF49[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF49[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF49[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF48[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF48[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF48[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF48[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF48[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF48[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF48[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF48[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x54++0x03 line.long 0x00 "WF55TO52,LCD waveform register" bitfld.long 0x00 31. " WF55[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF55[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF55[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF55[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF55[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF55[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF55[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF55[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF54[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF54[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF54[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF54[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF54[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF54[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF54[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF54[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF53[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF53[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF53[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF53[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF53[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF53[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF53[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF53[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF52[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF52[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF52[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF52[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF52[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF52[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF52[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF52[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x58++0x03 line.long 0x00 "WF59TO56,LCD waveform register" bitfld.long 0x00 31. " WF59[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF59[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF59[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF59[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF59[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF59[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF59[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF59[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF58[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF58[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF58[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF58[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF58[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF58[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF58[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF58[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF57[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF57[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF57[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF57[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF57[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF57[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF57[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF57[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF56[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF56[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF56[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF56[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF56[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF56[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF56[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF56[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" group.long 0x5C++0x03 line.long 0x00 "WF63TO60,LCD waveform register" bitfld.long 0x00 31. " WF63[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 30. " WF63[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 29. " WF63[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 28. " WF63[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 27. " WF63[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 26. " WF63[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 25. " WF63[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 24. " WF63[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 23. " WF62[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 22. " WF62[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 21. " WF62[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 20. " WF62[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 19. " WF62[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 18. " WF62[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 17. " WF62[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 16. " WF62[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 15. " WF61[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 14. " WF61[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 13. " WF61[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 12. " WF61[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 11. " WF61[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 10. " WF61[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 9. " WF61[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 8. " WF61[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 7. " WF60[H] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 6. " WF60[G] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 5. " WF60[F] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 4. " WF60[E] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 3. " WF60[D] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 2. " WF60[C] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" textline " " bitfld.long 0x00 1. " WF60[B] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" bitfld.long 0x00 0. " WF60[A] ,Segment-on backplane operation (backplane: Disabled/Enabled)" "Segment off/Phase deactivated,Segment on/Phase activated" tree.end endif width 0xB tree.end endif tree.open "GPIO (General-Purpose Input/Output)" tree.open "GPIO" tree "GPIO A" base ad:0x400FF000 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOA_PDOR,Port Data Output Register A" bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOA_PDOR_SET/CLR,Port Data Output Set/Clear Register A" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOA_PTOR,Port Toggle Output Register" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x0 line.byte 0x00 "GPIOA_PDIR,Port Data Input Register A" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOA_PDDR,Port Data Direction Register A" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOA_GACR,GPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) tree "GPIO B" base ad:0x400FF001 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOB_PDOR,Port Data Output Register B" bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOB_PDOR_SET/CLR,Port Data Output Set/Clear Register B" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOB_PTOR,Port Toggle Output Register B" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOB_PDIR,Port Data Input Register B" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOB_PDDR,Port Data Direction Register B" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" textline " " sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOB_GACR,GPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO C" base ad:0x400FF002 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOC_PDOR,Port Data Output Register C" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port Data Output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port Data Output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port Data Output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port Data Output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port Data Output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port Data Output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port Data Output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port Data Output 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 3. " PDO3 , Port Data Output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port Data Output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port Data Output 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDO0 , Port Data Output 0" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOC_PDOR_SET/CLR,Port Data Output Set/Clear Register C" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port Data Output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port Data Output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port Data Output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port Data Output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port Data Output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port Data Output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port Data Output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port Data Output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOC_PTOR,Port Toggle Output Register C" bitfld.byte 0x00 7. " PTTO7 ,Port Toggle Output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port Toggle Output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port Toggle Output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port Toggle Output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port Toggle Output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port Toggle Output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port Toggle Output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port Toggle Output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOC_PDIR,Port Data Input Register C" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port Data Input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port Data Input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port Data Input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port Data Input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port Data Input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port Data Input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port Data Input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port Data Input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 3. " PDI3 , Port Data Input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port Data Input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port Data Input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port Data Input 0" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOC_PDDR,Port Data Direction Register C" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port Data Direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port Data Direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port Data Direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port Data Direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port Data Direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port Data Direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port Data Direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port Data Direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 3. " PDD3 , Port Data Direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port Data Direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port Data Direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port Data Direction 0" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOC_GACR,GPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read Only Bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute Check Bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO D" base ad:0x400FF003 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOD_PDOR,Port Data Output Register D" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOD_PDOR_SET/CLR,Port Data Output Set/Clear Register D" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOD_PTOR,Port Toggle Output Register D" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOD_PDIR,Port Data Input Register D" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOD_PDDR,Port Data Direction Register D" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOD_GACR,GPIO Attribute Checker Register D" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif tree "GPIO E" base ad:0x400FF040 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOE_PDOR,Port Data Output Register E" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOE_PDOR_SET/CLR,Port Data Output Register E" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOE_PTOR,Port Toggle Output Register E" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOE_PDIR,Port Data Input Register E" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOE_PDDR,Port Data Direction Register E" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOE_GACR,GPIO Attribute Checker Register E" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO F" base ad:0x400FF041 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOF_PDOR,Port Data Output Register F" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOF_PDOR_SET/CLR,Port Data Output Register F" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOF_PTOR,Port Toggle Output Register F" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOF_PDIR,Port Data Input Register F" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOF_PDDR,Port Data Direction Register F" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOF_GACR,GPIO Attribute Checker Register F" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO G" base ad:0x400FF042 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOG_PDOR,Port Data Output Register G" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOG_PDOR_SET/CLR,Port Data Output Set/Clear Register G" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOG_PTOR,Port Toggle Output Register G" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOG_PDIR,Port Data Input Register G" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOG_PDDR,Port Data Direction Register G" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")) bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" textline " " bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOG_GACR,GPIO Attribute Checker Register G" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "GPIO H" base ad:0x400FF043 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOH_PDOR,Port Data Output Register H" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" bitfld.byte 0x00 5. " PDO5 , Port data output 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDO4 , Port data output 4" "Input,Output" bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDO7 , Port data output 7" "Input,Output" bitfld.byte 0x00 6. " PDO6 , Port data output 6" "Input,Output" endif else width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOH_PDOR_SET/CLR,Port Data Output Set/Clear Register H" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOH_PTOR,Port Toggle Output Register H" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOH_PDIR,Port Data Input Register H" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOH_PDDR,Port Data Direction Register H" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOH_GACR,GPIO Attribute Checker Register H" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif tree "GPIO I" base ad:0x400FF080 width 12. sif (!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOI_PDOR,Port Data Output Register I" sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")) bitfld.byte 0x00 3. " PDO3 , Port data output 3" "Input,Output" bitfld.byte 0x00 2. " PDO2 , Port data output 2" "Input,Output" bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 1. " PDO1 , Port data output 1" "Input,Output" bitfld.byte 0x00 0. " PDO0 , Port data output 0" "Input,Output" endif else width 20. sif (cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "GPIOI_PDOR_SET/CLR,Port Data Output Set/Clear Register I" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOI_PTOR,Port Toggle Output Register I" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" else group.byte 0x00++0x00 line.byte 0x00 "GPIOI_PDOR_SET/CLR,Port Data Output Set/Clear Register I" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOI_PTOR,Port Toggle Output Register I" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" endif textline " " endif width 12. rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOI_PDIR,Port Data Input Register I" sif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "GPIOI_PDDR,Port Data Direction Register I" sif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM14Z128CHH5*")) bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "GPIOI_GACR,GPIO Attribute Checker Register I" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end sif (cpuis("MKM34Z256VLQ7")) tree "GPIO J" base ad:0x400FF081 width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOJ_PDOR_SET/CLR,Port Data Output Set/Clear Register J" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOJ_PTOR,Port Toggle Output Register J" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOJ_PDIR,Port Data Input Register J" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "GPIOJ_PDDR,Port Data Direction Register J" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "GPIOJ_GACR,GPIO Attribute Checker Register J" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO K" base ad:0x400FF082 width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOK_PDOR_SET/CLR,Port Data Output Set/Clear Register K" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOK_PTOR,Port Toggle Output Register K" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOK_PDIR,Port Data Input Register K" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "GPIOK_PDDR,Port Data Direction Register K" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "GPIOK_GACR,GPIO Attribute Checker Register K" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "GPIO L" base ad:0x400FF083 width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOL_PDOR_SET/CLR,Port Data Output Set/Clear Register L" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" textline " " setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOL_PTOR,Port Toggle Output Register L" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" textline " " bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOL_PDIR,Port Data Input Register L" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "GPIOL_PDDR,Port Data Direction Register L" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "GPIOL_GACR,GPIO Attribute Checker Register L" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "GPIO M" base ad:0x400FF0C0 width 20. group.byte 0x00++0x00 line.byte 0x00 "GPIOM_PDOR_SET/CLR,Port Data Output Set/Clear Register M" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "GPIOM_PTOR,Port Toggle Output Register M" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "GPIOM_PDIR,Port Data Input Register M" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "GPIOM_PDDR,Port Data Direction Register M" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "GPIOM_GACR,GPIO Attribute Checker Register M" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif tree.end tree.open "FGPIO" sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "FGPIOA" base ad:0xF8000000 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOA_PDOR_SET/CLR,Port Data Output Set/Clear Register A" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOA_PTOR,Port Toggle Output Register" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOA_PDIR,Port Data Input Register A" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOA_PDDR,Port Data Direction Register A" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOA_GACR,FGPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOB" base ad:0xF8000001 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOB_PDOR_SET/CLR,Port Data Output Set/Clear Register B" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOB_PTOR,Port Toggle Output Register B" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOB_PDIR,Port Data Input Register B" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOB_PDDR,Port Data Direction Register B" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOB_GACR,FGPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOC" base ad:0xF8000002 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOC_PDOR_SET/CLR,Port Data Output Set/Clear Register C" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOC_PTOR,Port Toggle Output Register C" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOC_PDIR,Port Data Input Register C" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOC_PDDR,Port Data Direction Register C" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOC_GACR,FGPIO Attribute Checker Register" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOD" base ad:0xF8000003 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOD_PDOR_SET/CLR,Port Data Output Set/Clear Register D" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOD_PTOR,Port Toggle Output Register D" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOD_PDIR,Port Data Input Register D" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOD_PDDR,Port Data Direction Register D" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOD_GACR,FGPIO Attribute Checker Register D" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOE" base ad:0xF8000040 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOE_PDOR_SET/CLR,Port Data Output Set/Clear Register E" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOE_PTOR,Port Toggle Output Register E" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOE_PDIR,Port Data Input Register E" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOE_PDDR,Port Data Direction Register E" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOE_GACR,FGPIO Attribute Checker Register E" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOF" base ad:0xF8000041 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOF_PDOR_SET/CLR,Port Data Output Set/Clear Register F" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOF_PTOR,Port Toggle Output Register F" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOF_PDIR,Port Data Input Register F" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOF_PDDR,Port Data Direction Register F" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOF_GACR,FGPIO Attribute Checker Register F" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOG" base ad:0xF8000042 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOG_PDOR_SET/CLR,Port Data Output Set/Clear Register G" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOG_PTOR,Port Toggle Output Register G" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOG_PDIR,Port Data Input Register G" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOG_PDDR,Port Data Direction Register G" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOG_GACR,FGPIO Attribute Checker Register G" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOH" base ad:0xF8000043 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOH_PDOR_SET/CLR,Port Data Output Set/Clear Register H" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOH_PTOR,Port Toggle Output Register H" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOH_PDIR,Port Data Input Register H" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOH_PDDR,Port Data Direction Register H" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOH_GACR,FGPIO Attribute Checker Register H" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOI" base ad:0xF8000080 width 21. sif (cpuis("MKM34Z256VLQ7")) group.byte 0x00++0x00 line.byte 0x00 "FGPIOI_PDOR_SET/CLR,Port Data Output Set/Clear Register I" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOI_PTOR,Port Toggle Output Register I" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" else group.byte 0x00++0x00 line.byte 0x00 "FGPIOI_PDOR_SET/CLR,Port Data Output Set/Clear Register I" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOI_PTOR,Port Toggle Output Register I" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" endif textline " " width 13. rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOI_PDIR,Port Data Input Register I" sif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" textline " " elif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" endif group.byte 0x14++0x00 line.byte 0x00 "FGPIOI_PDDR,Port Data Direction Register I" sif (cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" textline " " elif (cpuis("MKM34Z256VLL7*")) bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" endif group.byte 0x1C++0x00 line.byte 0x00 "FGPIOI_GACR,FGPIO Attribute Checker Register I" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end sif (cpuis("MKM34Z256VLQ7")) tree "FGPIOJ" base ad:0xF8000081 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOJ_PDOR_SET/CLR,Port Data Output Set/Clear Register J" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOJ_PTOR,Port Toggle Output Register J" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOJ_PDIR,Port Data Input Register J" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOJ_PDDR,Port Data Direction Register J" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOJ_GACR,FGPIO Attribute Checker Register J" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOK" base ad:0xF8000082 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOK_PDOR_SET/CLR,Port Data Output Set/Clear Register K" setclrfld.byte 0x00 7. 0x04 7. 0x08 7. " PDO7 , Port data output 7" "Input,Output" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" textline " " setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" textline " " setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOK_PTOR,Port Toggle Output Register K" bitfld.byte 0x00 7. " PTTO7 ,Port toggle output 7" "No toggle,Toggle" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" textline " " bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" textline " " bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOK_PDIR,Port Data Input Register K" bitfld.byte 0x00 7. " PDI7 , Port data input 7" "Input,Output" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOK_PDDR,Port Data Direction Register K" bitfld.byte 0x00 7. " PDD7 , Port data direction 7" "Input,Output" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" textline " " bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" textline " " bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOK_GACR,FGPIO Attribute Checker Register K" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end tree "FGPIOL" base ad:0xF8000083 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOL_PDOR_SET/CLR,Port Data Output Set/Clear Register L" setclrfld.byte 0x00 6. 0x04 6. 0x08 6. " PDO6 , Port data output 6" "Input,Output" setclrfld.byte 0x00 5. 0x04 5. 0x08 5. " PDO5 , Port data output 5" "Input,Output" setclrfld.byte 0x00 4. 0x04 4. 0x08 4. " PDO4 , Port data output 4" "Input,Output" textline " " setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOL_PTOR,Port Toggle Output Register L" bitfld.byte 0x00 6. " PTTO6 ,Port toggle output 6" "No toggle,Toggle" bitfld.byte 0x00 5. " PTTO5 ,Port toggle output 5" "No toggle,Toggle" bitfld.byte 0x00 4. " PTTO4 ,Port toggle output 4" "No toggle,Toggle" textline " " bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOL_PDIR,Port Data Input Register L" bitfld.byte 0x00 6. " PDI6 , Port data input 6" "Input,Output" bitfld.byte 0x00 5. " PDI5 , Port data input 5" "Input,Output" bitfld.byte 0x00 4. " PDI4 , Port data input 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOL_PDDR,Port Data Direction Register L" bitfld.byte 0x00 6. " PDD6 , Port data direction 6" "Input,Output" bitfld.byte 0x00 5. " PDD5 , Port data direction 5" "Input,Output" bitfld.byte 0x00 4. " PDD4 , Port data direction 4" "Input,Output" textline " " bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOL_GACR,FGPIO Attribute Checker Register L" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif tree "FGPIOM" base ad:0xF80000C0 width 21. group.byte 0x00++0x00 line.byte 0x00 "FGPIOM_PDOR_SET/CLR,Port Data Output Set/Clear Register M" setclrfld.byte 0x00 3. 0x04 3. 0x08 3. " PDO3 , Port data output 3" "Input,Output" setclrfld.byte 0x00 2. 0x04 2. 0x08 2. " PDO2 , Port data output 2" "Input,Output" setclrfld.byte 0x00 1. 0x04 1. 0x08 1. " PDO1 , Port data output 1" "Input,Output" textline " " setclrfld.byte 0x00 0. 0x04 0. 0x08 0. " PDO0 , Port data output 0" "Input,Output" wgroup.byte 0x0C++0x00 line.byte 0x00 "FGPIOM_PTOR,Port Toggle Output Register M" bitfld.byte 0x00 3. " PTTO3 ,Port toggle output 3" "No toggle,Toggle" bitfld.byte 0x00 2. " PTTO2 ,Port toggle output 2" "No toggle,Toggle" bitfld.byte 0x00 1. " PTTO1 ,Port toggle output 1" "No toggle,Toggle" textline " " bitfld.byte 0x00 0. " PTTO0 ,Port toggle output 0" "No toggle,Toggle" rgroup.byte 0x10++0x00 line.byte 0x00 "FGPIOM_PDIR,Port Data Input Register M" bitfld.byte 0x00 3. " PDI3 , Port data input 3" "Input,Output" bitfld.byte 0x00 2. " PDI2 , Port data input 2" "Input,Output" bitfld.byte 0x00 1. " PDI1 , Port data input 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDI0 , Port data input 0" "Input,Output" group.byte 0x14++0x00 line.byte 0x00 "FGPIOM_PDDR,Port Data Direction Register M" bitfld.byte 0x00 3. " PDD3 , Port data direction 3" "Input,Output" bitfld.byte 0x00 2. " PDD2 , Port data direction 2" "Input,Output" bitfld.byte 0x00 1. " PDD1 , Port data direction 1" "Input,Output" textline " " bitfld.byte 0x00 0. " PDD0 , Port data direction 0" "Input,Output" group.byte 0x1C++0x00 line.byte 0x00 "FGPIOM_GACR,FGPIO Attribute Checker Register M" bitfld.byte 0x00 7. " ROB ,Read only bit" "Unlocked,Locked" bitfld.byte 0x00 0.--2. " ACB ,Attribute check bits" "RW/RW/RW,RW/RW/RO,RW/RW/--,RW/RO/RO,RW/RO/--,RW/--/--,RO/--/--,--/--/--" width 0x0B tree.end endif tree.end tree.end sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") tree.open "MTB (Micro Trace Buffer)" tree "MTB_RAM" base ad:0xF0000000 width 17. group.long 0x00++0x0B line.long 0x00 "MTB_POSITION,MTB Position Register" hexmask.long 0x00 3.--31. 0x08 " POINTER ,Trace packet address pointer" bitfld.long 0x00 2. " WRAP ,Pointer value wraps" "Low,High" line.long 0x04 "MTB_MASTER,MTB Master Register" bitfld.long 0x04 31. " EN ,Main trace enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " HALTREQ ,Halt request bit" "Not requested,Requested" bitfld.long 0x04 8. " RAMPRIV ,RAM privilege bit" "Low,High" newline bitfld.long 0x04 7. " SFRWPRIV ,Special function register write privilege bit" "Low,High" bitfld.long 0x04 6. " TSTOPEN ,Trace stop input enable" "Disabled,Enabled" bitfld.long 0x04 5. " TSTARTEN ,Trace start input enable" "Disabled,Enabled" newline bitfld.long 0x04 0.--4. " MASK ,Maximum size of the trace buffer in RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MTB_FLOW,MTB Flow Register" hexmask.long 0x08 3.--31. 0x08 " WATERMARK ,Watermark value" bitfld.long 0x08 1. " AUTOHALT ,Autohalt" "Not halted,Halted" bitfld.long 0x08 0. " AUTOSTOP ,Autostop" "Not stopped,Stopped" rgroup.long 0x0C++0x03 line.long 0x00 "MTB_BASE,MTB Base Register" rgroup.long 0xF00++0x03 line.long 0x00 "MTB_MODECTRL,Integration Mode Control Register" rgroup.long 0xFA0++0x07 line.long 0x00 "MTB_TAGSET,Claim TAG Set Register" line.long 0x04 "MTB_TAGCLEAR,Claim TAG Clear Register" rgroup.long 0xFB0++0x0F line.long 0x00 "MTB_LOCKACCESS,Lock Access Register" line.long 0x04 "MTB_LOCKSTAT,Lock Status Register" line.long 0x08 "MTB_AUTHSTAT,Authentication Status Register" bitfld.long 0x08 2. " BIT2 ,It's hardwired to NIDEN or DBGEN signal" "Low,High" bitfld.long 0x08 0. " BIT0 ,It's hardwired to DBGEN" "Low,High" line.long 0x0C "MTB_DEVICEARCH,Device Architecture Register" rgroup.long 0xFC8++0x07 line.long 0x00 "MTB_DEVICECFG,Device Configuration Register" line.long 0x04 "MTB_DEVICETYPID,Device Type Identifier Register" rgroup.long 0xFD0++0x03 line.long 0x00 "MTB_PERIPHID4,Peripheral ID Register 4" rgroup.long 0xFD4++0x03 line.long 0x00 "MTB_PERIPHID5,Peripheral ID Register 5" rgroup.long 0xFD8++0x03 line.long 0x00 "MTB_PERIPHID6,Peripheral ID Register 6" rgroup.long 0xFDC++0x03 line.long 0x00 "MTB_PERIPHID7,Peripheral ID Register 7" rgroup.long 0xFE0++0x03 line.long 0x00 "MTB_PERIPHID0,Peripheral ID Register 0" rgroup.long 0xFE4++0x03 line.long 0x00 "MTB_PERIPHID1,Peripheral ID Register 1" rgroup.long 0xFE8++0x03 line.long 0x00 "MTB_PERIPHID2,Peripheral ID Register 2" rgroup.long 0xFEC++0x03 line.long 0x00 "MTB_PERIPHID3,Peripheral ID Register 3" rgroup.long 0xFF0++0x03 line.long 0x00 "MTB_COMPID0,Component ID Register 0" rgroup.long 0xFF4++0x03 line.long 0x00 "MTB_COMPID1,Component ID Register 1" rgroup.long 0xFF8++0x03 line.long 0x00 "MTB_COMPID2,Component ID Register 2" rgroup.long 0xFFC++0x03 line.long 0x00 "MTB_COMPID3,Component ID Register 3" width 0x0B tree.end tree "MTB_DWT" base ad:0xF0001000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MTBDWT_CTRL,MTB DWT Control Register" bitfld.long 0x00 28.--31. " NUMCMP ,Number of comparators" "0,1,?..." bitfld.long 0x00 27. " NOTRCPKT ,Trace sample and exception trace" "Supported,Not supported" bitfld.long 0x00 26. " NOEXTTRIG ,External match signals" "Supported,Not supported" newline bitfld.long 0x00 25. " NOCYCCNT ,Cycle counter" "Supported,Not supported" bitfld.long 0x00 24. " NOPRFCNT ,Profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEBTENA ,POSTCNT underflow packets" "Not generated,Generated" newline bitfld.long 0x00 21. " FOLDEVTENA ,Folded instruction counter overflow events" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,LSU counter overflow events" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Sleep counter overflow events" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Exception overhead counter events" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,CPI counter overflow events" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLENA ,Periodic PC sample packets" "Not generated,Generated" bitfld.long 0x00 10.--11. " SYNCTAP ,Synchronization packets" "0,1,2,3" bitfld.long 0x00 9. " CYCTAP ,Cycle counter" "Not supported,Supported" newline bitfld.long 0x00 5.--8. " POSTINIT ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Cycle counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Cycle counter" "Not supported,Supported" group.long 0x20++0x0B line.long 0x00 "MTBDWT_COMP0,MTB_DWT Comparator Register 0" line.long 0x04 "MTBDWT_MASK0,MTB_DWT Comparator Mask Register 0" bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MTBDWT_FCT0,MTB_DWT Comparator Function Register 0" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred" else bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred" endif bitfld.long 0x08 12.--15. " DATAVADDR0 ,Data value address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 10.--11. " DATAVSIZE ,Data value size" "Byte,Halfword,Word,?..." bitfld.long 0x08 8. " DATAVMATCH ,Data value match" "Address comparison,Data value comparison" newline bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Read + write,?..." group.long 0x30++0x0B line.long 0x00 "MTBDWT_COMP1,MTB_DWT Comparator Register 1" line.long 0x04 "MTBDWT_MASK1,MTB_DWT Comparator Mask Register 1" bitfld.long 0x04 0.--4. " MASK ,Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MTBDWT_FCT1,MTB_DWT Comparator Function Register 1" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") rbitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred" else bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match occurred" endif bitfld.long 0x08 0.--3. " FUNCTION ,Function" "Disabled,,,,Instruction fetch,Data operand read,Data operand write,Read + write,?..." group.long 0x200++0x03 line.long 0x00 "MTBDWT_TBCTRL,MTB_DWT Trace Buffer Control Register" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKE14Z*")||cpuis("MKE15Z*") rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,?..." else bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators" "0,1,?..." endif bitfld.long 0x00 1. " ACOMP1 ,Action based on comparator 1 match" "Trigger TSTOP,Trigger TSTART" newline bitfld.long 0x00 0. " ACOMP0 ,Action based on comparator 0 match" "Trigger TSTOP,Trigger TSTART" rgroup.long 0xFC8++0x07 line.long 0x00 "MTBDWT_DEVICECFG,Device Configuration Register" line.long 0x04 "MTBDWT_DEVICETYPID,Device Type Identifier Register" rgroup.long (0xFD0+0x0)++0x03 line.long 0x00 "MTBDWT_PERIPHID4,Peripheral ID Register 4" rgroup.long (0xFD0+0x4)++0x03 line.long 0x00 "MTBDWT_PERIPHID5,Peripheral ID Register 5" rgroup.long (0xFD0+0x8)++0x03 line.long 0x00 "MTBDWT_PERIPHID6,Peripheral ID Register 6" rgroup.long (0xFD0+0xC)++0x03 line.long 0x00 "MTBDWT_PERIPHID7,Peripheral ID Register 7" rgroup.long (0xFD0+0x10)++0x03 line.long 0x00 "MTBDWT_PERIPHID0,Peripheral ID Register 0" rgroup.long (0xFD0+0x14)++0x03 line.long 0x00 "MTBDWT_PERIPHID1,Peripheral ID Register 1" rgroup.long (0xFD0+0x18)++0x03 line.long 0x00 "MTBDWT_PERIPHID2,Peripheral ID Register 2" rgroup.long (0xFD0+0x1C)++0x03 line.long 0x00 "MTBDWT_PERIPHID3,Peripheral ID Register 3" rgroup.long (0xFF0+0x0)++0x03 line.long 0x00 "MTBDWT_COMPID0,Component ID Register 0" rgroup.long (0xFF0+0x4)++0x03 line.long 0x00 "MTBDWT_COMPID1,Component ID Register 1" rgroup.long (0xFF0+0x8)++0x03 line.long 0x00 "MTBDWT_COMPID2,Component ID Register 2" rgroup.long (0xFF0+0xC)++0x03 line.long 0x00 "MTBDWT_COMPID3,Component ID Register 3" width 0x0B tree.end tree "ROM" base ad:0xF0002000 width 15. rgroup.long 0x0++0x03 line.long 0x00 "ROM_ENTRY0,Entry Register 0" rgroup.long 0x4++0x03 line.long 0x00 "ROM_ENTRY1,Entry Register 1" rgroup.long 0x8++0x03 line.long 0x00 "ROM_ENTRY2,Entry Register 2" rgroup.long 0x0C++0x03 line.long 0x00 "ROM_TABLEMARK,End of Table Marker Register" rgroup.long 0xFCC++0x03 line.long 0x00 "ROM_SYSACCESS,System Access Register" rgroup.long 0xFD0++0x03 line.long 0x00 "ROM_PERIPHID4,Peripheral ID Register 4" rgroup.long 0xFD4++0x03 line.long 0x00 "ROM_PERIPHID5,Peripheral ID Register 5" rgroup.long 0xFD8++0x03 line.long 0x00 "ROM_PERIPHID6,Peripheral ID Register 6" rgroup.long 0xFDC++0x03 line.long 0x00 "ROM_PERIPHID7,Peripheral ID Register 7" rgroup.long 0xFE0++0x03 line.long 0x00 "ROM_PERIPHID0,Peripheral ID Register 0" rgroup.long 0xFE4++0x03 line.long 0x00 "ROM_PERIPHID1,Peripheral ID Register 1" rgroup.long 0xFE8++0x03 line.long 0x00 "ROM_PERIPHID2,Peripheral ID Register 2" rgroup.long 0xFEC++0x03 line.long 0x00 "ROM_PERIPHID3,Peripheral ID Register 3" rgroup.long 0xFF0++0x03 line.long 0x00 "ROM_COMPID0,Component ID Register 0" rgroup.long 0xFF4++0x03 line.long 0x00 "ROM_COMPID1,Component ID Register 1" rgroup.long 0xFF8++0x03 line.long 0x00 "ROM_COMPID2,Component ID Register 2" rgroup.long 0xFFC++0x03 line.long 0x00 "ROM_COMPID3,Component ID Register 3" width 0xB tree.end tree.end endif tree "FTFA (Flash Memory Module)" base ad:0x40020000 width 11. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,FTFL read collision error flag" "No error,Error" textline " " eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" textline " " rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" textline " " rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW??Z*") sif (cpuis("MKV5*")) textline " " rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not ready,Ready" elif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||(cpuis("MKV10Z*"))||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MK63FN1M0VLQ12")||(cpu()=="MK63FN1M0VMD12")||(cpu()=="MK64FN1M0VLQ12")||(cpu()=="MK64FN1M0VMD12")||(cpu()=="MK64FN1M0VLL12")||(cpu()=="MK64FN1M0VDC12")||(cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")) textline " " rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block,1 block" rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "2 flash and 2 flex blocks,?..." textline " " rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" textline " " rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("K32W0?2S1M*") rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " CRCRDY ,CRC ready" "Not available,Available" textline " " rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" else textline " " rbitfld.byte 0x01 2. " PFLSH ,FTFL configuration" "Supported,?..." rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif endif rgroup.byte 0x02++0x00 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) group.byte 0x03++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*")||cpuis("MKW*")||cpuis("MKV5*") rgroup.byte 0x03++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif group.byte 0x4++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Registers" group.byte 0x5++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Registers" group.byte 0x6++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Registers" group.byte 0x7++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Registers" group.byte 0x8++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Registers" group.byte 0x9++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Registers" group.byte 0xA++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Registers" group.byte 0xB++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Registers" group.byte 0xC++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Registers" group.byte 0xD++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Registers" group.byte 0xE++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Registers" group.byte 0xF++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Registers" sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKW*")&&!cpuis("MKV5*") sif (cpuis("K32W0?2S1M*")) group.byte (0x10+0x01)++0x00 line.byte 0x00 "FOPT,Flash Option Register" group.byte (0x11+0x01)++0x00 line.byte 0x00 "FOPT,Flash Option Register" group.byte (0x12+0x01)++0x00 line.byte 0x00 "FOPT,Flash Option Register" group.byte (0x13+0x01)++0x00 line.byte 0x00 "FOPT,Flash Option Register" else group.byte 0x10++0x00 line.byte 0x00 "FOPT,Flash Option Register" endif endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) group.byte 0x18++0x01 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Program flash region protect" "Protected,Not protected" elif cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*") group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" elif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") group.byte 0x10++0x03 line.byte 0x00 "FPROTH3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTH2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTH1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTH0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" elif (cpuis("MKW*")) group.byte 0x10++0x03 line.byte 0x00 "FPROT3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" else group.byte 0x18++0x03 line.byte 0x00 "FPROTH3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTH2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTH1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTH0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" sif (cpuis("K32W0?2S1M*")) group.byte 0x1C++0x03 line.byte 0x00 "FPROTL3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROTL2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " PROT[15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROTL1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " PROT[23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROTL0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " PROT[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" textline " " bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" endif endif sif (cpuis("K32W0?2S1M*")) group.byte 0x24++0x01 line.byte 0x00 "FPROTSL,Secondary Program Flash Protection Registers" line.byte 0x01 "FPROTSH,Secondary Program Flash Protection Registers" endif sif (cpu()!="MK63FN1M0VLQ12")&&(cpu()!="MK63FN1M0VMD12")&&(cpu()!="MKV40F64VLH15")&&(cpu()!="MKV40F128VLH15")&&(cpu()!="MKV40F128VLL15")&&(cpu()!="MKV40F256VLH15")&&(cpu()!="MKV40F256VLL15")&&(cpu()!="MKV43F64VLH15")&&(cpu()!="MKV43F128VLH15")&&(cpu()!="MKV43F128VLL15")&&(cpu()!="MKV44F64VLH15")&&(cpu()!="MKV44F128VLH15")&&(cpu()!="MKV44F128VLL15")&&(cpu()!="MKV45F128VLH15")&&(cpu()!="MKV45F128VLL15")&&(cpu()!="MKV45F256VLH15")&&(cpu()!="MKV45F256VLL15")&&(cpu()!="MKV46F128VLH15")&&(cpu()!="MKV46F128VLL15")&&(cpu()!="MKV46F256VLH15")&&(cpu()!="MKV46F256VLL15")&&cpuis("MKV31F*")&&cpuis("MKV30F*")&&(cpu()=="MK64FN1M0VLQ12")&&(cpu()!="MK64FN1M0VMD12")&&(cpu()!="MK64FN1M0VLL12")&&(cpu()!="MK64FN1M0VDC12")&&(cpu()!="MK65FN2M0CAF18")&&(cpu()!="MK65FN2M0VMF18")&&(cpu()!="MK66FN2M0VLQ18")&&(cpu()!="MK66FN2M0VMD18")&&(!cpuis("K32W0?2S1M*")&&(!cpuis("MKW*"))) group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" line.byte 0x01 "FDPROT,Data Flash Protection Register" elif (cpuis("MKW21D*")) if (((per.l(ad:0x40020000))&0x80)==0x80) group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected" bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected" else rgroup.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT[7] ,EEPROM region 7 protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region 6 protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region 5 protect" "Protected,Not protected" textline " " bitfld.byte 0x00 4. " [4] ,EEPROM region 4 protect" "Protected,Not protected" bitfld.byte 0x00 3. " [3] ,EEPROM region 3 protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region 2 protect" "Protected,Not protected" textline " " bitfld.byte 0x00 1. " [1] ,EEPROM region 1 protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region 0 protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT[7] ,Data flash region 7 protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region 6 protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region 5 protect" "Protected,Not protected" textline " " bitfld.byte 0x01 4. " [4] ,Data flash region 4 protect" "Protected,Not protected" bitfld.byte 0x01 3. " [3] ,Data flash region 3 protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region 2 protect" "Protected,Not protected" textline " " bitfld.byte 0x01 1. " [1] ,Data flash region 1 protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region 0 protect" "Protected,Not protected" endif elif ((cpuis("MKW22D*"))||(cpuis("MKW24D*"))) hgroup.byte 0x16++0x01 hide.byte 0x00 "FEPROT,EEPROM Protection Register" hide.byte 0x01 "FDPROT,Data Flash Protection Register" endif textline " " sif ((cpu()=="MK65FN2M0CAF18")||(cpu()=="MK65FN2M0VMF18")||(cpu()=="MK65FX1M0CAF18")||(cpu()=="MK65FX1M0VMF18")||(cpu()=="MK66FN2M0VLQ18")||(cpu()=="MK66FN2M0VMD18")||(cpu()=="MK66FX1M0VLQ18")||(cpu()=="MK66FX1M0VMD18")||(cpu()=="MKV40F64VLH15")||(cpu()=="MKV40F128VLH15")||(cpu()=="MKV40F128VLL15")||(cpu()=="MKV40F256VLH15")||(cpu()=="MKV40F256VLL15")||(cpu()=="MKV43F64VLH15")||(cpu()=="MKV43F128VLH15")||(cpu()=="MKV43F128VLL15")||(cpu()=="MKV44F64VLH15")||(cpu()=="MKV44F128VLH15")||(cpu()=="MKV44F128VLL15")||(cpu()=="MKV45F128VLH15")||(cpu()=="MKV45F128VLL15")||(cpu()=="MKV45F256VLH15")||(cpu()=="MKV45F256VLL15")||(cpu()=="MKV46F128VLH15")||(cpu()=="MKV46F128VLL15")||(cpu()=="MKV46F256VLH15")||(cpu()=="MKV46F256VLL15")||cpuis("MKV31F*")||cpuis("MKV30F*")||(cpu()=="MKV42F128VLL16")||(cpu()=="MKV42F256VLL16")||(cpu()=="MKV44F128VLL16")||(cpu()=="MKV44F256VLL16")||(cpu()=="MKV46F128VLL16")||(cpu()=="MKV46F256VLL16")||(cpu()=="MKV42F128VLH16")||(cpu()=="MKV42F256VLH16")||(cpu()=="MKV44F128VLH16")||(cpu()=="MKV44F256VLH16")||(cpu()=="MKV44F64VLH16")||(cpu()=="MKV46F128VLH16")||(cpu()=="MKV46F256VLH16")||(cpu()=="MKV44F128VLF16")||(cpu()=="MKV44F64VLF16")||cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("K32W0?2S1M*")) rgroup.byte 0x18++0x0F line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA[39] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " XA[47] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Yes,No" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " XA[55] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Yes,No" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Yes,No" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " XA[63] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Yes,No" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Yes,No" line.byte 0x04 "XACCL3,Execute-only Access Register 3" bitfld.byte 0x04 7. " XA[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 5. " [5] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x04 4. " [4] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 2. " [2] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x04 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x04 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x05 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x05 7. " XA[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 5. " [13] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x05 4. " [12] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 2. " [10] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x05 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x05 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x06 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x06 7. " XA[23] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 6. " [22] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 5. " [21] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x06 4. " [20] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 3. " [19] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 2. " [18] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x06 1. " [17] ,Execute-only access control" "Yes,No" bitfld.byte 0x06 0. " [16] ,Execute-only access control" "Yes,No" line.byte 0x07 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x07 7. " XA[31] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 6. " [30] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 5. " [29] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x07 4. " [28] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 3. " [27] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 2. " [26] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x07 1. " [25] ,Execute-only access control" "Yes,No" bitfld.byte 0x07 0. " [24] ,Execute-only access control" "Yes,No" line.byte 0x08 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x08 7. " SA[39] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 6. " [38] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 5. " [37] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x08 4. " [36] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 3. " [35] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 2. " [34] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x08 1. " [33] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x08 0. " [32] ,Supervisor-only access control" "Yes,No" line.byte 0x09 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x09 7. " SA[47] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 6. " [46] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 5. " [45] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x09 4. " [44] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 3. " [43] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 2. " [42] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x09 1. " [41] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x09 0. " [40] ,Supervisor-only access control" "Yes,No" line.byte 0x0A "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x0A 7. " SA[55] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 6. " [54] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 5. " [53] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0A 4. " [52] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 3. " [51] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 2. " [50] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0A 1. " [49] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0A 0. " [48] ,Supervisor-only access control" "Yes,No" line.byte 0x0B "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x0B 7. " SA[63] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 6. " [62] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 5. " [61] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0B 4. " [60] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 3. " [59] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 2. " [58] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0B 1. " [57] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0B 0. " [56] ,Supervisor-only access control" "Yes,No" line.byte 0x0C "SACCL3,Supervisor-only Access Register 3" bitfld.byte 0x0C 7. " SA[7] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 6. " [6] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 5. " [5] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0C 4. " [4] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 3. " [3] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 2. " [2] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0C 1. " [1] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0C 0. " [0] ,Supervisor-only access control" "Yes,No" line.byte 0x0D "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x0D 7. " SA[15] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 6. " [14] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 5. " [13] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0D 4. " [12] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 3. " [11] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 2. " [10] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0D 1. " [9] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0D 0. " [8] ,Supervisor-only access control" "Yes,No" line.byte 0x0E "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x0E 7. " SA[23] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 6. " [22] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 5. " [21] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0E 4. " [20] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 3. " [19] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 2. " [18] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0E 1. " [17] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0E 0. " [16] ,Supervisor-only access control" "Yes,No" line.byte 0x0F "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x0F 7. " SA[31] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 6. " [30] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 5. " [29] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0F 4. " [28] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 3. " [27] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 2. " [26] ,Supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x0F 1. " [25] ,Supervisor-only access control" "Yes,No" bitfld.byte 0x0F 0. " [24] ,Supervisor-only access control" "Yes,No" sif (cpuis("K32W0?2S1M*")) rgroup.byte 0x28++0x03 line.byte 0x00 "XACCSH,Secondary Execute-only Access Registers" bitfld.byte 0x00 7. " XA_S[15] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 6. " [14] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 5. " [13] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x00 4. " [12] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 3. " [11] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 2. " [10] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x00 1. " [9] ,Execute-only access control" "Yes,No" bitfld.byte 0x00 0. " [8] ,Execute-only access control" "Yes,No" line.byte 0x01 "XACCSL,Secondary Execute-only Access Registers" bitfld.byte 0x01 7. " XA_S[7] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 6. " [6] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 5. " [5] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x01 4. " [4] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 3. " [3] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 2. " [2] ,Execute-only access control" "Yes,No" textline " " bitfld.byte 0x01 1. " [1] ,Execute-only access control" "Yes,No" bitfld.byte 0x01 0. " [0] ,Execute-only access control" "Yes,No" line.byte 0x02 "SACCSH,Secondary Supervisor-only Access Registers" bitfld.byte 0x02 7. " SA_S[15] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x02 6. " [14] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x02 5. " [13] ,Secondary supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x02 4. " [12] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x02 3. " [11] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x02 2. " [10] ,Secondary supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x02 1. " [9] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x02 0. " [8] ,Secondary supervisor-only access control" "Yes,No" line.byte 0x03 "SACCSL,Secondary Supervisor-only Access Registers" bitfld.byte 0x03 7. " SA_S[7] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x03 6. " [6] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x03 5. " [5] ,Secondary supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x03 4. " [4] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x03 3. " [3] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x03 2. " [2] ,Secondary supervisor-only access control" "Yes,No" textline " " bitfld.byte 0x03 1. " [1] ,Secondary supervisor-only access control" "Yes,No" bitfld.byte 0x03 0. " [0] ,Secondary supervisor-only access control" "Yes,No" endif endif sif (cpuis("MKE14Z*")||cpuis("MKE15Z*")||cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")||cpuis("MKW2?Z*")||cpuis("MKW3?Z*")||cpuis("MKW4?Z*")) rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" elif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7") rgroup.byte 0x2C++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2D++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif sif (cpuis("K32W0?2S1M*")) rgroup.byte 0x2E++0x00 line.byte 0x00 "FACSSS,Secondary Flash Access Segment Size Register" rgroup.byte 0x2F++0x00 line.byte 0x00 "FACSNS,Secondary Flash Access Segment Number Register" group.byte 0x52++0x01 line.byte 0x00 "FSTDBYCTL,Flash Standby Control Register" bitfld.byte 0x00 0. " STDBYDIS ,Standy mode disable" "Enabled,Disabled" group.byte 0x53++0x01 line.byte 0x00 "FSTDBY,Flash Standby Register" bitfld.byte 0x00 2. " STDBY2 ,Standy mode for flash block 2" "Enabled,Disabled" bitfld.byte 0x00 1. " STDBY1 ,Standy mode for flash block 1" "Enabled,Disabled" bitfld.byte 0x00 0. " STDBY0 ,Standy mode for flash block 0" "Enabled,Disabled" endif sif (cpuis("MKE14F*")||cpuis("MKE16F*")||cpuis("MKE18F*")) rgroup.byte 0x2E++0x01 line.byte 0x00 "FERSTAT,Flash Error Status Register" bitfld.byte 0x00 1. " DFDIF ,Double bit fault detect interrupt flag" "Not detected,Detected" line.byte 0x01 "FERCNFG,Flash Error Configuration Register" bitfld.byte 0x01 5. " FDFD ,Force double bit fault detect" "Not forced,Forced" bitfld.byte 0x01 1. " DFDIE ,Double bit fault detect interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end textline ""