; --------------------------------------------------------------------------------
; @Title: ISD9300 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-01-16 NEJ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: Generated (TRACE32, build: 165992.), based on:
;       ISD9300_v3_fixed.svd (Ver. 1.0)
; @Core: Cortex-M0
; @Chip: I9331RI, I9331VRI, I9341RI, I9341VRI, I9361RI, I9361VRI
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perisd9300.per 17349 2024-01-19 09:59:04Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "No effect,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "External clock,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Reads as one" "0,1"
bitfld.long 0x00 30. "                SKEW          ,Reads as zero" "0,1"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW          ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. "               VARIANT       ,Implementation defined variant number"
textline "                 "
hexmask.long.byte 0x00 4.--15. 1.  " PARTNO       ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. "               REVISION      ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. "      PENDSVSET     ,Set a pending PendSV interrupt" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 27. " PENDSVCLR    ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. "    PENDSTSET     ,Set a pending SysTick" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 25. " PENDSVCLR    ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. "    ISRPREEMPT    ,Pending exception service" "No service,Service"
textline "                 "
bitfld.long 0x00 22. " ISRPENDING   ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. "     VECTPENDING   ,Active exception number field"
textline "                 "
hexmask.long.byte 0x00 0.--5. 1.  " VECTACTIVET  ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF       ,Vector table address"
else
textline "                 "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY      ,Vector Key"
bitfld.long 0x00 15. "             ENDIANNESS    ,Data endianness bit" "Little-endian,Big-endian"
textline "                 "
bitfld.long 0x00 2. " SYSRESETREQ  ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. "        VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. "       SLEEPDEEP     ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                 "
bitfld.long 0x00 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN     ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. "         UNALIGN_TRP   ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11       ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15       ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. "               PRI_14        ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline "                 "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "     SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "     SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "     SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "     SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "     SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "     SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "     SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "     SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "     SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "     SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "     SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "     SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "     SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "     SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "     SET/CLRENA9  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "     SET/CLRENA8  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "     SET/CLRENA6  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "     SET/CLRENA5  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "     SET/CLRENA3  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "     SET/CLRENA2  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "     SET/CLRENA0  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEN9  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEN8  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEN6  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEN5  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEN3  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEN2  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEN0  ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3  ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. "  IP_2  ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. "  IP_1  ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7.   "  IP_0  ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7  ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. "  IP_6  ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. "  IP_5  ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7.   "  IP_4  ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. "  IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. "  IP_9  ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7.   "  IP_8  ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. "  IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. "  IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7.   "  IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. "  IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. "  IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7.   "  IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. "  IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. "  IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7.   "  IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. "  IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. "  IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7.   "  IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. "  IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. "  IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7.   "  IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL          ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. "    VCATCH             ,Vector catch flag" "No occurred,Occurred"
textline "                   "
eventfld.long 0x00 2. " DWTRAP            ,Data Watchpoint flag" "No match,Match"
textline "                   "
eventfld.long 0x00 1. " BKPT              ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. "       HALTED             ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "          REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA              ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA            ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. "       VC_HARDERR         ,Debug trap on a Hard Fault" "No error,Error"
textline "                   "
bitfld.long 0x04 0.  " VC_CORERESET      ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.     "              KEY  ,Key field" "No write,Write"
bitfld.long 0x00 0.     "  ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1     ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP      ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACMP (Analog Comparator Controller)"
base ad:0x400D0000
group.long 0x0++0xF
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
bitfld.long 0x0 4. "NEGSEL,Comparator0 Negative Input Select ." "0: VBG Bandgap reference voltage aaa 1.2V,1: VMID reference voltage aaa VCCA/2"
bitfld.long 0x0 1. "ACMPIE,CMP0 Interrupt Enable." "0: Disable CMP0 interrupt function,1: Enable CMP0 interrupt function"
bitfld.long 0x0 0. "ACMPEN,Comparator Enable." "0: Disable,1: Enable"
line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
bitfld.long 0x4 4. "NEGSEL,Comparator1 Negative Input Select ." "0: GPIOB[7],1: VBG Bandgap reference voltage aaa 1.2V"
bitfld.long 0x4 1. "ACMPIE,CMP1 Interrupt Enable." "0: Disable CMP1interrupt function,1: Enable CMP1 interrupt function"
bitfld.long 0x4 0. "ACMPEN,Comparator Enable." "0: Disable,1: Enable"
line.long 0x8 "ACMP_STATUS,Comparator Status Register"
bitfld.long 0x8 3. "ACMPO1,Comparator1 Output.Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP1EN aaa 0)." "0,1"
bitfld.long 0x8 2. "ACMPO0,Comparator0 Output.Synchronized to the APB clock to allow reading by software. Cleared when the comparator is disabled (CMP0EN aaa 0)." "0,1"
bitfld.long 0x8 1. "ACMPIF1,Compare 1 Flag.This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself." "0,1"
bitfld.long 0x8 0. "ACMPIF0,Compare 0 Flag.This bit is set by hardware whenever the comparator output changes state. This bit will cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself." "0,1"
line.long 0xC "ACMP_POSSEL,Comparator Select Register"
bitfld.long 0xC 0.--2. "POSSEL,Comparator0 GPIO Selection.GPIOB[POSSEL] is the active analog GPIO input selected to Comparator 0 positive input." "0,1,2,3,4,5,6,7"
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x400E0000
rgroup.long 0x0++0x3
line.long 0x0 "ADC_DAT,ADC FIFO Data Out"
hexmask.long.word 0x0 0.--15. 1. "RESULT,ADC Audio Data FIFO Read.A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with FIFOINTLV interrupt to determine if valid data is present in FIFO."
group.long 0x4++0x1B
line.long 0x0 "ADC_CHEN,ADC Enable Register"
bitfld.long 0x0 0. "CHEN,ADC Enable." "0: Conversion stopped and ADC is reset including..,1: ADC Conversion enabled"
line.long 0x4 "ADC_CLKDIV,ADC Clock Divider Register"
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,ADC Clock Divider .This register determines the clock division ration between the incoming ADC_CLK ( aaa HCLK by default) and the Delta-Sigma sampling clock of the ADC. This together with the over-sampling ratio (OVSPLRAT) determines the audio.."
line.long 0x8 "ADC_DCICTL,ADC Decimation Control Register"
hexmask.long.byte 0x8 16.--19. 1. "GAIN,CIC Filter Additional Gain.This should normally remain default 0. Can be set to non-zero values to provide additional digital gain from the decimation filter. An additional gain is applied to signal of GAIN/2."
hexmask.long.byte 0x8 0.--3. 1. "OVSPLRAT,Decimation Over-Sampling Ratio.This term determines the over-sampling ratio of the decimation filter. Valid values are:.0: OVSPLRAT aaa 64.1: OVSPLRAT aaa 128.2: OVSPLRAT aaa 192.3: OVSPLRAT aaa 384"
line.long 0xC "ADC_INTCTL,ADC Interrupt Control Register"
bitfld.long 0xC 31. "INTEN,Interrupt Enable.If set to '1' an interrupt is generated whenever FIFO level exceeds that set in FIFOINTLV." "0,1"
bitfld.long 0xC 0.--2. "FIFOINTLV,FIFO Interrupt Level.Determines at what level the ADC FIFO will generate a servicing interrupt to the CPU. Interrupt will be generated when number of words present in ADC FIFO is > FIFOINTLV." "0,1,2,3,4,5,6,7"
line.long 0x10 "ADC_PDMACTL,ADC PDMA Control Register"
bitfld.long 0x10 0. "RXDMAEN,Enable ADC PDMA Receive Channel .Enable ADC PDMA. If set  then ADC will request PDMA service when data is available." "0,1"
line.long 0x14 "ADC_CMP0,ADC Comparator 0 Control Register"
hexmask.long.word 0x14 16.--31. 1. "CMPDAT,Comparison Data.16 bit value to compare to FIFO output word."
hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count.When the A/D FIFO result matches the compare condition defined by CMPCOND  the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMCNT +1)  the CMPFLAG bit will be set."
newline
bitfld.long 0x14 7. "CMPFLAG,Compare Flag.When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self." "0,1"
bitfld.long 0x14 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches the value (CMPMCNT +1)  the CMPFLAG bit will be set." "0: Set the compare condition that result is less..,1: Set the compare condition that result is greater.."
newline
bitfld.long 0x14 1. "ADCMPIE,Compare Interrupt Enable.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT  CMPFLAG bit will be asserted  if ADCMPIE is set to 1  a compare interrupt request is generated." "0: Disable compare function interrupt,1: Enable compare function interrupt"
bitfld.long 0x14 0. "ADCMPEN,Compare Enable.Set this bit to 1 to enable compare CMPDAT with FIFO data output." "0: Disable compare,1: Enable compare"
line.long 0x18 "ADC_CMP1,ADC Comparator 0 Control Register"
hexmask.long.word 0x18 16.--31. 1. "CMPDAT,Comparison Data.16 bit value to compare to FIFO output word."
hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count.When the A/D FIFO result matches the compare condition defined by CMPCOND  the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMCNT +1)  the CMPFLAG bit will be set."
newline
bitfld.long 0x18 7. "CMPFLAG,Compare Flag.When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1 to self." "0,1"
bitfld.long 0x18 2. "CMPCOND,Compare Condition.Note: When the internal counter reaches the value (CMPMCNT +1)  the CMPFLAG bit will be set." "0: Set the compare condition that result is less..,1: Set the compare condition that result is greater.."
newline
bitfld.long 0x18 1. "ADCMPIE,Compare Interrupt Enable.If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT  CMPFLAG bit will be asserted  if ADCMPIE is set to 1  a compare interrupt request is generated." "0: Disable compare function interrupt,1: Enable compare function interrupt"
bitfld.long 0x18 0. "ADCMPEN,Compare Enable.Set this bit to 1 to enable compare CMPDAT with FIFO data output." "0: Disable compare,1: Enable compare"
tree.end
tree "ALC (Automatic Level Control)"
base ad:0x400B0048
group.long 0x0++0x3
line.long 0x0 "ALC_CTL,ALC Control Register"
bitfld.long 0x0 31. "PKLIMEN,ALC Peak Limiter Enable." "0: enable fast decrement when signal exceeds 87.5%..,1: disable fast decrement when signal exceeds 87.5%.."
bitfld.long 0x0 30. "PKSEL,ALC Gain Peak Detector Select." "0: use absolute peak value for ALC training (default),1: use peak-to-peak value for ALC training"
newline
bitfld.long 0x0 29. "NGPKSEL,ALC Noise Gate Peak Detector Select." "0: use peak-to-peak value for noise gate threshold..,1: use absolute peak value for noise gate threshold.."
bitfld.long 0x0 28. "ALCEN,ALC Select." "0: ALC disabled (default),1: ALC enabled"
newline
bitfld.long 0x0 25.--27. "MAXGAIN,ALC Maximum Gain." "0: -6.75 dB,1: -0.75 dB,2: +5.25 dB,3: +11.25 dB,4: +17.25 dB,5: +23.25 dB,6: +29.25 dB,7: +35.25 dB"
bitfld.long 0x0 22.--24. "MINGAIN,ALC Minimum Gain." "0: -12 dB,1: -6 dB,2: 0 dB,3: 6 dB,4: 12 dB,5: 18 dB,6: 24 dB,7: 30 dB"
newline
bitfld.long 0x0 21. "ZCEN,ALC Zero Crossing." "0: zero crossing disabled,1: zero crossing enabled"
hexmask.long.byte 0x0 17.--20. 1. "HOLDTIME,ALC Hold Time .(Value: 0~10). Hold Time aaa (2^HOLDTIME) ms"
newline
hexmask.long.byte 0x0 13.--16. 1. "TARGETLV,ALC Target Level."
bitfld.long 0x0 12. "MODESEL,ALC Mode." "0: ALC normal operation mode,1: ALC limiter mode"
newline
hexmask.long.byte 0x0 8.--11. 1. "DECAYSEL,ALC Decay Time .(Value: 0~10).When MODESEL aaa 0  Range: 125us to 128ms.When MODESEL aaa 1  Range: 31us to 32ms (time doubles with every step)"
hexmask.long.byte 0x0 4.--7. 1. "ATKSEL,ALC Attack Time .(Value: 0~10).When MODESEL aaa 0  Range: 500us to 512ms.When MODESEL aaa 1 Range: 125us to 128ms (Both ALC time doubles with every step)"
newline
bitfld.long 0x0 3. "NGEN,Noise Gate Enable." "0: Noise gate disabled,1: Noise gate enabled"
bitfld.long 0x0 0.--2. "NGTHBST,Noise Gate Threshold.Boost disabled: Threshold aaa (-81+6xNGTHBST) dB .Boost enabled: Threshold aaa (-87+6xNGTHBST) dB" "0,1,2,3,4,5,6,7"
rgroup.long 0x4++0x3
line.long 0x0 "ALC_STS,ALC status register"
hexmask.long.byte 0x0 11.--18. 1. "PEAKVAL,Peak Value.9 MSBs of measured absolute peak value"
hexmask.long.word 0x0 2.--10. 1. "P2PVAL,Peak-To-Peak Value.9 MSBs of measured peak-to-peak value"
newline
bitfld.long 0x0 1. "NOISEF,Noise Flag.Asserted when signal level is detected to be below NGTH" "0,1"
bitfld.long 0x0 0. "CLIPFLAG,Clipping Flag.Asserted when signal level is detected to be above 87.5% of full scale" "0,1"
group.long 0x8++0x7
line.long 0x0 "ALC_INTSTS,ALC interrupt register"
bitfld.long 0x0 0. "INTFLAG,ALC Interrupt.This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated  either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled..Write a 1 to this register to clear." "0,1"
line.long 0x4 "ALC_INTCTL,ALC interrupt enable register"
bitfld.long 0x4 0. "INTEN,ALC Interrupt Enable." "0: INTEN disabled,1: INTEN enabled"
tree.end
tree "ANA (Analog Functional Blocks)"
base ad:0x40080000
group.long 0x0++0x3
line.long 0x0 "ANA_VMID,VMID Reference Control Register"
bitfld.long 0x0 2. "PDHIRES,Power Down High (360kOhm) Resistance Reference." "0: Connect the High Resistance reference to VMID.,1: The High Resistance reference is disconnected.."
bitfld.long 0x0 1. "PDLORES,Power Down Low (4.8kOhm) Resistance Reference." "0: Connect the Low Resistance reference to VMID.,1: The Low Resistance reference is disconnected.."
newline
bitfld.long 0x0 0. "PULLDOWN,VMID Pulldown." "0: Release VMID pin for reference operation,1: Pull VMID pin to ground. Default power down and.."
group.long 0x8++0x7
line.long 0x0 "ANA_CURCTL0,Current Source Control Register"
bitfld.long 0x0 8.--9. "VALSEL,Current Source Value.Select master current for source generation." "0: 0.5 uA,1: 1 uA,2: 2.5 uA,3: 5 uA"
hexmask.long.byte 0x0 0.--7. 1. "CURSRCEN,Enable Current Source To GPIOB[X].Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source.."
line.long 0x4 "ANA_CURCTL1,Current Source Control Register 1"
hexmask.long.word 0x4 0.--15. 1. "CURSRCEN,Enable Current Source To GPIOB[X]  GPIOA[X-4].Individually enable current source to GPIO pins. Each GPIOB[11:0] and GPIOA[11:8] pin has a separate current source.."
group.long 0x20++0xF
line.long 0x0 "ANA_LDOSEL,LDO Voltage Select Register"
bitfld.long 0x0 0.--1. "LDOSEL,Select LDO Output Voltage.Note that maximum I/O pad operation speed only specified for voltage >2.4V. ." "0: 3.0V,1: 1.8V,2: 2.4V,3: 3.3V"
line.long 0x4 "ANA_LDOPD,LDO Power Down Register"
bitfld.long 0x4 1. "DISCHAR,Discharge." "0: No load on VD33,1: Switch discharge resistor to VD33"
bitfld.long 0x4 0. "PD,Power Down LDO.When powered down no current delivered to VD33.." "0: Enable LDO,1: Power Down"
line.long 0x8 "ANA_MICBSEL,Microphone Bias Select Register"
bitfld.long 0x8 2. "REFSEL,Select Reference Source For MICBIAS Generator.VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary  then noise performance can be sacrificed and bandgap voltage used as.." "0: VMID aaa VCCA/2 is reference source,1: VBG (bandgap voltage reference) is reference.."
bitfld.long 0x8 0.--1. "VOLSEL,Select Microphone Bias Voltage.MICBMODE aaa 0.0: 90% VCCA.1: 65% VCCA.2: 75% VCCA.3: 50% VCCA.MICBMODE aaa 1.0: 2.4V.1: 1.7V.2: 2.0V.3: 1.3V" "0: 2,1: 1,2: 2,3: 1"
line.long 0xC "ANA_MICBEN,Microphone Bias Enable Register"
bitfld.long 0xC 0. "MICBEN,Enable Microphone Bias Generator." "0: Powered Down,1: Enabled"
group.long 0x50++0x3
line.long 0x0 "ANA_MUXCTL,Analog Multiplexer Control Register"
bitfld.long 0x0 14. "MUXEN,Enable The Analog Multiplexer." "0: All channels disabled,1: Selection determined by register setting"
bitfld.long 0x0 13. "PGAINSEL,Select MICP/MICN To PGA Inputs" "0,1"
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bitfld.long 0x0 12. "PTATCUR,Select PTAT Current. I_PTAT  to PGA_INN  negative input to PGA  for temperature measurement." "0,1"
hexmask.long.byte 0x0 8.--11. 1. "POSINSEL,Selects Connection Of GPIOB[7 5 3 1] To PGA_INP  Positive Input Of PGA.1000b: GPIOB[7] connected to PGA_INP.0100b: GPIOB[5] connected to PGA_INP.0010b: GPIOB[3] connected to PGA_INP.0001b: GPIOB[1] connected to PGA_INP"
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hexmask.long.byte 0x0 0.--7. 1. "NEGINSEL,Selects Connection Of GPIOB[7:0] To PGA_INN  Negative Input Of PGA.If NEGINSEL[n] aaa 1 then GPIOB[n] is connected to PGA_INN."
group.long 0x60++0xB
line.long 0x0 "ANA_PGACTL,PGA Enable Register"
bitfld.long 0x0 3. "BSTGAIN,Boost Stage Gain Setting." "0: Gain aaa 0dB,1: Gain aaa 26dB"
bitfld.long 0x0 2. "PUBOOST,Power Up Control For Boost Stage Amplifier.This amplifier must be powered up for signal path operation.." "0: Power Down,1: Power up"
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bitfld.long 0x0 1. "PUPGA,Power Up Control For PGA Amplifier.This amplifier must be powered up for signal path operation.." "0: Power Down,1: Power up"
bitfld.long 0x0 0. "REFSEL,Select Reference For Analog Path.Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to VBG aaa 1.2V.." "0: Select VMID voltage as analog ground reference,1: Select Bandgap voltage as analog ground reference"
line.long 0x4 "ANA_SIGCTL,Signal Path Control Register"
bitfld.long 0x4 6. "MUTEBST,Boost Stage Mute Control." "0: Normal,1: Signal Muted"
bitfld.long 0x4 5. "MUTEPGA,PGA Mute Control." "0: Normal,1: Signal Muted"
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bitfld.long 0x4 4. "PUADCOP,Power Up ADC Sigma-Delta Modulator. This block must be powered up for ADC operation." "0: Power down,1: Power up"
bitfld.long 0x4 3. "PUCURB,Power Up Control For Current Bias Generation.This block must be powered up for signal path operation.." "0: Power down,1: Power up"
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bitfld.long 0x4 2. "PUBUFADC,Power Up Control For ADC Reference Buffer.This block must be powered up for signal path operation.." "0: Power down,1: Power up"
bitfld.long 0x4 1. "PUBUFPGA,Power Up Control For PGA Reference Buffer.This block must be powered up for signal path operation.." "0: Power down,1: Power up"
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bitfld.long 0x4 0. "PUZCDCMP,Power Up And Enable Control For Zero Cross Detect Comparator.When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal threshold. To operate ZCD the ALC peripheral clock (CLK_APBCLK0.BQALCKEN) must also be.." "0: Power down,1: Power up and enable zero cross detection"
line.long 0x8 "ANA_PGAGAIN,PGA Gain Select Register"
hexmask.long.byte 0x8 8.--13. 1. "GAINREAD,Current PGA Gain Value.Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA gain."
hexmask.long.byte 0x8 0.--5. 1. "GAINSET,Select The PGA Gain Setting.From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB."
group.long 0x84++0x3
line.long 0x0 "ANA_TRIM,Oscillator Trim Register"
hexmask.long.byte 0x0 16.--23. 1. "SUPERFINE,Superfine.The SUPERFINE trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE trim setting between the current setting and one setting above (values 1 127) or below (values -1  -128) the current trim.."
hexmask.long.byte 0x0 8.--15. 1. "COARSE,COARSE .Current COARSE range setting of the oscillator. Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "OSCTRIM,Oscillator Trim.Reads current oscillator trim setting. Read Only."
group.long 0x8C++0x3
line.long 0x0 "ANA_CAPSCTL,Capacitive Touch Sensing Control Register"
bitfld.long 0x0 31. "CAPSEN,Enable." "0: Disable/Reset block,1: Enable Block"
bitfld.long 0x0 30. "INTEN,Interrupt Enable." "0: Disable/Reset CAPS_IRQ interrupt,1: Enable CAPS_IRQ interrupt"
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bitfld.long 0x0 29. "RSTCNT,Reset Count.0: Release/Activate CAP_CNT.1: Set high to reset CAP_CNT." "0: Release/Activate CAP_CNT,1: Set high to reset CAP_CNT"
hexmask.long.byte 0x0 8.--15. 1. "CLKDIV,Reference Clock Divider.Circuit can be used to generate a reference clock output of SDCLK/2/(CLKDIV+1) instead of a Capacitive Touch Sensing reset signal."
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bitfld.long 0x0 5. "CLKMODE,Reference Clock Mode." "0: Capacitive Touch Sensing Mode,1: Circuit is in Reference clock generation mode"
bitfld.long 0x0 2.--4. "CYCLECNT,Number Of Relaxation Cycles.Peripheral performs 2^(CYCLECNT) relaxation cycles before generating interrupt." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--1. "LOWTIME,Output Low Time.Number of PCLK cycles to discharge external capacitor. ." "0: 1cycle,1: 2cycles,2: 8cycles,3: 16cycles"
rgroup.long 0x90++0x3
line.long 0x0 "ANA_CAPSCNT,Capacitive Touch Sensing Count Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPSCNT,Counter Read Back Value Of Capacitive Touch Sensing Block"
group.long 0x94++0x3
line.long 0x0 "ANA_FQMMCTL,Frequency Measurement Control Register"
bitfld.long 0x0 31. "FQMMEN,FQMMEN." "0: Disable/Reset block,1: Start Frequency Measurement"
hexmask.long.byte 0x0 16.--23. 1. "CYCLESEL,Frequency Measurement Cycles.Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us)  set CYCLESEL to 7  then measurement period would be 30.5175*(7+1)  244.1us."
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bitfld.long 0x0 2. "MMSTS,Measurement Done." "0: Measurement Ongoing,1: Measurement Complete"
bitfld.long 0x0 0.--1. "CLKSEL,Reference Clock Source.00b: OSC16K  .01b: OSC32K (default)  .1xb: I2S_WS - can be GPIOA[4 8 12] according to SYS_GPA_MFP register  configure I2S in SLAVE mode to enable." "0,1,2,3"
rgroup.long 0x98++0x3
line.long 0x0 "ANA_FQMMCNT,Frequency Measurement Count Register"
hexmask.long.word 0x0 0.--15. 1. "FQMMCNT,Frequency Measurement Count.When MMSTS aaa 1 and FQMMEN aaa 1  this is number of PCLK periods counted for frequency measurement..The frequency will be PCLK aaa FQMMCNT * Fref /(CYCLESEL+1) Hz.Maximum resolution of measurement is Fref.."
group.long 0x9C++0x3
line.long 0x0 "ANA_FQMMCYC,Frequency Measurement Cycle Register"
hexmask.long.tbyte 0x0 0.--23. 1. "FQMMCYC,Frequency Measurement Cycles. Number of reference clock periods plus one to measure target clock (PCLK)"
tree.end
tree "BIQ (Biquad Filter)"
base ad:0x400B0000
group.long 0x0++0x3B
line.long 0x0 "BIQ_COEFF0,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x0 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x4 "BIQ_COEFF1,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x4 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x8 "BIQ_COEFF2,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x8 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0xC "BIQ_COEFF3,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0xC 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x10 "BIQ_COEFF4,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x10 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x14 "BIQ_COEFF5,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x14 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x18 "BIQ_COEFF6,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x18 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x1C "BIQ_COEFF7,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x1C 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x20 "BIQ_COEFF8,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x20 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x24 "BIQ_COEFF9,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x24 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x28 "BIQ_COEFF10,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x28 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x2C "BIQ_COEFF11,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x2C 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x30 "BIQ_COEFF12,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x30 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x34 "BIQ_COEFF13,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x34 0.--31. 1. "COEFFDAT,Coefficient Data"
line.long 0x38 "BIQ_COEFF14,Coefficient b0 In H(z) Transfer Function.(3.16 format) - 1st stage BIQ Coefficients"
hexmask.long 0x38 0.--31. 1. "COEFFDAT,Coefficient Data"
group.long 0x40++0x3
line.long 0x0 "BIQ_CTL,BIQ Control Register"
hexmask.long.word 0x0 16.--28. 1. "SRDIV,Sample Rate Divider.This register is used to program the operating sampling rate of the biquad filter. The sample rate is defined as.HCLK/(SRDIV+1). .Default to 3071 so the sampling rate is 16K when HCLK is 49.152MHz."
bitfld.long 0x0 4.--6. "DPWMPUSR,DPWM Path Up Sample Rate (From SRDIV Result).This register is only used when PATHSEL is set to 1. The operating sample rate for the biquad filter will be.(DPWMPUSR+1)*HCLK/(SRDIV+1)..Default value for this register is 3." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 3. "DLCOEFF,Move BIQ Out Of Reset State ." "0: BIQ filter is in reset state,1: When this bit is on the default coefficients.."
bitfld.long 0x0 2. "PRGCOEFF,Programming Mode Coefficient Control Bit.This bit must be turned off when BIQEN in on." "0: Coefficient RAM is in normal mode,1: coefficient RAM is under programming mode"
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bitfld.long 0x0 1. "PATHSEL,AC Path Selection For BIQ." "0: used in ADC path,1: used in DPWM path"
bitfld.long 0x0 0. "BIQEN,BIQ Filter Start To Run." "0: BIQ filter is not processing,1: BIQ filter is on"
tree.end
tree "BOD (Brown-out Detector)"
base ad:0x40084000
group.long 0x0++0x13
line.long 0x0 "BODTALM_BODSEL,Brown Out Detector Select Register"
bitfld.long 0x0 4. "BODRANGE,Range.Range setting for BODVL" "0,1"
bitfld.long 0x0 3. "BODHYS,BOD Hysteresis ." "0: Hysteresis Disabled,1: Enable Hysteresis of BOD detection"
bitfld.long 0x0 0.--2. "BODVL,BOD Voltage Level.RANGE aaa 0 .111b aaa 4.6V.110b aaa 3.0V.101b aaa 2.8V.100b aaa 2.65V.011b aaa 2.5V.010b aaa 2.4V.001b aaa 2.2V.000b aaa 2.1V.RANGE aaa 1.111b aaa 4.2V.110b aaa 3.9V.101b aaa 3.8V.100b aaa 3.7V.011b aaa 3.6V.010b aaa 3.4V.001b aaa.." "0,1,2,3,4,5,6,7"
line.long 0x4 "BODTALM_BODCTL,Brown Out Detector Enable Register"
bitfld.long 0x4 4. "BODOUT,Output Of BOD Detection Block.This signal can be monitored to determine the current state of the BOD comparator. BODOUT aaa 1 implies that VCC is less than BODVL." "0,1"
bitfld.long 0x4 3. "BODIF,Current Status Of Interrupt." "0,1"
bitfld.long 0x4 2. "BODINTEN,BOD Interrupt Enable." "0: Disable BOD Interrupt,1: Enable BOD Interrupt"
bitfld.long 0x4 0.--1. "BODEN,BOD Enable.1xb aaa Enable continuous BOD detection..01b aaa Enable time multiplexed BOD detection. See BODTALM_BODDTMR register..00b aaa Disable BOD Detection." "0,1,2,3"
line.long 0x8 "BODTALM_TALMSEL,Temperature Alarm Select Register"
hexmask.long.byte 0x8 0.--3. 1. "TALMVL,Temperature Alarm Sense Level.0000:105C.0001:115C.0010:125C.0100:135C.1000:145C"
line.long 0xC "BODTALM_TALMCTL,Temperature Alarm Enable Register"
bitfld.long 0xC 3. "TALMIF,Current Status Of Interrupt.Latched whenever a Temperature Sense event occurs and IE aaa 1. Write '1' to clear." "0,1"
bitfld.long 0xC 2. "TALMIEN,TALARM Interrupt Enable." "0: Disable TALARM Interrupt,1: Enable TALARM Interrupt"
bitfld.long 0xC 1. "TALMOUT,Output Of TALARM Block.Can be polled to determine whether TALARM active (be 1)." "0,1"
bitfld.long 0xC 0. "TALMEN,TALARM Enable." "0: Disable TALARM Detection,1: Enable TALARM Detection"
line.long 0x10 "BODTALM_BODDTMR,Brown Out Detector Timer Register"
hexmask.long.byte 0x10 16.--19. 1. "DURTON,Time BOD Detector Is Active.(DURTON+1) * 100us. Minimum value is 1. (default is 400us)"
hexmask.long.word 0x10 0.--15. 1. "DURTOFF,Time BOD Detector Is Off. (DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)"
tree.end
tree "CLK (Clock Control)"
base ad:0x50000200
group.long 0x0++0x2B
line.long 0x0 "CLK_PWRCTL,System Power Control Register"
hexmask.long.byte 0x0 28.--31. 1. "WKTMRSTS,Current Wakeup Timer Setting.Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode."
bitfld.long 0x0 26. "PORWKF,POR Wakeup Flag.Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered." "0,1"
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bitfld.long 0x0 25. "TMRWKF,Timer Wakeup Flag.Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 16Khz oscillator. Flag is cleared when DPD mode is entered." "0,1"
bitfld.long 0x0 24. "WKPINWKF,Pin Wakeup Flag.Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "SELWKTMR,Select Wakeup Timer.SELWKTMR[0] aaa 1: WAKEUP after 128 OSC16K clocks (12.8 ms).SELWKTMR[1] aaa 1: WAKEUP after 256 OSC16K clocks (25.6 ms).SELWKTMR[2] aaa 1: WAKEUP after 512 OSC16K clocks (51.2 ms).SELWKTMR[3] aaa 1: WAKEUP after 1024 OSC16K.."
bitfld.long 0x0 17. "LIRCDPDEN,OSC16K Enabled Control.Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled  device cannot wake from DPD with SELWKTMR delay.." "0: enabled,1: disabled"
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bitfld.long 0x0 16. "WKPINEN,Wakeup Pin Enabled Control.Determines whether WAKEUP pin is enabled in DPD mode.." "0: enabled,1: disabled"
bitfld.long 0x0 11. "DPDEN,Deep Power Down (DPD) Bit.Set to '1' and issue WFI/WFE instruction to enter DPD mode." "0,1"
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bitfld.long 0x0 10. "SPDEN,Standby Power Down (SPD) Bit.Set to '1' and issue WFI/WFE instruction to enter SPD mode." "0,1"
bitfld.long 0x0 9. "STOP,Stop.RESERVED - do not set to '1'" "0,1"
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bitfld.long 0x0 3. "LIRCEN,OSC16K Oscillator Enable Bit." "0: disable,1: enable (default)"
bitfld.long 0x0 2. "HIRCEN,OSC49M Oscillator Enable Bit." "0: disable,1: enable (default)"
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bitfld.long 0x0 1. "LXTEN,External 32.768 KHz Crystal Enable Bit." "0: disable (default),1: enable"
line.long 0x4 "CLK_AHBCLK,AHB Device Clock Enable Control Register"
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Control." "0: To disable the Flash ISP engine clock,1: To enable the Flash ISP engine clock"
bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Control." "0: To disable the PDMA engine clock,1: To enable the PDMA engine clock"
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bitfld.long 0x4 0. "HCLKEN,CPU Clock Enable (HCLK).Must be left as '1' for normal operation." "0,1"
line.long 0x8 "CLK_APBCLK0,APB Device Clock Enable Control Register"
bitfld.long 0x8 31. "PWM1CH01CKEN,PWM1CH0 And PWM1CH1 Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 30. "ANACKEN,Analog Block Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 29. "I2S0CKEN,I2S Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 28. "ADCCKEN,Audio Analog-Digital-Converter (ADC) Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 26. "SBRAMCKEN,Standby RAM Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 22. "ACMPCKEN,Analog Comparator Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 21. "PWM0CH23CKEN,PWM0CH2 And PWM0CH3 Block Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 20. "PWM0CH01CKEN,PWM0CH0 And PWM0CH1 Block Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 19. "CRCCKEN,Cyclic Redundancy Check Block Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 18. "BFALCKEN,Biquad Filter And Automatic Level Control Block Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 16. "UARTCKEN,UART Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 13. "DPWMCKEN,Differential PWM Speaker Driver Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 7. "TMR1CKEN,Timer1 Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x8 6. "TMR0CKEN,Timer0 Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x8 5. "RTCCKEN,Real-Time-Clock APB Interface Clock Control." "0: Disable,1: Enable"
bitfld.long 0x8 4. "WDTCKEN,Watchdog Clock Enable Control." "0: Disable,1: Enable"
line.long 0xC "CLK_DPDSTATE,Deep Power Down State Register"
hexmask.long.byte 0xC 8.--15. 1. "DPDSTSRD,DPD State Read Back.Read back of CLK_DPDSTATE register. This register was preserved from last DPD event ."
hexmask.long.byte 0xC 0.--7. 1. "DPDSTSWR,DPD State Write.To set the CLK_DPDSTATE register  write value to this register. Data is latched on next DPD event."
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 6.--7. "HIRCFSEL,OSC48M Frequency Select.Determines which trim setting to use for OSC48M internal oscillator. Oscillator is factory trimmed within 1% to:.0: 49.152MHz (Default).1: 32.768MHz.2: 36.864MHz" "0: 49,1: 32,2: 36,?"
bitfld.long 0x10 3.--5. "STCLKSEL,MCU Cortex_M0 SYST Clock Source Select.These bits are protected  to write to bits first perform the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL)).000 aaa clock source from 16kHz internal clock .001 aaa clock source.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Select.Ensure that related clock sources (pre-select and new-select) are enabled before updating register..These bits are protected  to write to bits first perform the unlock sequence (see Protected Register Lock Key Register.." "0,1,2,3,4,5,6,7"
line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 30.--31. "PWM0CH23CKSEL,PWM0CH2 And PWM0CH3 Clock Source Select.PWM0CH2 and PWM0CH3 uses the same clock source  and pre-scaler." "0: clock source from internal 16kHz oscillator,1: clock source from external 32kHz crystal clock,?,?"
bitfld.long 0x14 28.--29. "PWM0CH01CKSEL,PWM0CH0 And PWM0CH1 Clock Source Select.PWM0CH0 and PWM0CH1 uses the same clock source  and pre-scaler." "0: clock source from internal 16kHz oscillator,1: clock source from external 32kHz crystal clock,?,?"
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bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Select.000 aaa clock source from internal 16kHz oscillator.001 aaa clock source from external 32kHz crystal clock.010 aaa clock source from HCLK.011 aaa clock source from external pin (GPIOA[15]).1xx aaa clock source from.." "0,1,2,3,4,5,6,7"
bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Select.000 aaa clock source from internal 16kHz oscillator.001 aaa clock source from external 32kHz crystal clock.010 aaa clock source from HCLK.011 aaa clock source from external pin (GPIOA[14]).1xx aaa clock source from.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4. "DPWMCKSEL,Differential Speaker Driver PWM Clock Source Select." "0: OSC48M clock,1: 2x OSC48M clock"
bitfld.long 0x14 0.--1. "WDTSEL,WDT Clock Source Select." "0: clock source from internal OSC48M oscillator clock,1: clock source from external 32kHz crystal clock,?,?"
line.long 0x18 "CLK_CLKDIV0,Clock Divider Number Register"
hexmask.long.byte 0x18 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source.The ADC clock frequency aaa (ADC clock source frequency ) / (ADC_N + 1)"
hexmask.long.byte 0x18 8.--11. 1. "UARTDIV,UART Clock Divide Number From UART Clock Source.The UART clock frequency aaa (UART clock source frequency ) / (UART_N + 1)"
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hexmask.long.byte 0x18 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source.The HCLK clock frequency aaa (HCLK clock source frequency) / (HCLK_N + 1)"
line.long 0x1C "CLK_CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x1C 4.--5. "PWM1CH01CKSEL,PWM1CH0 And PWM1CH1 Clock Source Select.PWM1CH0 and PWM1CH1 uses the same clock source  and pre-scaler." "0: clock source from internal 16kHz oscillator,1: clock source from external 32kHz crystal clock,?,?"
bitfld.long 0x1C 0.--1. "I2S0SEL,I2S0 Clock Source Select." "0: clock source from internal 16kHz oscillator,1: clock source from external 32kHz crystal clock,?,?"
line.long 0x20 "CLK_SLEEPCTL,Sleep Clock Source Select Register"
bitfld.long 0x20 31. "PWM1CH01CKEN,PWM1CH0 And PWM1CH1 Block Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 30. "ANACKEN,Analog Block Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 29. "I2SCKEN,I2S Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 28. "ADCCKEN,Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 26. "SBRAMCKEN,Standby RAM Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 22. "ACMPCKEN,Analog Comparator Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 21. "PWM0CH23CKEN,PWM0CH2 And PWM0CH3 Block Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 20. "PWM0CH01CKEN,PWM0CH0 And PWM0CH1 Block Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 19. "CRCCKEN,Cyclic Redundancy Check Sleep Block Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 18. "BQALCKEN,Biquad Filter/ALC Block Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 16. "UARTCKEN,UART Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 13. "DPWMCKEN,Differential PWM Speaker Driver Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 12. "SPI0CKEN,SPI0 Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 8. "I2C0CKEN,I2C0 Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 7. "TMR1CKEN,Timer1 Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 6. "TMR0CKEN,Timer0 Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 5. "RTCCKEN,Real-Time- Sleep Clock APB Interface Clock Control." "0: Disable,1: Enable"
bitfld.long 0x20 4. "WDTCKEN,Watchdog Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 2. "ISPCKEN,Flash ISP Controller Sleep Clock Enable Control." "0: Disable,1: Enable"
bitfld.long 0x20 1. "PDMACKEN,PDMA Controller Sleep Clock Enable Control." "0: Disable,1: Enable"
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bitfld.long 0x20 0. "HCLKCKEN,CPU Clock Sleep Enable (HCLK).Must be left as '1' for normal operation.." "0: Disable,1: Enable"
line.long 0x24 "CLK_PWRSTSF,Power State Flag Register"
bitfld.long 0x24 2. "SPDF,Powered Down Flag.This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag." "0,1"
bitfld.long 0x24 1. "STOPF,Stop Flag.This flag is set if core logic was stopped but not powered down. Write '1' to clear flag." "0,1"
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bitfld.long 0x24 0. "DSF,Deep Sleep Flag.This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag." "0,1"
line.long 0x28 "CLK_DBGPD,Debug Port Power Down Disable Register"
bitfld.long 0x28 7. "ICEDATST,ICEDATST Pin State.Read Only. Current state of ICE_DAT pin." "0,1"
bitfld.long 0x28 6. "ICECLKST,ICECLKST Pin State.Read Only. Current state of ICE_CLK pin." "0,1"
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bitfld.long 0x28 0. "DISPDREQ,Disable Power Down." "0: Enable power down requests,1: Disable power down requests"
tree.end
tree "DPWM (Differential Audio PWM Output)"
base ad:0x40070000
group.long 0x0++0x3
line.long 0x0 "DPWM_CTL,DPWM Control Register"
bitfld.long 0x0 6. "DPWMEN,DPWM Enable." "0: Disable DPWM SPK pins are tri-state CIC filter..,1: Enable DPWM SPK pins are enabled and driven data.."
bitfld.long 0x0 4.--5. "DITHEREN,DPWM Signal Dither Control.To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither:." "0: No dither,1: +/- 1 bit dither,?,3: +/- 2 bit dither"
bitfld.long 0x0 3. "DEADTIME,DPWM Driver Deadtime Control.Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors." "0,1"
bitfld.long 0x0 0.--2. "MODUFRQ,DPWM Modulation Frequency.This parameter controls the carrier modulation frequency of the PWM signal as a proportion of DPWM_CLK..MODUFRQ : DPWM_CLK Division : Frequency for DPWM_CLK aaa 98.304MHZ.0 : 228.." "?,?,?,?,?,?,?,?"
rgroup.long 0x4++0x3
line.long 0x0 "DPWM_STS,DPWM DATA FIFO Status Register"
bitfld.long 0x0 1. "EMPTY,FIFO Empty." "0: FIFO is not empty,1: FIFO is empty"
bitfld.long 0x0 0. "FULL,FIFO Full." "0: FIFO is not full,1: FIFO is full"
group.long 0x8++0x3
line.long 0x0 "DPWM_DMACTL,DPWM PDMA Control Register"
bitfld.long 0x0 0. "DMAEN,Enable DPWM DMA Interface." "0: Disable PDMA. No requests will be made to PDMA..,1: Enable PDMA. Block will request data from PDMA.."
wgroup.long 0xC++0x3
line.long 0x0 "DPWM_DATA,DPWM DATA FIFO Input"
hexmask.long.word 0x0 0.--15. 1. "INDATA,DPWM FIFO Audio Data Input.A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to."
group.long 0x10++0x3
line.long 0x0 "DPWM_ZOHDIV,DPWM Zero Order Hold Division Register"
hexmask.long.byte 0x0 0.--7. 1. "ZOHDIV,DPWM Zero Order Hold  Down-Sampling Divisor.The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula: .Fs aaa HCLK/ZOHDIV/64.Valid range is 1 to 255. Default is 48  which gives a.."
tree.end
tree "FMC (Flash Memory Control)"
base ad:0x5000C000
group.long 0x0++0x13
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x0 21. "CACHEDIS,Cache Disable.When set to 1  caching of flash memory reads is disabled." "0,1"
bitfld.long 0x0 16.--18. "WAITCFG,Flash Access Wait State Configuration.For M and H speed grade parts this sets the access speed to the flash memory..0x00: Three wait states. HCLK > 72MHz.0x01: Two wait states. 72MHz > HCLK > 50MHz.0x02: One wait state. HCLK <aaa 50MHz.Before.." "0: Three wait states,1: Two wait states,2: One wait state,?,?,?,?,?"
bitfld.long 0x0 7. "SWRST,Software Reset.Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset." "0,1"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag.This bit is set by hardware when a triggered ISP meets any of the following conditions:.(1) APROM writes to itself..(2) LDROM writes to itself. .(3) Destination address is illegal  such as over an available range..Write 1 to clear." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable.LDROM update enable bit. ." "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable. When enabled  ISP functions can access the CONFIG address space and modify device configuration area." "0: Disable,1: Enable"
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bitfld.long 0x0 1. "BS,Boot Select .Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag  which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0;.." "0: APROM,1: LDROM"
bitfld.long 0x0 0. "ISPEN,ISP Enable." "0: Disable ISP function,1: Enable ISP function"
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address Register.This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only  consequently ISPADDR [1:0] must be 00b for correct ISP operation."
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data Register.Write data to this register before an ISP program operation..Read data from this register after an ISP read operation"
line.long 0xC "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP Command .Operation Mode : CMD.Standby : 0x3X.Read : 0x00.Program : 0x21.Page Erase : 0x22.Read CID : 0x0B.Read DID : 0x0C"
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger.Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished..After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee.." "0: ISP operation is finished,1: ISP is on going"
rgroup.long 0x14++0x3
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address.This register reports the data flash starting address. It is a read only register..Data flash size is defined by user configuration; register content is loaded from Config1 when chip is reset."
tree.end
tree "GPIO (General Purpose I/Os)"
base ad:0x50004000
group.long 0x0++0xF
line.long 0x0 "PA_MODE,GPIO Port A Pin I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
line.long 0x4 "PA_DINOFF,GPIO Port A Pin Input Disable"
hexmask.long.word 0x4 16.--31. 1. "DINOFF,GPIOx Pin[N] OFF Digital Input Path Enable."
line.long 0x8 "PA_DOUT,GPIO Port A Data Output Value"
hexmask.long.word 0x8 0.--15. 1. "DOUT,Px Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output  open-drain or quasi-bidirectional mode.."
line.long 0xC "PA_DATMSK,GPIO Port A Data Output Write Mask"
hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Data Output Write Mask.These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to '1'  the corresponding DOUTn bit is writing protected. ."
rgroup.long 0x10++0x3
line.long 0x0 "PA_PIN,GPIO Port A Pin Value"
hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin Values.The value read from each of these bit reflects the actual status of the respective GPIO pin"
group.long 0x14++0xF
line.long 0x0 "PA_DBEN,GPIO Port A De-bounce Enable"
hexmask.long.word 0x0 0.--15. 1. "DBEN,Port [A/B] De-Bounce Enable Control.DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated  input signal must be valid for two consecutive de-bounce periods. The de-bounce time is.."
line.long 0x4 "PA_INTTYPE,GPIO Port A Interrupt Trigger Type"
hexmask.long.word 0x4 0.--15. 1. "TYPE,Port [A/B] Edge Or Level Detection Interrupt Trigger Type.TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered  edge de-bounce is controlled by the DBEN register. If the.."
line.long 0x8 "PA_INTEN,GPIO Port A Interrupt Enable"
hexmask.long.word 0x8 16.--31. 1. "RHIEN,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High.RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function..If the interrupt is configured in level.."
hexmask.long.word 0x8 0.--15. 1. "FLIEN,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low.FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function..If the interrupt is configured in level.."
line.long 0xC "PA_INTSRC,GPIO Port A Interrupt Source Flag"
hexmask.long.word 0xC 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag.Read :.1 aaa Indicates GPIOx[n] generated an interrupt.0 aaa No interrupt from GPIOx[n].Write :.1 aaa Clear the corresponding pending interrupt..0 aaa No action"
group.long 0x40++0xF
line.long 0x0 "PB_MODE,GPIO Port A Pin I/O Mode Control"
bitfld.long 0x0 30.--31. "MODE15,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 28.--29. "MODE14,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 26.--27. "MODE13,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 24.--25. "MODE12,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 22.--23. "MODE11,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 20.--21. "MODE10,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 18.--19. "MODE9,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 16.--17. "MODE8,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 14.--15. "MODE7,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Px I/O Pin[N] Mode Control .Determine each I/O type of GPIOx pins." "0: GPIO port [n] pin is in INPUT mode,1: GPIO port [n] pin is in OUTPUT mode,?,?"
line.long 0x4 "PB_DINOFF,GPIO Port A Pin Input Disable"
hexmask.long.word 0x4 16.--31. 1. "DINOFF,GPIOx Pin[N] OFF Digital Input Path Enable."
line.long 0x8 "PB_DOUT,GPIO Port A Data Output Value"
hexmask.long.word 0x8 0.--15. 1. "DOUT,Px Pin[N] Output Value.Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output  open-drain or quasi-bidirectional mode.."
line.long 0xC "PB_DATMSK,GPIO Port A Data Output Write Mask"
hexmask.long.word 0xC 0.--15. 1. "DATMSK,Port [A/B] Data Output Write Mask.These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to '1'  the corresponding DOUTn bit is writing protected. ."
rgroup.long 0x50++0x3
line.long 0x0 "PB_PIN,GPIO Port A Pin Value"
hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin Values.The value read from each of these bit reflects the actual status of the respective GPIO pin"
group.long 0x54++0xF
line.long 0x0 "PB_DBEN,GPIO Port A De-bounce Enable"
hexmask.long.word 0x0 0.--15. 1. "DBEN,Port [A/B] De-Bounce Enable Control.DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated  input signal must be valid for two consecutive de-bounce periods. The de-bounce time is.."
line.long 0x4 "PB_INTTYPE,GPIO Port A Interrupt Trigger Type"
hexmask.long.word 0x4 0.--15. 1. "TYPE,Port [A/B] Edge Or Level Detection Interrupt Trigger Type.TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered  edge de-bounce is controlled by the DBEN register. If the.."
line.long 0x8 "PB_INTEN,GPIO Port A Interrupt Enable"
hexmask.long.word 0x8 16.--31. 1. "RHIEN,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High.RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function..If the interrupt is configured in level.."
hexmask.long.word 0x8 0.--15. 1. "FLIEN,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low.FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function..If the interrupt is configured in level.."
line.long 0xC "PB_INTSRC,GPIO Port A Interrupt Source Flag"
hexmask.long.word 0xC 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag.Read :.1 aaa Indicates GPIOx[n] generated an interrupt.0 aaa No interrupt from GPIOx[n].Write :.1 aaa Clear the corresponding pending interrupt..0 aaa No action"
group.long 0x180++0x3
line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control"
bitfld.long 0x0 5. "ICLKON,Interrupt Clock On Mode.Set this bit '0' will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.." "0: disable the clock if the GPIOx[n] interrupt is..,1: Interrupt generation clock always active"
bitfld.long 0x0 4. "DBCLKSRC,De-Bounce Counter Clock Source Select." "0: De-bounce counter clock source is HCLK,1: De-bounce counter clock source is the internal.."
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-Bounce Sampling Cycle Selection .For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce clocks. For example if DBCLKSRC aaa 6  then interrupt is sampled every 2^6 aaa 64 de-bounce clocks. If DBCLKSRC is 16KHz oscillator.."
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x40020000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL,I2C Control Register"
bitfld.long 0x0 7. "INTEN,Enable Interrupt." "0: Disable interrupt,1: Enable interrupt CPU"
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit.Set to enable I2C serial function block." "0: Disable,1: Enable"
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bitfld.long 0x0 5. "STA,I2C START Control Bit.Setting STA to logic 1 will enter master mode  the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit.In master mode  set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition  when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode  setting STO resets I2C.." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag.When a new SIO state is present in the I2C_STATUS register  the SI flag is set by hardware  and if bit EI (I2C_CTL[7]) is set  the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit.1. A slave is acknowledging the address sent from master  .2. The receiver devices are acknowledging the data sent by transmitter. .When AA aaa 0 prior to address or data received  a Not acknowledged (high level to SDA).." "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave address Register0"
hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode  the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
bitfld.long 0x4 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x8 "I2C_DAT,I2C DATA Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data Register.During master or slave transmit mode  data to be transmitted is written to this register. During master or slave receive mode  data that has been received may be read from this register."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Register.The status register of I2C:.The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2C_STATUS contains F8H  no serial interrupt is.."
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C clock divided Register"
hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided Register.The I2C clock rate bits: Data Baud Rate of I2C aaa PCLK /(4x(I2C_CLKDIV+1))."
line.long 0x4 "I2C_TOCTL,I2C Time out control Register"
bitfld.long 0x4 2. "TOCEN,Time-Out Counter Control Bit.When enabled  the 14 bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared." "0: Disable,1: Enable"
bitfld.long 0x4 1. "TOCDIV4,Time-Out Counter Input Clock Divide By 4 .When enabled  the time-out clock is PCLK/4." "0: Disable,1: Enable"
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bitfld.long 0x4 0. "TOIF,Time-Out Flag." "0: No time-out,1: Time-out flag is set by H/W. It can interrupt.."
line.long 0x8 "I2C_ADDR1,I2C Slave address Register0"
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode  the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
bitfld.long 0x8 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
line.long 0xC "I2C_ADDR2,I2C Slave address Register0"
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode  the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
bitfld.long 0xC 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x10 "I2C_ADDR3,I2C Slave address Register0"
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address Register.The content of this register is irrelevant when I2C is in master mode. In the slave mode  the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if any of the addresses are matched."
bitfld.long 0x10 0. "GC,General Call Function." "0: Disable General Call Function,1: Enable General Call Function"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave address Mask Register0"
bitfld.long 0x14 7. "ADDRMSKx7,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x14 6. "ADDRMSKx6,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x14 5. "ADDRMSKx5,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x14 4. "ADDRMSKx4,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x14 3. "ADDRMSKx3,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x14 2. "ADDRMSKx2,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x14 1. "ADDRMSKx1,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
line.long 0x18 "I2C_ADDRMSK1,I2C Slave address Mask Register0"
bitfld.long 0x18 7. "ADDRMSKx7,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x18 6. "ADDRMSKx6,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x18 5. "ADDRMSKx5,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x18 4. "ADDRMSKx4,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x18 3. "ADDRMSKx3,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x18 2. "ADDRMSKx2,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x18 1. "ADDRMSKx1,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
line.long 0x1C "I2C_ADDRMSK2,I2C Slave address Mask Register0"
bitfld.long 0x1C 7. "ADDRMSKx7,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x1C 6. "ADDRMSKx6,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x1C 5. "ADDRMSKx5,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x1C 4. "ADDRMSKx4,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x1C 3. "ADDRMSKx3,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x1C 2. "ADDRMSKx2,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x1C 1. "ADDRMSKx1,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
line.long 0x20 "I2C_ADDRMSK3,I2C Slave address Mask Register0"
bitfld.long 0x20 7. "ADDRMSKx7,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x20 6. "ADDRMSKx6,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x20 5. "ADDRMSKx5,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x20 4. "ADDRMSKx4,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x20 3. "ADDRMSKx3,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
bitfld.long 0x20 2. "ADDRMSKx2,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
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bitfld.long 0x20 1. "ADDRMSKx1,I2C Address Mask Register.I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison." "0: Mask disable,1: Mask enable (the received corresponding address.."
tree.end
tree "I2S (Inter-IC Sound)"
base ad:0x400A0000
group.long 0x0++0xF
line.long 0x0 "I2S_CTL,I2S Control Register"
bitfld.long 0x0 21. "RXPDMAEN,Enable Receive DMA.When RX DMA is enabled  I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.." "0: Disable RX DMA,1: Enable RX DMA"
bitfld.long 0x0 20. "TXPDMAEN,Enable Transmit DMA.When TX DMA is enables  I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.." "0: Disable TX DMA,1: Enable TX DMA"
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bitfld.long 0x0 19. "RXCLR,Clear Receive FIFO.Write 1 to clear receive FIFO  internal pointer is reset to FIFO start point  and I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty..This bit is cleared by hardware automatically when clear operation complete." "0,1"
bitfld.long 0x0 18. "TXCLR,Clear Transmit FIFO.Write 1 to clear transmit FIFO  internal pointer is reset to FIFO start point  and I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed. .This bit is cleared by hardware.." "0,1"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detect Enable.If this bit is set to 1  when left channel data sign bit changes  or data bits are all zero  the LZCIF flag in I2S_STATUS register will be set to 1. ." "0: Disable left channel zero cross detect,1: Enable left channel zero cross detect"
bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detect Enable.If this bit is set to 1  when right channel data sign bit changes  or data bits are all zero  the RZCIF flag in I2S_STATUS register will be set to 1. ." "0: Disable right channel zero cross detect,1: Enable right channel zero cross detect"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable.The ISD9160 can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous  then data will be periodically corrupted. Software needs to implement a way to.." "0: Disable master clock,1: Enable master clock"
bitfld.long 0x0 12.--14. "RXTH,Receive FIFO Threshold Level.When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set. ." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 9.--11. "TXTH,Transmit FIFO Threshold Level.If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8. "SLAVE,Slave Mode.I2S can operate as a master or slave. For master mode  I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from ISD9160. In slave mode  I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "FORMAT,Data Format.See Figure 561 and Figure 562 for timing differences." "0: I2S data format,1: MSB justified data format"
bitfld.long 0x0 6. "MONO,Monaural Data.This parameter sets whether mono or stereo data is processed. See Figure 563 for details of how data is formatted in transmit and receive FIFO.." "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width.This parameter sets the word width of audio data. See Figure 563 for details of how data is formatted in transmit and receive FIFO.." "0: data is 8 bit,1: data is 16 bit,?,?"
bitfld.long 0x0 3. "MUTE,Transmit Mute Enable." "0: Transmit data is shifted from FIFO,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable." "0: Disable data receive,1: Enable data receive"
bitfld.long 0x0 1. "TXEN,Transmit Enable." "0: Disable data transmit,1: Enable data transmit"
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bitfld.long 0x0 0. "I2SEN,Enable I2S Controller." "0: Disable,1: Enable"
line.long 0x4 "I2S_CLKDIV,I2S Clock Divider Register"
hexmask.long.byte 0x4 8.--15. 1. "BCLKDIV,Bit Clock Divider.If I2S operates in master mode  bit clock is provided by ISD9160. Software can program these bits to generate bit clock frequency for the desired sample rate..For sample rate Fs  the desired bit clock frequency is:.F(BCLK) aaa.."
bitfld.long 0x4 0.--2. "MCLKDIV,Master Clock Divider.ISD9160 can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0  MCLK is the same as I2S_CLKDIV clock input  otherwise MCLK frequency is given by:.F(MCLK) aaa F(I2S_CLKDIV) /.." "0,1,2,3,4,5,6,7"
line.long 0x8 "I2S_IEN,I2S Interrupt Enable Register"
bitfld.long 0x8 12. "LZCIEN,Left Channel Zero Cross Interrupt Enable.Interrupt will occur if this bit is set to 1 and left channel has zero cross event." "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x8 11. "RZCIEN,Right Channel Zero Cross Interrupt Enable.Interrupt will occur if this bit is set to 1 and right channel has zero cross event." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable.Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].." "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x8 9. "TXOVIEN,Transmit FIFO Overflow Interrupt Enable.Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 8. "TXUDIEN,Transmit FIFO Underflow Interrupt Enable.Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.." "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x8 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt.Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].." "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x8 1. "RXOVIEN,Receive FIFO Overflow Interrupt Enable." "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x8 0. "RXUDIEN,Receive FIFO Underflow Interrupt Enable.If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1. ." "0: Disable interrupt,1: Enable interrupt"
line.long 0xC "I2S_STATUS,I2S Status Register"
hexmask.long.byte 0xC 28.--31. 1. "TXCNT,Transmit FIFO Level (Read Only)."
hexmask.long.byte 0xC 24.--27. 1. "RXCNT,Receive FIFO Level (Read Only)."
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bitfld.long 0xC 23. "LZCIF,Left Channel Zero Cross Flag (Write '1' To Clear  Or Clear LZCEN)." "0: No zero cross detected,1: Left channel zero cross is detected"
bitfld.long 0xC 22. "RZCIF,Right Channel Zero Cross Flag (Write '1' To Clear  Or Clear RZCEN)." "0: No zero cross,1: Right channel zero cross is detected"
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rbitfld.long 0xC 21. "TXBUSY,Transmit Busy (Read Only).This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register. ." "0: Transmit shift register is empty,1: Transmit shift register is busy"
rbitfld.long 0xC 20. "TXEMPTY,Transmit FIFO Empty (Read Only).This is set when transmit FIFO is empty.." "0: Not empty,1: Empty"
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rbitfld.long 0xC 19. "TXFULL,Transmit FIFO Full (Read Only).This bit is set when transmit FIFO is full.." "0: Not full,1: Full"
rbitfld.long 0xC 18. "TXTHIF,Transmit FIFO Threshold Flag (Read Only).When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by.." "0: Data word(s) in FIFO is greater than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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bitfld.long 0xC 17. "TXOVIF,Transmit FIFO Overflow Flag (Write '1' To Clear).This flag is set if data is written to transmit FIFO when it is full. ." "0: No overflow,1: Overflow"
bitfld.long 0xC 16. "TXUDIF,Transmit FIFO Underflow Flag (Write '1' To Clear).This flag is set if I2S controller requests data when transmit FIFO is empty. ." "0: No underflow,1: Underflow"
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rbitfld.long 0xC 12. "RXEMPTY,Receive FIFO Empty (Read Only).This is set when receive FIFO is empty.." "0: Not empty,1: Empty"
rbitfld.long 0xC 11. "RXFULL,Receive FIFO Full (Read Only).This bit is set when receive FIFO is full.." "0: Not full,1: Full"
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rbitfld.long 0xC 10. "RXTHIF,Receive FIFO Threshold Flag (Read Only).When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by.." "0: Data word(s) in FIFO is less than threshold level,1: Data word(s) in FIFO is greater than or equal to.."
bitfld.long 0xC 9. "RXOVIF,Receive FIFO Overflow Flag (Write '1' To Clear).This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.." "0: No overflow,1: Overflow"
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bitfld.long 0xC 8. "RXUDIF,Receive FIFO Underflow Flag (Write '1' To Clear).This flag is set if attempt is made to read receive FIFO while it is empty. ." "0: No underflow,1: Underflow"
rbitfld.long 0xC 3. "RIGHT,Right Channel Active (Read Only).This bit indicates current data being transmitted/received belongs to right channel." "0: Left channel,1: Right channel"
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rbitfld.long 0xC 2. "TXIF,I2S Transmit Interrupt (Read Only).This indicates that there is an active transmit interrupt source. This could be TXOVIF  TXUDIF  TXTHIF  LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding.." "0: No transmit interrupt,1: Transmit interrupt occurred"
rbitfld.long 0xC 1. "RXIF,I2S Receive Interrupt (Read Only).This indicates that there is an active receive interrupt source. This could be RXOVIF  RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be.." "0: No receive interrupt,1: Receive interrupt occurred"
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rbitfld.long 0xC 0. "I2SIF,I2S Interrupt (Read Only).This bit is set if any enabled I2S interrupt is active.." "0: No I2S interrupt,1: I2S interrupt active"
wgroup.long 0x10++0x3
line.long 0x0 "I2S_TX,I2S Transmit FIFO Register"
hexmask.long 0x0 0.--31. 1. "TX,Transmit FIFO Register (Write Only).A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT."
rgroup.long 0x14++0x3
line.long 0x0 "I2S_RX,I2S Receive FIFO Register"
hexmask.long 0x0 0.--31. 1. "RX,Receive FIFO Register (Read Only).A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT."
tree.end
tree "INT (Interrupt Multiplexer)"
base ad:0x50000300
rgroup.long 0x0++0x7F
line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity Register"
bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: BOD_INT" "0,1,2,3,4,5,6,7"
line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity Register"
bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: WDT_INT" "0,1,2,3,4,5,6,7"
line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity Register"
bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: INT0_INT" "0,1,2,3,4,5,6,7"
line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity Register"
bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: INT0_INT" "0,1,2,3,4,5,6,7"
line.long 0x10 "IRQ4_SRC,IRQ4 (GPA/B) Interrupt Source Identity Register"
bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: GPB_INT.Bit0: GPA_INT" "0,1,2,3,4,5,6,7"
line.long 0x14 "IRQ5_SRC,IRQ5 (ALC) Interrupt Source Identity Register"
bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: ALC_INT" "0,1,2,3,4,5,6,7"
line.long 0x18 "IRQ6_SRC,IRQ6 (PWM0) Interrupt Source Identity Register"
bitfld.long 0x18 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: PWM0_INT" "0,1,2,3,4,5,6,7"
line.long 0x1C "IRQ7_SRC,IRQ7 (PWM1) Interrupt Source Identity Register"
bitfld.long 0x1C 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: PWM1_INT" "0,1,2,3,4,5,6,7"
line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity Register"
bitfld.long 0x20 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: TMR0_INT" "0,1,2,3,4,5,6,7"
line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity Register"
bitfld.long 0x24 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: TMR1_INT" "0,1,2,3,4,5,6,7"
line.long 0x28 "IRQ10_SRC,IRQ10 (RESERVED) Interrupt Source Identity Register"
line.long 0x2C "IRQ11_SRC,IRQ11 (RESERVED) Interrupt Source Identity Register"
line.long 0x30 "IRQ12_SRC,IRQ12 (UART0) Interrupt Source Identity Register"
bitfld.long 0x30 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: UART0_INT" "0,1,2,3,4,5,6,7"
line.long 0x34 "IRQ13_SRC,IRQ13 (RESERVED) Interrupt Source Identity Register"
line.long 0x38 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity Register"
bitfld.long 0x38 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: SPI0_INT" "0,1,2,3,4,5,6,7"
line.long 0x3C "IRQ15_SRC,IRQ15 (RESERVED) Interrupt Source Identity Register"
line.long 0x40 "IRQ16_SRC,IRQ16 (RESERVED) Interrupt Source Identity Register"
line.long 0x44 "IRQ17_SRC,IRQ17 (RESERVED) Interrupt Source Identity Register"
line.long 0x48 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity Register"
bitfld.long 0x48 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: I2C0_INT" "0,1,2,3,4,5,6,7"
line.long 0x4C "IRQ19_SRC,IRQ19 (RESERVED) Interrupt Source Identity Register"
line.long 0x50 "IRQ20_SRC,IRQ20 (RESERVED) Interrupt Source Identity Register"
line.long 0x54 "IRQ21_SRC,IRQ21 (TALARM) Interrupt Source Identity Register"
bitfld.long 0x54 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: TALARM_INT" "0,1,2,3,4,5,6,7"
line.long 0x58 "IRQ22_SRC,IRQ22 (RESERVED ) Interrupt Source Identity Register"
line.long 0x5C "IRQ23_SRC,IRQ23 (RESERVED) Interrupt Source Identity Register"
line.long 0x60 "IRQ24_SRC,IRQ24 (RESERVED) Interrupt Source Identity Register"
line.long 0x64 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity Register"
bitfld.long 0x64 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: TALARM_INT" "0,1,2,3,4,5,6,7"
line.long 0x68 "IRQ26_SRC,IRQ26 (PDMA) Interrupt Source Identity Register"
bitfld.long 0x68 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: PDMA_INT" "0,1,2,3,4,5,6,7"
line.long 0x6C "IRQ27_SRC,IRQ27 (I2S) Interrupt Source Identity Register"
bitfld.long 0x6C 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: I2S_INT" "0,1,2,3,4,5,6,7"
line.long 0x70 "IRQ28_SRC,IRQ28 (CAPS) Interrupt Source Identity Register"
bitfld.long 0x70 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: CAPS_INT" "0,1,2,3,4,5,6,7"
line.long 0x74 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity Register"
bitfld.long 0x74 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: ADC_INT" "0,1,2,3,4,5,6,7"
line.long 0x78 "IRQ30_SRC,IRQ30 (RESERVED) Interrupt Source Identity Register"
line.long 0x7C "IRQ31_SRC,IRQ31 (RTC) Interrupt Source Identity Register"
bitfld.long 0x7C 0.--2. "INT_SRC,Interrupt Source Identity.Bit2: 0.Bit1: 0.Bit0: RTC_INT" "0,1,2,3,4,5,6,7"
group.long 0x80++0x7
line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register"
bitfld.long 0x0 7. "IRQ_TM,IRQ Test Mode.If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the MCU_IRQ register. This is a protected register to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))" "0,1"
hexmask.long.byte 0x0 0.--4. 1. "NMI_SEL,NMI Source Interrupt Select.The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0].The NMI_SEL bit[4:0] used to select the NMI interrupt source"
line.long 0x4 "MCU_IRQ,MCU IRQ Number Identify Register"
hexmask.long 0x4 0.--31. 1. "MCU_IRQ,MCU IRQ Source Test Mode.In Normal mode (NMI_SEL register bit [7] aaa 0) The device collects interrupts from each peripheral and synchronizes them to interrupt the Cortex-M0..In Test mode (NMI_SEL register bit [7] aaa 1)  the interrupts from.."
tree.end
tree "PDMA (Peripheral Direct Memory Access)"
base ad:0x50008000
group.long 0x0++0xF
line.long 0x0 "PDMA_DSCT0_CTL,PDMA Control Register of Channel 0"
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start A PDMA Operation.Note: When PDMA transfer completed  this bit will be cleared automatically..If a bus error occurs  all PDMA transfer will be stopped. Software must reset PDMA channel  and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select.This parameter determines the data width to be transferred each PDMA transfer operation..Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select .x1xx: If this bit is set  and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes.."
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select.This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Destination Address is incremented,1: RESERVED,?,?"
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bitfld.long 0x0 4.--5. "SASEL,Source Address Select.This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Source address is incremented,1: RESERVED,?,?"
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select.This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable.Setting this bit to 1 enables PDMA's operation. If this bit is cleared  PDMA will ignore all PDMA request and force Bus Master into IDLE state..Note: SWRST will clear this bit." "0,1"
line.long 0x4 "PDMA_DSCT0_ENDSA,PDMA Transfer Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "ENDSA,PDMA Transfer Source Address Register.This register holds the initial Source Address of PDMA transfer. .Note: The source address must be word aligned."
line.long 0x8 "PDMA_DSCT0_ENDDA,PDMA Transfer Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "ENDDA,PDMA Transfer Destination Address Register.This register holds the initial Destination Address of PDMA transfer. .Note: The destination address must be word aligned."
line.long 0xC "PDMA_TXBCCH0,PDMA Transfer Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "BYTECNT,PDMA Transfer Byte Count Register.This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF..Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode  the transfer byte count must be word aligned  that is multiples.."
rgroup.long 0x10++0xF
line.long 0x0 "PDMA_INLBPCH0,PDMA Internal Buffer Pointer Register of Channel 0"
hexmask.long.byte 0x0 0.--3. 1. "BURPTR,PDMA Internal Buffer Pointer Register (Read Only).A PDMA transaction consists of two stages  a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between.."
line.long 0x4 "PDMA_CURSACH0,PDMA Current Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "CURSA,PDMA Current Source Address Register (Read Only).This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs."
line.long 0x8 "PDMA_CURDACH0,PDMA Current Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "CURDA,PDMA Current Destination Address Register (Read Only).This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs."
line.long 0xC "PDMA_CURBCCH0,PDMA Current Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "CURBC,PDMA Current Byte Count Register (Read Only).This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs"
group.long 0x20++0x7
line.long 0x0 "PDMA_INTENCH0,PDMA Interrupt Enable Control Register of Channel 0"
bitfld.long 0x0 2. "WAINTEN,Wraparound Interrupt Enable.If enabled  and channel source or destination address is in wraparound mode  the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of .PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
bitfld.long 0x0 1. "TXOKIEN,PDMA Transfer Done Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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bitfld.long 0x0 0. "TXABTIEN,PDMA Read/Write Target Abort Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted  PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
line.long 0x4 "PDMA_CH0IF,PDMA Interrupt Status Register of Channel 0"
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only).This bit is the Interrupt pin status of PDMA channel." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "WAIF,Wrap Around Transfer Byte Count Interrupt Flag.These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits..0001 aaa Current transfer finished flag (CURBC.."
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bitfld.long 0x4 1. "TXOKIF,Block Transfer Done Interrupt Flag.This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
bitfld.long 0x4 0. "TXABTIF,PDMA Read/Write Target Abort Interrupt Flag.This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received"
rgroup.long 0x34++0x3
line.long 0x0 "PDMA_SPANRCH0,PDMA Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--8. 1. "SPANREG,Span Increment Register.This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned  then this number is added to the address register each transfer. The size of the.."
group.long 0x38++0x3
line.long 0x0 "PDMA_CURSRCH0,PDMA Current Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--15. 1. "CSPANREG,Current Span Increment Register.This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode."
group.long 0x100++0xF
line.long 0x0 "PDMA_DSCT1_CTL,PDMA Control Register of Channel 0"
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start A PDMA Operation.Note: When PDMA transfer completed  this bit will be cleared automatically..If a bus error occurs  all PDMA transfer will be stopped. Software must reset PDMA channel  and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select.This parameter determines the data width to be transferred each PDMA transfer operation..Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select .x1xx: If this bit is set  and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes.."
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select.This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Destination Address is incremented,1: RESERVED,?,?"
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bitfld.long 0x0 4.--5. "SASEL,Source Address Select.This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Source address is incremented,1: RESERVED,?,?"
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select.This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable.Setting this bit to 1 enables PDMA's operation. If this bit is cleared  PDMA will ignore all PDMA request and force Bus Master into IDLE state..Note: SWRST will clear this bit." "0,1"
line.long 0x4 "PDMA_DSCT1_ENDSA,PDMA Transfer Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "ENDSA,PDMA Transfer Source Address Register.This register holds the initial Source Address of PDMA transfer. .Note: The source address must be word aligned."
line.long 0x8 "PDMA_DSCT1_ENDDA,PDMA Transfer Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "ENDDA,PDMA Transfer Destination Address Register.This register holds the initial Destination Address of PDMA transfer. .Note: The destination address must be word aligned."
line.long 0xC "PDMA_TXBCCH1,PDMA Transfer Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "BYTECNT,PDMA Transfer Byte Count Register.This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF..Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode  the transfer byte count must be word aligned  that is multiples.."
rgroup.long 0x110++0xF
line.long 0x0 "PDMA_INLBPCH1,PDMA Internal Buffer Pointer Register of Channel 0"
hexmask.long.byte 0x0 0.--3. 1. "BURPTR,PDMA Internal Buffer Pointer Register (Read Only).A PDMA transaction consists of two stages  a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between.."
line.long 0x4 "PDMA_CURSACH1,PDMA Current Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "CURSA,PDMA Current Source Address Register (Read Only).This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs."
line.long 0x8 "PDMA_CURDACH1,PDMA Current Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "CURDA,PDMA Current Destination Address Register (Read Only).This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs."
line.long 0xC "PDMA_CURBCCH1,PDMA Current Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "CURBC,PDMA Current Byte Count Register (Read Only).This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs"
group.long 0x120++0x7
line.long 0x0 "PDMA_INTENCH1,PDMA Interrupt Enable Control Register of Channel 0"
bitfld.long 0x0 2. "WAINTEN,Wraparound Interrupt Enable.If enabled  and channel source or destination address is in wraparound mode  the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of .PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
bitfld.long 0x0 1. "TXOKIEN,PDMA Transfer Done Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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bitfld.long 0x0 0. "TXABTIEN,PDMA Read/Write Target Abort Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted  PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
line.long 0x4 "PDMA_CH1IF,PDMA Interrupt Status Register of Channel 0"
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only).This bit is the Interrupt pin status of PDMA channel." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "WAIF,Wrap Around Transfer Byte Count Interrupt Flag.These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits..0001 aaa Current transfer finished flag (CURBC.."
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bitfld.long 0x4 1. "TXOKIF,Block Transfer Done Interrupt Flag.This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
bitfld.long 0x4 0. "TXABTIF,PDMA Read/Write Target Abort Interrupt Flag.This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received"
rgroup.long 0x134++0x3
line.long 0x0 "PDMA_SPANRCH1,PDMA Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--8. 1. "SPANREG,Span Increment Register.This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned  then this number is added to the address register each transfer. The size of the.."
group.long 0x138++0x3
line.long 0x0 "PDMA_CURSRCH1,PDMA Current Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--15. 1. "CSPANREG,Current Span Increment Register.This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode."
group.long 0x200++0xF
line.long 0x0 "PDMA_DSCT2_CTL,PDMA Control Register of Channel 0"
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start A PDMA Operation.Note: When PDMA transfer completed  this bit will be cleared automatically..If a bus error occurs  all PDMA transfer will be stopped. Software must reset PDMA channel  and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select.This parameter determines the data width to be transferred each PDMA transfer operation..Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select .x1xx: If this bit is set  and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes.."
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select.This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Destination Address is incremented,1: RESERVED,?,?"
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bitfld.long 0x0 4.--5. "SASEL,Source Address Select.This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Source address is incremented,1: RESERVED,?,?"
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select.This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable.Setting this bit to 1 enables PDMA's operation. If this bit is cleared  PDMA will ignore all PDMA request and force Bus Master into IDLE state..Note: SWRST will clear this bit." "0,1"
line.long 0x4 "PDMA_DSCT2_ENDSA,PDMA Transfer Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "ENDSA,PDMA Transfer Source Address Register.This register holds the initial Source Address of PDMA transfer. .Note: The source address must be word aligned."
line.long 0x8 "PDMA_DSCT2_ENDDA,PDMA Transfer Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "ENDDA,PDMA Transfer Destination Address Register.This register holds the initial Destination Address of PDMA transfer. .Note: The destination address must be word aligned."
line.long 0xC "PDMA_TXBCCH2,PDMA Transfer Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "BYTECNT,PDMA Transfer Byte Count Register.This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF..Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode  the transfer byte count must be word aligned  that is multiples.."
rgroup.long 0x210++0xF
line.long 0x0 "PDMA_INLBPCH2,PDMA Internal Buffer Pointer Register of Channel 0"
hexmask.long.byte 0x0 0.--3. 1. "BURPTR,PDMA Internal Buffer Pointer Register (Read Only).A PDMA transaction consists of two stages  a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between.."
line.long 0x4 "PDMA_CURSACH2,PDMA Current Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "CURSA,PDMA Current Source Address Register (Read Only).This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs."
line.long 0x8 "PDMA_CURDACH2,PDMA Current Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "CURDA,PDMA Current Destination Address Register (Read Only).This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs."
line.long 0xC "PDMA_CURBCCH2,PDMA Current Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "CURBC,PDMA Current Byte Count Register (Read Only).This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs"
group.long 0x220++0x7
line.long 0x0 "PDMA_INTENCH2,PDMA Interrupt Enable Control Register of Channel 0"
bitfld.long 0x0 2. "WAINTEN,Wraparound Interrupt Enable.If enabled  and channel source or destination address is in wraparound mode  the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of .PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
bitfld.long 0x0 1. "TXOKIEN,PDMA Transfer Done Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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bitfld.long 0x0 0. "TXABTIEN,PDMA Read/Write Target Abort Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted  PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
line.long 0x4 "PDMA_CH2IF,PDMA Interrupt Status Register of Channel 0"
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only).This bit is the Interrupt pin status of PDMA channel." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "WAIF,Wrap Around Transfer Byte Count Interrupt Flag.These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits..0001 aaa Current transfer finished flag (CURBC.."
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bitfld.long 0x4 1. "TXOKIF,Block Transfer Done Interrupt Flag.This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
bitfld.long 0x4 0. "TXABTIF,PDMA Read/Write Target Abort Interrupt Flag.This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received"
rgroup.long 0x234++0x3
line.long 0x0 "PDMA_SPANRCH2,PDMA Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--8. 1. "SPANREG,Span Increment Register.This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned  then this number is added to the address register each transfer. The size of the.."
group.long 0x238++0x3
line.long 0x0 "PDMA_CURSRCH2,PDMA Current Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--15. 1. "CSPANREG,Current Span Increment Register.This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode."
group.long 0x300++0xF
line.long 0x0 "PDMA_DSCT3_CTL,PDMA Control Register of Channel 0"
bitfld.long 0x0 23. "TXEN,Trigger Enable - Start A PDMA Operation.Note: When PDMA transfer completed  this bit will be cleared automatically..If a bus error occurs  all PDMA transfer will be stopped. Software must reset PDMA channel  and then trigger again." "0: Write: no effect. Read: Idle/Finished,1: Enable PDMA data read or write transfer"
bitfld.long 0x0 19.--20. "TXWIDTH,Peripheral Transfer Width Select.This parameter determines the data width to be transferred each PDMA transfer operation..Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB)." "0: One word (32 bits) is transferred for every PDMA..,1: One byte (8 bits) is transferred for every PDMA..,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "WAINTSEL,Wrap Interrupt Select .x1xx: If this bit is set  and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes.."
bitfld.long 0x0 6.--7. "DASEL,Destination Address Select.This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Destination Address is incremented,1: RESERVED,?,?"
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bitfld.long 0x0 4.--5. "SASEL,Source Address Select.This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed  incremented or wrapped.." "0: Transfer Source address is incremented,1: RESERVED,?,?"
bitfld.long 0x0 2.--3. "MODESEL,PDMA Mode Select.This parameter selects to transfer direction of the PDMA channel. Possible values are:." "0: Memory to Memory mode (SRAM-to-SRAM),1: IP to Memory mode (APB-to-SRAM),?,?"
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bitfld.long 0x0 1. "SWRST,Software Engine Reset." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
bitfld.long 0x0 0. "CHEN,PDMA Channel Enable.Setting this bit to 1 enables PDMA's operation. If this bit is cleared  PDMA will ignore all PDMA request and force Bus Master into IDLE state..Note: SWRST will clear this bit." "0,1"
line.long 0x4 "PDMA_DSCT3_ENDSA,PDMA Transfer Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "ENDSA,PDMA Transfer Source Address Register.This register holds the initial Source Address of PDMA transfer. .Note: The source address must be word aligned."
line.long 0x8 "PDMA_DSCT3_ENDDA,PDMA Transfer Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "ENDDA,PDMA Transfer Destination Address Register.This register holds the initial Destination Address of PDMA transfer. .Note: The destination address must be word aligned."
line.long 0xC "PDMA_TXBCCH3,PDMA Transfer Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "BYTECNT,PDMA Transfer Byte Count Register.This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF..Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode  the transfer byte count must be word aligned  that is multiples.."
rgroup.long 0x310++0xF
line.long 0x0 "PDMA_INLBPCH3,PDMA Internal Buffer Pointer Register of Channel 0"
hexmask.long.byte 0x0 0.--3. 1. "BURPTR,PDMA Internal Buffer Pointer Register (Read Only).A PDMA transaction consists of two stages  a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between.."
line.long 0x4 "PDMA_CURSACH3,PDMA Current Source Address Register of Channel 0"
hexmask.long 0x4 0.--31. 1. "CURSA,PDMA Current Source Address Register (Read Only).This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs."
line.long 0x8 "PDMA_CURDACH3,PDMA Current Destination Address Register of Channel 0"
hexmask.long 0x8 0.--31. 1. "CURDA,PDMA Current Destination Address Register (Read Only).This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs."
line.long 0xC "PDMA_CURBCCH3,PDMA Current Byte Count Register of Channel 0"
hexmask.long.word 0xC 0.--15. 1. "CURBC,PDMA Current Byte Count Register (Read Only).This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs"
group.long 0x320++0x7
line.long 0x0 "PDMA_INTENCH3,PDMA Interrupt Enable Control Register of Channel 0"
bitfld.long 0x0 2. "WAINTEN,Wraparound Interrupt Enable.If enabled  and channel source or destination address is in wraparound mode  the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of .PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts.." "0: Disable Wraparound PDMA interrupt generation,1: Enable Wraparound interrupt generation"
bitfld.long 0x0 1. "TXOKIEN,PDMA Transfer Done Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.." "0: Disable PDMA transfer done interrupt generation,1: Enable PDMA transfer done interrupt generation"
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bitfld.long 0x0 0. "TXABTIEN,PDMA Read/Write Target Abort Interrupt Enable.If enabled  the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted  PDMA channel must be reset to resume DMA.." "0: Disable PDMA transfer target abort interrupt..,1: Enable PDMA transfer target abort interrupt.."
line.long 0x4 "PDMA_CH3IF,PDMA Interrupt Status Register of Channel 0"
rbitfld.long 0x4 31. "INTSTS,Interrupt Pin Status (Read Only).This bit is the Interrupt pin status of PDMA channel." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "WAIF,Wrap Around Transfer Byte Count Interrupt Flag.These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits..0001 aaa Current transfer finished flag (CURBC.."
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bitfld.long 0x4 1. "TXOKIF,Block Transfer Done Interrupt Flag.This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.." "0: Transfer ongoing or Idle,1: Transfer Complete"
bitfld.long 0x4 0. "TXABTIF,PDMA Read/Write Target Abort Interrupt Flag.This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA.." "0: No bus ERROR response received,1: Bus ERROR response received"
rgroup.long 0x334++0x3
line.long 0x0 "PDMA_SPANRCH3,PDMA Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--8. 1. "SPANREG,Span Increment Register.This is a signed number in range [-128 127] for use in spanned address mode. If destination or source addressing mode is set as spanned  then this number is added to the address register each transfer. The size of the.."
group.long 0x338++0x3
line.long 0x0 "PDMA_CURSRCH3,PDMA Current Span Increment Register of Channel 0"
hexmask.long.word 0x0 0.--15. 1. "CSPANREG,Current Span Increment Register.This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode."
group.long 0xE00++0x7
line.long 0x0 "PDMA_CRCCTL,CRC Control Register"
bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode." "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,?,?"
bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length.When operation in CPU PIO mode (CRCEN aaa 1  TRGEN aaa 0)  this field indicates the write data length..00 aaa Data length is 8-bit mode.01 aaa Data length is 16-bit mode.1x aaa Data length is 32-bit mode.Note1: This field is.." "0,1,2,3"
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bitfld.long 0x0 27. "CHKSFMT,Checksum Complement." "0: No 1's complement for CRC checksum,1: 1's complement for CRC checksum"
bitfld.long 0x0 26. "DATFMT,Write Data Complement." "0: No 1's complement for CRC write data in,1: 1's complement for CRC write data in"
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bitfld.long 0x0 25. "CHKSREV,Checksum Reverse.Note: If the checksum data is 0XDD7B0F2E  the bit order reversed for CRC checksum is 0x74F0DEBB." "0: No bit order reverse for CRC checksum,1: Bit order reverse for CRC checksum"
bitfld.long 0x0 24. "DATREV,Write Data Order Reverse.Note: If the write data is 0xAABBCCDD  the bit order reverse for CRC write data in is 0x55DD33BB" "0: No bit order reversed for CRC write data in,1: Bit order reversed for CRC write data in (per.."
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bitfld.long 0x0 23. "TRGEN,TRGEN.Note1: If this bit assert indicates the CRC engine operation in CRC DMA mode  do not fill in any data in PDMA_CRCDAT register..Note2: When CRC DMA transfer is completed  this bit will be cleared automatically..Note3: If the bus error occurs .." "0: No effect,1: CRC DMA data read or write transfer Enabled"
bitfld.long 0x0 1. "CRCRST,CRC Engine Reset.Note: When operated in CPU PIO mode  setting this bit will reload the initial seed value." "0: No effect,1: Reset the internal CRC state machine and.."
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bitfld.long 0x0 0. "CRCEN,CRC Channel Enable.Setting this bit to 1 enables CRC's operation..When operation in CRC DMA mode (TRGEN aaa 1)  if user clears this bit  the DMA operation will be continuous until all CRC DMA operation is done  and the TRGEN bit will asserted until.." "0,1"
line.long 0x4 "PDMA_CRCSA,CRC DMA Source Address Register"
hexmask.long 0x4 0.--31. 1. "SRCADDR,CRC DMA Transfer Source Address Register.This field indicates a 32-bit source address of CRC DMA..Note: The source address must be word alignment."
group.long 0xE0C++0x3
line.long 0x0 "PDMA_CRCBC,CRC DMA Transfer Byte Count Register"
hexmask.long.word 0x0 0.--15. 1. "BYTECNT,CRC DMA Transfer Byte Count Register.This field indicates a 16-bit transfer byte count number of CRC DMA."
rgroup.long 0xE14++0x3
line.long 0x0 "PDMA_CRCCSA,CRC DMA Current Source Address Register"
hexmask.long 0x0 0.--31. 1. "CURSA,CRC DMA Current Source Address Register (Read Only).This field indicates the source address where the CRC DMA transfer just occurs."
rgroup.long 0xE1C++0x3
line.long 0x0 "PDMA_CRCCBC,CRC DMA Current Transfer Byte Count Register"
hexmask.long.word 0x0 0.--15. 1. "CURBC,CRC DMA Current Byte Count Register (Read Only).This field indicates the current remained byte count of CRC_DMA..Note: CRCRST will clear this register value."
group.long 0xE20++0x7
line.long 0x0 "PDMA_CRCINTEN,CRC DMA Interrupt Enable Register"
bitfld.long 0x0 1. "TXOKIEN,CRC DMA Transfer Done Interrupt Enable." "0: Interrupt generator Disabled when CRC DMA..,1: Interrupt generator Enabled when CRC DMA.."
bitfld.long 0x0 0. "TXABTIEN,CRC DMA Read/Write Target Abort Interrupt Enable." "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled during.."
line.long 0x4 "PDMA_CRCINTF,CRC DMA Interrupt Status Register"
bitfld.long 0x4 1. "TXOKIF,Block Transfer Done Interrupt Flag.This bit indicates that CRC DMA has finished all transfer..Software can write 1 to clear this bit to zero." "0: Not finished,1: Done"
bitfld.long 0x4 0. "TXABTIF,CRC DMA Read/Write Target Abort Interrupt Flag.Software can write 1 to clear this bit to zero." "0: No bus ERROR response received,1: Bus ERROR response received"
group.long 0xE80++0x7
line.long 0x0 "PDMA_CRCDAT,CRC Write Data Register"
hexmask.long 0x0 0.--31. 1. "DATA,CRC Write Data Register.When operated in CPU PIO (PDMA_CRCCTL.CRCEN aaa 1  PDMA_CRCCTL.TRGEN aaa 0) mode  software can write data to this field to perform CRC operation;.When operated in CRC DMA mode (PDMA_CRCCTL.CRCEN aaa 1  PDMA_CRCCTL.TRGEN aaa.."
line.long 0x4 "PDMA_CRCSEED,CRC Seed Register"
hexmask.long 0x4 0.--31. 1. "SEED,CRC Seed Register.This field indicates the CRC seed value."
rgroup.long 0xE88++0x3
line.long 0x0 "PDMA_CRCCHKS,CRC Checksum Register"
hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Register.This field indicates the CRC checksum."
group.long 0xF00++0x7
line.long 0x0 "PDMA_GLOCTL,PDMA Global Control Register"
hexmask.long.byte 0x0 8.--11. 1. "CHCKEN,PDMA Controller Channel Clock Enable Control.To enable clock for channel n CHCKEN[n] must be set..CHCKEN[n] aaa 1: Enable Channel n clock.CHCKEN[n] aaa 0: Disable Channel n clock"
bitfld.long 0x0 0. "SWRST,PDMA Software Reset.Note: This bit can reset all channels (global reset)." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the internal.."
line.long 0x4 "PDMA_SVCSEL,PDMA Service Selection Control Register"
hexmask.long.byte 0x4 28.--31. 1. "I2STXSEL,PDMA I2S Transmit Selection.This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request."
hexmask.long.byte 0x4 24.--27. 1. "I2SRXSEL,PDMA I2S Receive Selection.This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request."
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hexmask.long.byte 0x4 20.--23. 1. "UARTXSEL,PDMA UART0 Transmit Selection.This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request."
hexmask.long.byte 0x4 16.--19. 1. "UARTRXSEL,PDMA UART0 Receive Selection.This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request."
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hexmask.long.byte 0x4 12.--15. 1. "DPWMTXSEL,PDMA DPWM Transmit Selection.This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request."
hexmask.long.byte 0x4 8.--11. 1. "ADCRXSEL,PDMA ADC Receive Selection.This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request."
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hexmask.long.byte 0x4 4.--7. 1. "SPITXSEL,PDMA SPI0 Transmit Selection.This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request."
hexmask.long.byte 0x4 0.--3. 1. "SPIRXSEL,PDMA SPI0 Receive Selection.This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request."
rgroup.long 0xF0C++0x3
line.long 0x0 "PDMA_GLOBALIF,PDMA Global Interrupt Status Register"
hexmask.long.byte 0x0 0.--3. 1. "GLOBALIF,Interrupt Pin Status (Read Only).GLOBALIF[n] is the interrupt status of PDMA channel n."
tree.end
tree "PWM (Pulse Width Modulator)"
base ad:0x40040000
group.long 0x0++0x13
line.long 0x0 "PWM0_CLKPSC,PWM Prescaler Register"
hexmask.long.byte 0x0 24.--31. 1. "DTCNT23,Dead Zone Interval Register For Pair Of PWM0CH2 And PWM0CH3.These 8 bits determine dead zone length..The unit time of dead zone length is that from clock selector 0."
hexmask.long.byte 0x0 16.--23. 1. "DTCNT01,Dead Zone Interval Register For Pair Of PWM0CH0 And PWM0CH1.These 8 bits determine dead zone length..The unit time of dead zone length is that from clock selector 0."
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hexmask.long.byte 0x0 8.--15. 1. "CLKPSC23,Clock Pre-Scaler For Pair Of PWM0CH2 And PWM0CH3.Clock input is divided by (CLKPSC23 + 1) .If CLKPSC23 aaa 0  then the pre-scaler output clock will be stopped..This implies PWM counter 2 and 3 will also be stopped."
hexmask.long.byte 0x0 0.--7. 1. "CLKPSC01,Clock Pre-Scaler Pair Of PWM0CH0 And PWM0CH1.Clock input is divided by (CLKPSC01 + 1) .If CLKPSC01 aaa 0  then the pre-scaler output clock will be stopped..This implies PWM counter 0 and 1 will also be stopped."
line.long 0x4 "PWM0_CLKDIV,PWM Clock Select Register"
bitfld.long 0x4 12.--14. "CLKDIV3,Timer 3 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 8.--10. "CLKDIV2,Timer 2 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "CLKDIV1,Timer 1 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0.--2. "CLKDIV0,Timer 0 Clock Source Selection.Value : Input clock divided by.0 : 2.1 : 4.2 : 8.3 :.." "0: 2,1: 4,2: 8,3: 16,4: 1,?,?,?"
line.long 0x8 "PWM0_CTL,PWM Control Register"
bitfld.long 0x8 27. "CNTMODE3,PWM-Timer 3 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
bitfld.long 0x8 26. "PINV3,PWM-Timer 3 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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bitfld.long 0x8 24. "CNTEN3,PWM-Timer 3 Enable/Disable Start Run." "0: Stop PWM-Timer 3,1: Enable PWM-Timer 3 Start/Run"
bitfld.long 0x8 19. "CNTMODE2,PWM-Timer 2 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD2 and PWM_CMPDAT2 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
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bitfld.long 0x8 18. "PINV2,PWM-Timer 2 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 16. "CNTEN2,PWM-Timer 2 Enable/Disable Start Run." "0: Stop PWM-Timer 2,1: Enable PWM-Timer 2 Start/Run"
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bitfld.long 0x8 11. "CNTMODE1,PWM-Timer 1 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
bitfld.long 0x8 10. "PINV1,PWM-Timer 1 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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bitfld.long 0x8 8. "CNTEN1,PWM-Timer 1 Enable/Disable Start Run." "0: Stop PWM-Timer 1,1: Enable PWM-Timer 1 Start/Run"
bitfld.long 0x8 5. "DTEN23,Dead-Zone 23 Generator Enable/Disable Pair Of PWM0CH2 And PWM0CH3.Note: When Dead-Zone Generator is enabled  the pair of PWM0CH2 and PWM0CH3 become a complementary pair." "0: Disable,1: Enable"
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bitfld.long 0x8 4. "DTEN01,Dead-Zone 01 Generator Enable/Disable Pair Of PWM0CH0 And PWM0CH1.Note: When Dead-Zone Generator is enabled  the pair of PWM0CH0 and PWM0CH1 become a complementary pair." "0: Disable,1: Enable"
bitfld.long 0x8 3. "CNTMODE0,PWM-Timer 0 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared." "0: One-Shot Mode,1: Auto-reload Mode"
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bitfld.long 0x8 2. "PINV0,PWM-Timer 0 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x8 0. "CNTEN0,PWM-Timer 0 Enable/Disable Start Run." "0: Stop PWM-Timer 0 Running,1: Enable PWM-Timer 0 Start/Run"
line.long 0xC "PWM0_PERIOD0,PWM Counter Register 0"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x10 "PWM0_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0x14++0x3
line.long 0x0 "PWM0_CNT0,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0x18++0x7
line.long 0x0 "PWM0_PERIOD1,PWM Counter Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x4 "PWM0_CMPDAT1,PWM Comparator Register 0"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0x20++0x3
line.long 0x0 "PWM0_CNT1,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0x24++0x7
line.long 0x0 "PWM0_PERIOD2,PWM Counter Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x4 "PWM0_CMPDAT2,PWM Comparator Register 0"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0x2C++0x3
line.long 0x0 "PWM0_CNT2,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0x30++0x7
line.long 0x0 "PWM0_PERIOD3,PWM Counter Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x4 "PWM0_CMPDAT3,PWM Comparator Register 0"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0x38++0x3
line.long 0x0 "PWM0_CNT3,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0x40++0x7
line.long 0x0 "PWM0_INTEN,PWM Interrupt Enable Register"
bitfld.long 0x0 3. "PIEN3,PWM Timer 3 Interrupt Enable." "0: Disable,1: Enable"
bitfld.long 0x0 2. "PIEN2,PWM Timer 2 Interrupt Enable." "0: Disable,1: Enable"
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bitfld.long 0x0 1. "PIEN1,PWM Timer 1 Interrupt Enable." "0: Disable,1: Enable"
bitfld.long 0x0 0. "PIEN0,PWM Timer 0 Interrupt Enable." "0: Disable,1: Enable"
line.long 0x4 "PWM0_INTSTS,PWM Interrupt Flag Register"
bitfld.long 0x4 3. "PIF3,PWM Timer 3 Interrupt Flag.Flag is set by hardware when PWM0CH3 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
bitfld.long 0x4 2. "PIF2,PWM Timer 2 Interrupt Flag.Flag is set by hardware when PWM0CH2 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
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bitfld.long 0x4 1. "PIF1,PWM Timer 1 Interrupt Flag.Flag is set by hardware when PWM0CH1 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
bitfld.long 0x4 0. "PIF0,PWM Timer 0 Interrupt Flag.Flag is set by hardware when PWM0CH0 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
group.long 0x50++0x7
line.long 0x0 "PWM0_CAPCTL01,Capture Control Register For Pair Of PWM0CH0 And PWM0CH1"
bitfld.long 0x0 23. "CFLIF1,PWM_FCAPDAT1 Latched Indicator Bit.When input channel 1 has a falling transition  PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x0 22. "CRLIF1,PWM_RCAPDAT1 Latched Indicator Bit.When input channel 1 has a rising transition  PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x0 20. "CAPIF1,Capture1 Interrupt Indication Flag.If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1)  a rising transition at input channel 1 will result in CAPIF1 to high; Similarly  a falling transition will cause CAPIF1 to be set high if channel 1.." "0,1"
bitfld.long 0x0 19. "CAPEN1,Capture Channel 1 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 1,1: Enable capture function on channel 1"
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bitfld.long 0x0 18. "CFLIEN1,Channel 1 Falling Latch Interrupt Enable .When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling edge latch interrupt,1: Enable falling edge latch interrupt"
bitfld.long 0x0 17. "CRLIEN1,Channel 1 Rising Latch Interrupt Enable .When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising edge latch interrupt,1: Enable rising edge latch interrupt"
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bitfld.long 0x0 16. "CAPINV1,Channel 1 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
bitfld.long 0x0 7. "CFLIF0,PWM_FCAPDAT0 Latched Indicator Bit.When input channel 0 has a falling transition  PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x0 6. "CRLIF0,PWM_RCAPDAT0 Latched Indicator Bit.When input channel 0 has a rising transition  PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x0 4. "CAPIF0,Capture0 Interrupt Indication Flag.If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1)  a rising transition at input channel 0 will result in CAPIF0 to high; Similarly  a falling transition will cause CAPIF0 to be set high if channel 0.." "0,1"
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bitfld.long 0x0 3. "CAPEN0,Capture Channel 0 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 0,1: Enable capture function on channel 0"
bitfld.long 0x0 2. "CFLIEN0,Channel 0 Falling Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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bitfld.long 0x0 1. "CRLIEN0,Channel 0 Rising Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
bitfld.long 0x0 0. "CAPINV0,Channel 0 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
line.long 0x4 "PWM0_CAPCTL23,Capture Control Register For Pair Of PWM0CH2 And PWM0CH3"
bitfld.long 0x4 23. "CFLIF3,PWM_FCAPDAT3 Latched Indicator Bit.When input channel 1 has a falling transition  PWM_FCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x4 22. "CRLIF3,PWM_RCAPDAT3 Latched Indicator Bit.When input channel 1 has a rising transition  PWM_RCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x4 20. "CAPIF3,Capture3 Interrupt Indication Flag.If channel 1 rising latch interrupt is enabled (CRLIEN3 aaa 1)  a rising transition at input channel 1 will result in CAPIF3 to high; Similarly  a falling transition will cause CAPIF3 to be set high if channel 1.." "0,1"
bitfld.long 0x4 19. "CAPEN3,Capture Channel 3 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 1,1: Enable capture function on channel 1"
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bitfld.long 0x4 18. "CFLIEN3,Channel 3 Falling Latch Interrupt Enable .When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling edge latch interrupt,1: Enable falling edge latch interrupt"
bitfld.long 0x4 17. "CRLIEN3,Channel 3 Rising Latch Interrupt Enable .When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising edge latch interrupt,1: Enable rising edge latch interrupt"
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bitfld.long 0x4 16. "CAPINV3,Channel 3 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
bitfld.long 0x4 7. "CFLIF2,PWM_FCAPDAT2 Latched Indicator Bit.When input channel 0 has a falling transition  PWM_FCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x4 6. "CRLIF2,PWM_RCAPDAT2 Latched Indicator Bit.When input channel 0 has a rising transition  PWM_RCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x4 4. "CAPIF2,Capture2 Interrupt Indication Flag.If channel 0 rising latch interrupt is enabled (CRLIEN2 aaa 1)  a rising transition at input channel 0 will result in CAPIF2 to high; Similarly  a falling transition will cause CAPIF2 to be set high if channel 0.." "0,1"
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bitfld.long 0x4 3. "CAPEN2,Capture Channel 2 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 0,1: Enable capture function on channel 0"
bitfld.long 0x4 2. "CFLIEN2,Channel 2 Falling Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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bitfld.long 0x4 1. "CRLIEN2,Channel 2 Rising Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
bitfld.long 0x4 0. "CAPINV2,Channel 2 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
rgroup.long 0x58++0x1F
line.long 0x0 "PWM0_RCAPDAT0,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x0 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0x4 "PWM0_FCAPDAT0,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x4 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
line.long 0x8 "PWM0_RCAPDAT1,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x8 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0xC "PWM0_FCAPDAT1,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0xC 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
line.long 0x10 "PWM0_RCAPDAT2,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x10 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0x14 "PWM0_FCAPDAT2,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x14 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
line.long 0x18 "PWM0_RCAPDAT3,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x18 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0x1C "PWM0_FCAPDAT3,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x1C 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
group.long 0x78++0x1B
line.long 0x0 "PWM0_CAPINEN,Capture Input Enable Register"
hexmask.long.byte 0x0 0.--3. 1. "CAPINEN,Capture Input Enable Register.0 : OFF (GPA[13:12]  GPB[15:14] pin input disconnected from Capture block).1 : ON (GPA[13:12]   GPB[15:14] pin  if in PWM alternative function  will be configured as an input and fed to capture.."
line.long 0x4 "PWM0_POEN,PWM0 Output Enable Register for CH0~CH3"
bitfld.long 0x4 3. "POEN3,PWM0CH3 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM0CH3 output to pin,1: Enable PWM0CH3 output to pin"
bitfld.long 0x4 2. "POEN2,PWM0CH2 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM0CH2 output to pin,1: Enable PWM0CH2 output to pin"
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bitfld.long 0x4 1. "POEN1,PWM0CH1 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM0CH1 output to pin,1: Enable PWM0CH1 output to pin"
bitfld.long 0x4 0. "POEN0,PWM0CH0 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM0CH0 output to pin,1: Enable PWM0CH 0 output to pin"
line.long 0x8 "PWM1_CLKPSC,PWM Prescaler Register"
hexmask.long.byte 0x8 16.--23. 1. "DTCNT01,Dead Zone Interval Register For Pair Of PWM1CH0 And PWM1CH1.These 8 bits determine dead zone length..The unit time of dead zone length is that from clock selector 0."
hexmask.long.byte 0x8 0.--7. 1. "CLKPSC01,Clock Pre-Scaler For Pair Of PWM1CH0 And PWM1CH1.Clock input is divided by (CLKPSC01 + 1) .If CLKPSC01 aaa 0  then the pre-scaler output clock will be stopped..This implies PWM counter 4 and 5 will also be stopped."
line.long 0xC "PWM1_CLKDIV,PWM Clock Select Register"
bitfld.long 0xC 4.--6. "CLKDIV1,Timer 1 Clock Source Selection. (Table is as CLKDIV0)" "0,1,2,3,4,5,6,7"
bitfld.long 0xC 0.--2. "CLKDIV0,Timer 0 Clock Source Selection.Value : Input clock divided by.0 : 2.1 : 4.2 : 8.3 :.." "0: 2,1: 4,2: 8,3: 16,4: 1,?,?,?"
line.long 0x10 "PWM1_CTL,PWM Control Register"
bitfld.long 0x10 11. "CNTMODE1,PWM-Timer 1 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared." "0: One-Shot Mode,1: Auto-load Mode"
bitfld.long 0x10 10. "PINV1,PWM-Timer 1 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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bitfld.long 0x10 8. "CNTEN1,PWM-Timer 1 Enable/Disable Start Run." "0: Stop PWM-Timer 1,1: Enable PWM-Timer 1 Start/Run"
bitfld.long 0x10 4. "DTEN01,Dead-Zone 01 Generator Enable/Disable For Pair Of PWM1CH0 And PWM1CH1.Note: When Dead-Zone Generator is enabled  the pair of PWM1CH0 and PWM1CH1 become a complementary pair." "0: Disable,1: Enable"
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bitfld.long 0x10 3. "CNTMODE0,PWM-Timer 0 Auto-Reload/One-Shot Mode.Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared." "0: One-Shot Mode,1: Auto-reload Mode"
bitfld.long 0x10 2. "PINV0,PWM-Timer 0 Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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bitfld.long 0x10 0. "CNTEN0,PWM-Timer 0 Enable/Disable Start Run." "0: Stop PWM-Timer 0 Running,1: Enable PWM-Timer 0 Start/Run"
line.long 0x14 "PWM1_PERIOD0,PWM Counter Register 0"
hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x18 "PWM1_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x18 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0x94++0x3
line.long 0x0 "PWM1_CNT0,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0x98++0x7
line.long 0x0 "PWM1_PERIOD1,PWM Counter Register 0"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value.PERIOD determines the PWM period..PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty ratio aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width.."
line.long 0x4 "PWM1_CMPDAT1,PWM Comparator Register 0"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register.CMP determines the PWM duty cycle..PWM frequency aaa PWM1CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1); .Duty Cycle aaa (CMP+1)/(PERIOD+1)..CMP > aaa PERIOD: PWM output is always high..CMP < PERIOD: PWM low width aaa.."
rgroup.long 0xA0++0x3
line.long 0x0 "PWM1_CNT1,PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register.Reports the current value of the 16-bit down counter."
group.long 0xC0++0x7
line.long 0x0 "PWM1_INTEN,PWM Interrupt Enable Register"
bitfld.long 0x0 1. "PIEN1,PWM Timer 1 Interrupt Enable." "0: Disable,1: Enable"
bitfld.long 0x0 0. "PIEN0,PWM Timer 0 Interrupt Enable." "0: Disable,1: Enable"
line.long 0x4 "PWM1_INTSTS,PWM Interrupt Flag Register"
bitfld.long 0x4 1. "PIF1,PWM Timer 1 Interrupt Flag.Flag is set by hardware when PWM1CH1 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
bitfld.long 0x4 0. "PIF0,PWM Timer 0 Interrupt Flag.Flag is set by hardware when PWM1CH0 down counter reaches zero  software can clear this bit by writing '1' to it." "0,1"
group.long 0xD0++0x3
line.long 0x0 "PWM1_CAPCTL01,Capture Control Register For Pair Of PWM1CH0 And PWM1CH1"
bitfld.long 0x0 23. "CFLIF1,PWM_FCAPDAT1 Latched Indicator Bit.When input channel 1 has a falling transition  PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x0 22. "CRLIF1,PWM_RCAPDAT1 Latched Indicator Bit.When input channel 1 has a rising transition  PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x0 20. "CAPIF1,Capture1 Interrupt Indication Flag.If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1)  a rising transition at input channel 1 will result in CAPIF1 to high; Similarly  a falling transition will cause CAPIF1 to be set high if channel 1.." "0,1"
bitfld.long 0x0 19. "CAPEN1,Capture Channel 1 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 1,1: Enable capture function on channel 1"
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bitfld.long 0x0 18. "CFLIEN1,Channel 1 Falling Latch Interrupt Enable .When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling edge latch interrupt,1: Enable falling edge latch interrupt"
bitfld.long 0x0 17. "CRLIEN1,Channel 1 Rising Latch Interrupt Enable .When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising edge latch interrupt,1: Enable rising edge latch interrupt"
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bitfld.long 0x0 16. "CAPINV1,Channel 1 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
bitfld.long 0x0 7. "CFLIF0,PWM_FCAPDAT0 Latched Indicator Bit.When input channel 0 has a falling transition  PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
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bitfld.long 0x0 6. "CRLIF0,PWM_RCAPDAT0 Latched Indicator Bit.When input channel 0 has a rising transition  PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware  software can clear this bit by writing a zero to it." "0,1"
bitfld.long 0x0 4. "CAPIF0,Capture0 Interrupt Indication Flag.If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1)  a rising transition at input channel 0 will result in CAPIF0 to high; Similarly  a falling transition will cause CAPIF0 to be set high if channel 0.." "0,1"
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bitfld.long 0x0 3. "CAPEN0,Capture Channel 0 Transition Enable/Disable.When enabled  Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition..When disabled  Capture function is inactive as is interrupt." "0: Disable capture function on channel 0,1: Enable capture function on channel 0"
bitfld.long 0x0 2. "CFLIEN0,Channel 0 Falling Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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bitfld.long 0x0 1. "CRLIEN0,Channel 0 Rising Latch Interrupt Enable ON/OFF.When enabled  capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
bitfld.long 0x0 0. "CAPINV0,Channel 0 Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
rgroup.long 0xD8++0xF
line.long 0x0 "PWM1_RCAPDAT0,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x0 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0x4 "PWM1_FCAPDAT0,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x4 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
line.long 0x8 "PWM1_RCAPDAT1,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x8 0.--15. 1. "RCAPDAT,Capture Rising Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a rising edge of the input signal."
line.long 0xC "PWM1_FCAPDAT1,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0xC 0.--15. 1. "FCAPDAT,Capture Falling Latch Register.In Capture mode  this register is latched with the value of the PWM counter on a falling edge of the input signal."
group.long 0xF8++0x7
line.long 0x0 "PWM1_CAPINEN,Capture Input Enable Register"
bitfld.long 0x0 0.--1. "CAPINEN,Capture Input Enable Register.0 : OFF (GPA[15:14] pin input disconnected from Capture block).1 : ON (GPA[15:14] pin  if in PWM alternative function  will be configured as an input and fed to capture function).CAPINEN[1:0].Bit [1][0].Bit x1 :.." "0: OFF,1: ON,?,?"
line.long 0x4 "PWM1_POEN,PWM1 Output Enable Register for CH0~CH1"
bitfld.long 0x4 1. "POEN1,PWM1CH1 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM1CH1 output to pin,1: Enable PWM1CH1 output to pin"
bitfld.long 0x4 0. "POEN0,PWM1CH0 Output Enable Register.Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)" "0: Disable PWM1CH0 output to pin,1: Enable PWM1CH0 output to pin"
tree.end
tree "RTC (Real-Time Clock)"
base ad:0x40008000
group.long 0x0++0x23
line.long 0x0 "RTC_INIT,RTC Initialization Register"
hexmask.long 0x0 1.--31. 1. "INIT,RTC Initialization.After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357 to INIT. This will force a hardware reset then release all logic and counters."
rbitfld.long 0x0 0. "ATVSTS,RTC Active Status (Read Only).0: RTC is in reset state.1: RTC is in normal active state." "0: RTC is in reset state,1: RTC is in normal active state"
line.long 0x4 "RTC_RWEN,RTC Access Enable Register"
rbitfld.long 0x4 16. "RWENF,RTC Register Access Enable Flag (Read Only).This bit will be set after RWEN[15:0] register is set to 0xA965  it will clear automatically in 512 RTC clock cycles or RWEN[15:0] ! aaa 0xA965. The effect of RTC_RWEN.RWENF on access to each register is.." "0: RTC register read/write disable,1: RWENF aaa 0"
hexmask.long.word 0x4 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only). 0xA965 aaa Enable RTC access . Others aaa Disable RTC access"
line.long 0x8 "RTC_FREQADJ,RTC Frequency Compensation Register"
hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part.Register should contain the value (INT(Factual) - 32761).Ex: Integer part of detected value aaa 32772 . RTC_FREQADJ.INTEGER aaa 32772-32761 aaa 11 (1011b).The range between 32761 and 32776"
hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fractional Part.Formula aaa (fraction part of detected value) x 60.Refer to 5.8.4.4 for the examples."
line.long 0xC "RTC_TIME,Time Load Register"
bitfld.long 0xC 20.--21. "TENHR,10 Hour Time Digit (0~3)" "0,1,2,3"
hexmask.long.byte 0xC 16.--19. 1. "HR,1 Hour Time Digit (0~9)"
bitfld.long 0xC 12.--14. "TENMIN,10 Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--11. 1. "MIN,1 Min Time Digit (0~9)"
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bitfld.long 0xC 4.--6. "TENSEC,10 Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--3. 1. "SEC,1 Sec Time Digit (0~9)"
line.long 0x10 "RTC_CAL,Calendar Load Register"
hexmask.long.byte 0x10 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)"
hexmask.long.byte 0x10 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)"
bitfld.long 0x10 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
hexmask.long.byte 0x10 8.--11. 1. "MON,1-Month Calendar Digit (0~9)"
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bitfld.long 0x10 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
hexmask.long.byte 0x10 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)"
line.long 0x14 "RTC_CLKFMT,Time Scale Selection Register"
bitfld.long 0x14 0. "_24HEN,24-Hour / 12-Hour Mode Selection.Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode..The range of 24-hour time scale is between 0 and 23..12-hour time scale:.01(AM01)  02(AM02)  03(AM03)  04(AM04)  05(AM05) .." "0: select 12-hour time scale with AM and PM..,1: select 24-hour time scale"
line.long 0x18 "RTC_WEEKDAY,Day of the Week Register"
bitfld.long 0x18 0.--2. "WEEKDAY,Day Of The Week Register .0 (Sunday)  1 (Monday)  2 (Tuesday)  3 (Wednesday).4 (Thursday)  5 (Friday)  6 (Saturday)" "0,1,2,3,4,5,6,7"
line.long 0x1C "RTC_TALM,Time Alarm Register"
bitfld.long 0x1C 20.--21. "TENHR,10 Hour Time Digit of Alarm Setting (0~3)2" "0,1,2,3"
hexmask.long.byte 0x1C 16.--19. 1. "HR,1 Hour Time Digit of Alarm Setting (0~9)"
bitfld.long 0x1C 12.--14. "TENMIN,10 Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 8.--11. 1. "MIN,1 Min Time Digit of Alarm Setting (0~9)"
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bitfld.long 0x1C 4.--6. "TENSEC,10 Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x1C 0.--3. 1. "SEC,1 Sec Time Digit of Alarm Setting (0~9)"
line.long 0x20 "RTC_CALM,Calendar Alarm Register"
hexmask.long.byte 0x20 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
hexmask.long.byte 0x20 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
bitfld.long 0x20 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
hexmask.long.byte 0x20 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)"
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bitfld.long 0x20 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
hexmask.long.byte 0x20 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
rgroup.long 0x24++0x3
line.long 0x0 "RTC_LEAPYEAR,Leap year Indicator Register"
bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication Register (Read Only)." "0: Current year is not a leap year,1: Current year is leap year"
group.long 0x28++0xB
line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register"
bitfld.long 0x0 1. "TICKIEN,Time-Tick Interrupt And Wakeup-By-Tick Enable." "0: RTC Time-Tick Interrupt is disabled,1: RTC Time-Tick Interrupt is enabled"
bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable." "0: RTC Alarm Interrupt is disabled,1: RTC Alarm Interrupt is enabled"
line.long 0x4 "RTC_INTSTS,RTC Interrupt Indicator Register"
bitfld.long 0x4 1. "TICKIF,RTC Time-Tick Interrupt Flag." "0: Indicates no Time-Tick Interrupt condition,1: Indicates RTC Time-Tick Interrupt generated"
bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag." "0: Indicates no Alarm Interrupt condition,1: Indicates RTC Alarm Interrupt generated"
line.long 0x8 "RTC_TICK,RTC Time Tick Register"
bitfld.long 0x8 3. "TWKEN,RTC Timer Wakeup CPU Function Enable Bit.If TWKE is set before CPU is in power-down mode  when a RTC Time-Tick or Alarm Match occurs  CPU will wake up.." "0: Disable Wakeup CPU function,1: Enable the Wakeup function"
bitfld.long 0x8 0.--2. "TICKSEL,Time Tick Period Select.The RTC time tick period for Periodic Time-Tick Interrupt request..Time Tick (second) : 1 / (2^TTR).Note: This register can be read back after the RTC is active." "0,1,2,3,4,5,6,7"
tree.end
tree "SCS (External Interrupt Controller Control Registers)"
base ad:0xE000E000
group.long 0x100++0x3
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "SETENA,Set-Enable Control.Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). .Writing 1 will enable the associated interrupt..Writing 0 has no effect..The register.."
group.long 0x180++0x3
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "CLRENA,Clear-Enable Control.Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). .Writing 1 will disable the associated interrupt..Writing 0 has no effect..The.."
group.long 0x200++0x3
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "SETPEND,Set-Pending Control.Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Writing 0 has no effect..The register reads.."
group.long 0x280++0x3
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear-Pending Control.Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)..Writing 0 has no effect..The register.."
group.long 0x400++0x1F
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
bitfld.long 0x0 30.--31. "PRI_3,Priority Of IRQ3.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_2,Priority Of IRQ2.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x0 14.--15. "PRI_1,Priority Of IRQ1.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x0 6.--7. "PRI_0,Priority Of IRQ0.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
bitfld.long 0x4 30.--31. "PRI_7,Priority Of IRQ7.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_6,Priority Of IRQ6.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x4 14.--15. "PRI_5,Priority Of IRQ5.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x4 6.--7. "PRI_4,Priority Of IRQ4.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
bitfld.long 0x8 30.--31. "PRI_11,Priority Of IRQ11.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x8 22.--23. "PRI_10,Priority Of IRQ10.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x8 14.--15. "PRI_9,Priority Of IRQ9.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x8 6.--7. "PRI_8,Priority Of IRQ8.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
bitfld.long 0xC 30.--31. "PRI_15,Priority Of IRQ15.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0xC 22.--23. "PRI_14,Priority Of IRQ14.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0xC 14.--15. "PRI_13,Priority Of IRQ13.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0xC 6.--7. "PRI_12,Priority Of IRQ12.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
bitfld.long 0x10 30.--31. "PRI_19,Priority Of IRQ19.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x10 22.--23. "PRI_18,Priority Of IRQ18.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x10 14.--15. "PRI_17,Priority Of IRQ17.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x10 6.--7. "PRI_16,Priority Of IRQ16.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
bitfld.long 0x14 30.--31. "PRI_23,Priority Of IRQ23.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x14 22.--23. "PRI_22,Priority Of IRQ22.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x14 14.--15. "PRI_21,Priority Of IRQ21.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x14 6.--7. "PRI_20,Priority Of IRQ20.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
bitfld.long 0x18 30.--31. "PRI_27,Priority Of IRQ27.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x18 22.--23. "PRI_26,Priority Of IRQ26.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x18 14.--15. "PRI_25,Priority Of IRQ25.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x18 6.--7. "PRI_24,Priority Of IRQ24.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
bitfld.long 0x1C 30.--31. "PRI_31,Priority Of IRQ31.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x1C 22.--23. "PRI_30,Priority Of IRQ30.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x1C 14.--15. "PRI_29,Priority Of IRQ29.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x1C 6.--7. "PRI_28,Priority Of IRQ28.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x40030000
group.long 0x0++0x1B
line.long 0x0 "SPI_CTL,Control and Status Register"
bitfld.long 0x0 24. "RXMODEEN,FIFO Receive Mode Enable." "0: Disable function,1: Enable FIFO receive mode. In this mode SPI.."
bitfld.long 0x0 23. "RXTCNTEN,DMA Receive Transaction Count Enable." "0: Disable function,1: Enable transaction counter for DMA receive only.."
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bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable." "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable." "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x0 20. "QDIODIR,Quad Or Dual I/O Mode Direction Control." "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable.Note:.Byte reorder function is only available if DWIDTH is defined as 16  24  and 32 bits..REORDER is only available for Receive mode in DUAL and QUAD transactions..For DUAL and QUAD transactions with REORDER  SUSPITV.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Master Slave Mode Control." "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable." "0: Disable SPI Unit Transfer Interrupt,1: Enable SPI Unit Transfer Interrupt to CPU"
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bitfld.long 0x0 16. "TWOBIT,Two Bits Transfer Mode .When 2-bit mode is enabled  the first serial transmitted bit data is from the first FIFO buffer data  and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function  the.." "0: Disable two-bit transfer mode,1: Enable two-bit transfer mode"
bitfld.long 0x0 13. "LSB,LSB First.Note:.For DUAL and QUAD transactions with LSB must be set to 0." "0: The MSB is transmitted/received first (which bit..,1: The LSB is sent first on the line (bit 0 of TX.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,DWIDTH - Data Word Bit Length.This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted..DWIDTH aaa 0x01 ... 1 bit.DWIDTH aaa 0x02 ... 2 bits........DWIDTH aaa 0x1f ... 31 bits.DWIDTH aaa 0x00 ..."
hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only).The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity." "0: SCLK idle low,1: SCLK idle high"
bitfld.long 0x0 2. "TXNEG,Transmit At Negative Edge." "0: The transmitted data output signal is changed at..,1: The transmitted data output signal is changed at.."
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bitfld.long 0x0 1. "RXNEG,Receive At Negative Edge." "0: The received data input signal is latched at the..,1: The received data input signal is latched at the.."
bitfld.long 0x0 0. "SPIEN,SPI Transfer Enable.In Master mode  the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode  the device is ready to receive data when this bit is set to 1. .Note:.All configuration should be set before.." "0: Disable SPI Transfer,1: Enable SPI Transfer"
line.long 0x4 "SPI_CLKDIV,Clock Divider Register (Master Only)"
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register .The value in this field is the frequency divider for generating the SPI engine clock Fspi_sclk  and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. .Fspi_sclk aaa.."
line.long 0x8 "SPI_SSCTL,Slave Select Register"
hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-Out Period .In Slave mode  these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock. If the value is 0  it indicates the.."
bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable ." "0: Slave select inactive interrupt Disable,1: Slave select inactive interrupt Enable"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable ." "0: Slave select active interrupt Disable,1: Slave select active interrupt Enable"
bitfld.long 0x8 9. "SLVUDRIEN,Slave Mode Error 1 Interrupt Enable ." "0: Slave mode error 1 interrupt Disable,1: Slave mode error 1 interrupt Enable"
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bitfld.long 0x8 8. "SLVBCEIEN,Slave Mode Error 0 Interrupt Enable ." "0: Slave mode error 0 interrupt Disable,1: Slave mode error 0 interrupt Enable"
bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-Out FIFO Clear." "0: Function disabled,1: Both the FIFO clear function TXRST and RXRST are.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-Out Interrupt Enable." "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
bitfld.long 0x8 4. "SLV3WIRE,Slave 3-Wire Mode Enable.This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI_CLK  SPI_MISO  and SPI_MOSI.." "0: 4-wire bi-directional interface,1: 3-wire bi-directional interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)." "0: If this bit is cleared slave select signals will..,1: If this bit is set SPI_SS0/1 signals will be.."
bitfld.long 0x8 2. "SSACTPOL,Slave Select Active Level.This bit defines the active status of slave select signal (SPI_SS0/1).." "0: The slave select signal SPI_SS0/1 is active on..,1: The slave select signal SPI_SS0/1 is active on.."
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bitfld.long 0x8 0.--1. "SS,Slave Select Control Bits (Master Only).If AUTOSS bit is cleared  writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state..If the AUTOSS bit is set  writing 0 to any bit.." "0,1,2,3"
line.long 0xC "SPI_PDMACTL,SPI PDMA Control Register"
bitfld.long 0xC 2. "PDMARST,PDMA Reset." "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable.Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware.." "0,1"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit DMA Enable.Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done." "0,1"
line.long 0x10 "SPI_FIFOCTL,FIFO Control/Status Register"
bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold.If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting  the TXTHIF bit will be set to 1  else the TXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold.If the valid data count of the receive FIFO buffer is larger than the RXTH setting  the RXTHIF bit will be set to 1  else the RXTHIF bit will be cleared to 0." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 7. "TXUDFIEN,Slave Transmit Under Run Interrupt Enable." "0: Slave Transmit FIFO under-run interrupt Disabled,1: Slave Transmit FIFO under-run interrupt Enabled"
bitfld.long 0x10 6. "TXUDFPOL,Transmit Under-Run Data Out.Note: The under run event is active after the serial clock input and the hardware synchronous  so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last.." "0: The SPI data out is 0 if there is transmit..,1: The SPI data out is 1 if there is transmit.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable." "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-Out Interrupt Enable." "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable." "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Clear Transmit FIFO Buffer.Note: If there is slave receive time out event  the TXRST will be set 1 when the SPI_SSCTL.SLVTORST  is enabled." "0: No effect,1: Clear transmit FIFO buffer. The TXFULL bit will.."
bitfld.long 0x10 0. "RXRST,Clear Receive FIFO Buffer.Note: If there is slave receive time out event  the RXRST will be set 1 when the SPI_SSCTL.SLVTORST  is enabled." "0: No effect,1: Clear receive FIFO buffer. The RXFULL bit will.."
line.long 0x14 "SPI_STATUS,Status Register"
hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only).This bit field indicates the valid data count of transmit FIFO buffer."
hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only).This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,FIFO CLR Status (Read Only).Note: Both the TXRST  RXRST  need 3 system clock + 3 engine clocks  the status of this bit allows the user to monitor whether the clear function is busy or done." "0: Done the FIFO buffer clear function of TXRST and..,1: Doing the FIFO buffer clear function of TXRST or.."
rbitfld.long 0x14 19. "TXUFIF,Slave Transmit FIFO Under-Run Interrupt Status (Read Only).When the transmit FIFO buffer is empty and further serial clock pulses occur  data transmitted will be the value of the last transmitted bit and this under-run bit will be set..Note: This.." "0,1"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Status (Read Only).Note: If TXTHIEN aaa 1 and TXTHIF aaa 1  the SPI controller will generate a SPI interrupt request." "0: The valid data count of the transmit FIFO buffer..,1: The valid data count of the transmit FIFO buffer.."
rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)." "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)." "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Bit Status (Read Only).Note: The clock source of SPI controller logic is engine clock  it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic  this bit indicates the real.." "0: Indicate the transmit control bit is disabled,1: Indicate the transfer control bit is active"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-Out Interrupt Status.Note: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Status.When the receive FIFO buffer is full  the follow-up data will be dropped and this bit will be set to 1..Note: This bit will be cleared by writing 1 to itself." "0,1"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Status (Read Only).Note: If RXTHIEN aaa 1 and RXTHIF aaa 1  the SPI controller will generate a SPI interrupt request." "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)." "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)." "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
rbitfld.long 0x14 7. "SLVURIF,Slave Mode Error 1 Interrupt Status (Read Only).In Slave mode  transmit under-run occurs when the slave select line goes to inactive state.." "0: No Slave mode error 1 event,1: Slave mode error 1 occurs"
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rbitfld.long 0x14 6. "SLVBEIF,Slave Mode Error 0 Interrupt Status (Read Only).In Slave mode  there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state..Note: If the slave select active but there is no any serial clock input  the SLVBEIF also.." "0: No Slave mode error 0 event,1: Slave mode error 0 occurs"
rbitfld.long 0x14 5. "SLVTOIF,Slave Time-Out Interrupt Status (Read Only).When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input  the slave time-out counter in SPI controller logic will be start. When the value of time-out counter.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only).Note: If SPI_SSCTL.SSACTPOL is set 0  and the SSLINE is 1  the SPI slave select is in inactive status." "0: Indicates the slave select line bus status is 0,1: Indicates the slave select line bus status is 1"
bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Status.Note: This bit will be cleared by writing 1 to itself." "0: Slave select inactive interrupt is clear or not..,1: Slave select inactive interrupt event has occur"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Status.Note: This bit will be cleared by writing 1 to itself." "0: Slave select active interrupt is clear or not..,1: Slave select active interrupt event has occur"
bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Status.Note: This bit will be cleared by writing 1 to itself." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,SPI Unit Bus Status (Read Only).The following listing are the bus busy conditions:.SPIEN aaa 1 and the TXEMPTY aaa 0..For SPI Master  the TXEMPTY aaa 1 but the current transaction is not finished yet..For SPI Slave receive mode  the SPIEN aaa 1 and.." "0: No transaction in the SPI bus,1: SPI controller unit is in busy state"
line.long 0x18 "SPI_RXTSNCNT,Receive Transaction Count Register"
hexmask.long.tbyte 0x18 0.--16. 1. "RXTSNCNT,DMA Receive Transaction Count.When using DMA to receive SPI data without transmitting data  this register can be used in conjunction with the control bit SPI_CTL.RXTCNTEN to set number of transactions to perform. Without this  the SPI interface.."
wgroup.long 0x20++0x3
line.long 0x0 "SPI_TX,FIFO Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register.A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register..For example  if DWIDTH is set to.."
rgroup.long 0x30++0x3
line.long 0x0 "SPI_RX,FIFO Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register.A read from this register pops data from the 8-level receive FIFO. Valid data is present if the SPI_STATUS. RXEMPTY bit is not set to 1. This is a read-only register."
tree.end
tree "SYS (System Global Control)"
base ad:0x50000000
rgroup.long 0x0++0x3
line.long 0x0 "SYS_PDID,Product ID"
hexmask.long 0x0 0.--31. 1. "PDID,Product Identifier.Chip identifier for ISD9300 series."
group.long 0x4++0xB
line.long 0x0 "SYS_RSTSTS,System Reset Source Register"
bitfld.long 0x0 10. "PORF,Power On Reset Flag.The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down..This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF  DPDRSTF  and WKRSTF" "0: No detected,1: A power on Reset has occurred"
bitfld.long 0x0 9. "DPDRSTF,Deep Power Down Reset Flag.The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function. .This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF  DPDRSTF  and WKRSTF" "0: No detected,1: A power on was triggered by DPD timer"
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bitfld.long 0x0 8. "WKRSTF,Wakeup Pin Reset Flag.The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin. .This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF  DPDRSTF  and.." "0: No detected,1: A power on was triggered by WAKEUP pin"
bitfld.long 0x0 7. "CPURF,Reset Source From CPU.The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a '1' to reset Cortex-M0 CPU kernel and Flash memory controller (FMC)..This bit is cleared by writing 1 to itself." "0: No reset from CPU,1: The Cortex-M0 CPU kernel and FMC has been reset.."
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bitfld.long 0x0 6. "PMURSTF,Reset Source From PMU.The PMURSTF flag is set if the PMU..This bit is cleared by writing 1 to itself." "0: No reset from PMU,1: PMU reset the system from a power down/standby.."
bitfld.long 0x0 5. "SYSRF,Reset Source From MCU.The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel..This bit is cleared by writing 1 to itself." "0: No reset from MCU,1: The Cortex_M0 MCU issued a reset signal to reset.."
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bitfld.long 0x0 2. "WDTRF,Reset Source From WDG.The WDTRF flag is set if pervious reset source originates from the Watch-Dog module..This bit is cleared by writing 1 to itself." "0: No reset from Watch-Dog,1: The Watch-Dog module issued the reset signal to.."
bitfld.long 0x0 0. "CORERSTF,Reset Source From CORE.The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR)  RESETn Pin Reset or PMU reset. .This bit is cleared by writing 1 to itself." "0: No reset from CORE,1: Core was reset by hardware block"
line.long 0x4 "SYS_IPRST0,IP Reset Control Resister0"
bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset.Set '1' will generate a reset signal to the PDMA Block. User needs to set this bit to '0' to release from the reset state." "0: Normal operation,1: PDMA IP reset"
bitfld.long 0x4 1. "CPURST,CPU Kernel One Shot Reset.Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC)  this bit will automatically return to '0' after the 2 clock cycles.This bit is a protected bit  to program first issue the unlock sequence (see.." "0: Normal,1: Reset CPU"
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bitfld.long 0x4 0. "CHIPRST,CHIP One Shot Reset.Set this bit will reset the whole chip  this bit will automatically return to '0' after the 2 clock cycles..CHIPRST has same behavior as POR reset  all the chip modules are reset and the chip configuration settings from flash.." "0: Normal,1: Reset CHIP"
line.long 0x8 "SYS_IPRST1,IP Reset Control Resister1"
bitfld.long 0x8 30. "ANARST,Analog Block Control Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 29. "I2S0RST,I2S Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 28. "EADCRST,ADC Controller Reset ." "0: Normal Operation,1: Reset"
bitfld.long 0x8 22. "ACMPRST,Analog Comparator Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 21. "PWM1RST,PWM1 Controller Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 20. "PWM0RST,PWM0 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 19. "CRCRST,CRC Generation Block Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 18. "BIQRST,Biquad Filter Block Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 13. "DPWMRST,DPWM Speaker Driver Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset." "0: Normal Operation,1: Reset"
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bitfld.long 0x8 7. "TMR1RST,Timer1 Controller Reset." "0: Normal Operation,1: Reset"
bitfld.long 0x8 6. "TMR0RST,Timer0 Controller Reset." "0: Normal Operation,1: Reset"
group.long 0x30++0xF
line.long 0x0 "SYS_PASMTEN,GPIOA input type control register"
bitfld.long 0x0 31. "SMTEN31,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 30. "SMTEN30,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 29. "SMTEN29,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 28. "SMTEN28,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 27. "SMTEN27,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 26. "SMTEN26,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 25. "SMTEN25,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 24. "SMTEN24,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 23. "SMTEN23,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 22. "SMTEN22,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 21. "SMTEN21,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 20. "SMTEN20,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 19. "SMTEN19,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 18. "SMTEN18,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
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bitfld.long 0x0 17. "SMTEN17,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
bitfld.long 0x0 16. "SMTEN16,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOA[15:0] I/O input Schmitt Trigger disabled,1: GPIOA[15:0] I/O input Schmitt Trigger enabled"
line.long 0x4 "SYS_PBSMTEN,GPIOB input type control register"
bitfld.long 0x4 23. "SMTEN23,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
bitfld.long 0x4 22. "SMTEN22,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
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bitfld.long 0x4 21. "SMTEN21,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
bitfld.long 0x4 20. "SMTEN20,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
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bitfld.long 0x4 19. "SMTEN19,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
bitfld.long 0x4 18. "SMTEN18,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
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bitfld.long 0x4 17. "SMTEN17,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
bitfld.long 0x4 16. "SMTEN16,Schmitt Trigger.This register controls whether the GPIO input buffer Schmitt trigger is enabled.." "0: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger..,1: GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger.."
line.long 0x8 "SYS_GPA_MFP,GPIOA multiple alternate functions control register"
bitfld.long 0x8 30.--31. "PA15MFP,Alternate Function Setting For PA15MFP." "0: GPIO,1: TM1,?,?"
bitfld.long 0x8 28.--29. "PA14MFP,Alternate Function Setting For PA14MFP." "0: GPIO,1: TM0,?,?"
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bitfld.long 0x8 26.--27. "PA13MFP,Alternate Function Setting For PA13MFP." "0: GPIO,1: PWM0CH1,?,?"
bitfld.long 0x8 24.--25. "PA12MFP,Alternate Function Setting For PA12MFP." "0: GPIO,1: PWM0CH0,?,?"
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bitfld.long 0x8 22.--23. "PA11MFP,Alternate Function Setting For PA11MFP." "0: GPIO,1: I2C_SCL,?,?"
bitfld.long 0x8 20.--21. "PA10MFP,Alternate Function Setting For PA10MFP." "0: GPIO,1: I2C_SDA,?,?"
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bitfld.long 0x8 18.--19. "PA9MFP,Alternate Function Setting For PA9MFP." "0: GPIO,1: UART_RX,?,?"
bitfld.long 0x8 16.--17. "PA8MFP,Alternate Function Setting For PA8MFP." "0: GPIO,1: UART_TX,?,?"
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bitfld.long 0x8 14.--15. "PA7MFP,Alternate Function Setting For PA7MFP." "0: GPIO,1: I2S_SDO,?,?"
bitfld.long 0x8 12.--13. "PA6MFP,Alternate Function Setting For PA6MFP." "0: GPIO,1: I2S_SDI,?,?"
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bitfld.long 0x8 10.--11. "PA5MFP,Alternate Function Setting For PA5MFP." "0: GPIO,1: I2S_BCLK,?,?"
bitfld.long 0x8 8.--9. "PA4MFP,Alternate Function Setting For PA4MFP." "0: GPIO,1: I2S_FS,?,?"
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bitfld.long 0x8 6.--7. "PA3MFP,Alternate Function Setting For PA3MFP." "0: GPIO,1: SPI_MISO0,?,?"
bitfld.long 0x8 4.--5. "PA2MFP,Alternate Function Setting For PA2MFP." "0: GPIO,1: SPI_SSB0,?,?"
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bitfld.long 0x8 2.--3. "PA1MFP,Alternate Function Setting For PA1MFP." "0: GPIO,1: SPI_SCLK,?,?"
bitfld.long 0x8 0.--1. "PA0MFP,Alternate Function Setting For PA0MFP." "0: GPIO,1: SPI_MOSI0,?,?"
line.long 0xC "SYS_GPB_MFP,GPIOB multiple alternate functions control register"
bitfld.long 0xC 30.--31. "PB15MFP,Alternate Function Setting For PB15MFP." "0: GPIO,1: PWM0CH3,?,?"
bitfld.long 0xC 28.--29. "PB14MFP,Alternate Function Setting For PB14MFP." "0: GPIO,1: PWM0CH2,?,?"
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bitfld.long 0xC 26.--27. "PB13MFP,Alternate Function Setting For PB13MFP." "0: GPIO,1: SPI_MOSI1,?,?"
bitfld.long 0xC 24.--25. "PB12MFP,Alternate Function Setting For PB12MFP." "0: GPIO,1: SPI_MISO1,?,?"
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bitfld.long 0xC 22.--23. "PB11MFP,Alternate Function Setting For PB11MFP." "0: GPIO,1: I2S_SDO,?,?"
bitfld.long 0xC 20.--21. "PB10MFP,Alternate Function Setting For PB10MFP." "0: GPIO,?,?,?"
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bitfld.long 0xC 18.--19. "PB9MFP,Alternate Function Setting For PB9MFP." "0: GPIO,1: I2S_BCLK(master),?,?"
bitfld.long 0xC 16.--17. "PB8MFP,Alternate Function Setting For PB8MFP." "0: GPIO,1: I2S_FS(master),?,?"
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bitfld.long 0xC 14.--15. "PB7MFP,Alternate Function Setting For PB7MFP." "0: GPIO,1: I2S_SDO,?,?"
bitfld.long 0xC 12.--13. "PB6MFP,Alternate Function Setting For PB6MFP." "0: GPIO,1: I2S_SDI,?,?"
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bitfld.long 0xC 10.--11. "PB5MFP,Alternate Function Setting For PB5MFP." "0: GPIO,1: PWM0CH1B,?,?"
bitfld.long 0xC 8.--9. "PB4MFP,Alternate Function Setting For PB4MFP." "0: GPIO,1: PWM0CH0B,?,?"
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bitfld.long 0xC 6.--7. "PB3MFP,Alternate Function Setting For PB3MFP." "0: GPIO,1: I2C_SDA,?,?"
bitfld.long 0xC 4.--5. "PB2MFP,Alternate Function Setting For PB2MFP." "0: GPIO,1: I2C_SCL,?,?"
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bitfld.long 0xC 2.--3. "PB1MFP,Alternate Function Setting For PB1MFP." "0: GPIO,1: MCLK,?,?"
bitfld.long 0xC 0.--1. "PB0MFP,Alternate Function Setting For PB0MFP." "0: GPIO,1: SPI_SSB1,?,?"
group.long 0x54++0x3
line.long 0x0 "SYS_WKCTL,WAKEUP pin control register"
bitfld.long 0x0 3. "WKDOUT,Wakeup Output State.Default set 0" "0,1"
bitfld.long 0x0 2. "WKOENB,Wakeup Pin Output Enable Bar." "0: drive WKDOUT to pin,1: tri-state (default)"
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bitfld.long 0x0 1. "WKPUEN,Wakeup Pin Pull-Up Control.This signal is latched in deep power down and preserved.." "0: pull-up enable,1: tri-state (default)"
bitfld.long 0x0 0. "WKDIN,State Of Wakeup Pin.Read only." "0,1"
group.long 0x100++0x3
line.long 0x0 "SYS_REGLCTL,Register Lock Control"
bitfld.long 0x0 0. "REGLCTL,Protected Register Unlock Register." "0: Protected registers are locked. Any write to the..,1: Protected registers are unlocked"
group.long 0x110++0x3
line.long 0x0 "SYS_IRCTCTL,Oscillator Frequency Adjustment control register"
bitfld.long 0x0 24. "RGE1SEL,Range Bit For Oscillator." "0: high range,1: low range"
hexmask.long.byte 0x0 16.--23. 1. "FREQ1SEL,Frequency Select.8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution."
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bitfld.long 0x0 8. "RGE0SEL,Range Bit For Oscillator." "0: high range,1: low range"
hexmask.long.byte 0x0 0.--7. 1. "FREQ0SEL,Frequency Select.8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution."
tree.end
tree "SYSINFO (System Control Registers)"
base ad:0xE000ED00
rgroup.long 0x0++0x3
line.long 0x0 "SYSCTL_CPUID,CPUID Base Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPCODE,Implementer Code Assigned By ARM.ARM aaa 0x41."
hexmask.long.byte 0x0 16.--19. 1. "PART,ARMv6-M Parts.Reads as 0xC for ARMv6-M parts"
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number.Reads as 0xC20."
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hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision.Reads as 0x0"
group.long 0x4++0x3
line.long 0x0 "SYSCTL_ICSR,Interrupt Control State Register"
bitfld.long 0x0 31. "NMIPNSET,NMI Pending Set Control.Setting this bit will activate an NMI. Since NMI is the highest priority exception  it will activate as soon as it is registered. Reads back with current state (1 if Pending  0 if not)." "0,1"
bitfld.long 0x0 28. "PPSVISET,Set A Pending PendSV Interrupt.This is normally used to request a context switch. Reads back with current state (1 if Pending  0 if not)." "0,1"
bitfld.long 0x0 27. "PPSVICLR,Clear A Pending PendSV Interrupt.Write 1 to clear a pending PendSV interrupt." "0,1"
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bitfld.long 0x0 26. "PSTKISET,Set A Pending SYST.Reads back with current state (1 if Pending  0 if not)." "0,1"
bitfld.long 0x0 25. "PSTKICLR,Clear A Pending SYST.Write 1 to clear a pending SYST." "0,1"
bitfld.long 0x0 23. "ISRPREEM,ISR Preemptive.If set  a pending exception will be serviced on exit from the debug halt state." "0,1"
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bitfld.long 0x0 22. "ISRPEND,ISR Pending.Indicates if an external configurable (NVIC generated) interrupt is pending." "0,1"
hexmask.long.word 0x0 12.--20. 1. "VTPEND,Vector Pending.Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value.."
hexmask.long.word 0x0 0.--8. 1. "VTACT,Vector Active.0: Thread mode.Value > 1: the exception number for the current executing exception."
group.long 0xC++0x7
line.long 0x0 "SYSCTL_AIRCTL,Application Interrupt and Reset Control Register"
hexmask.long.word 0x0 16.--31. 1. "VTKEY,Vector Key.The value 0x05FA must be written to this register  otherwise.a write to register is UNPREDICTABLE."
bitfld.long 0x0 15. "ENDIANES,Endianness.Read Only. Reads 0 indicating little endian machine." "0,1"
bitfld.long 0x0 2. "SRSTREQ,System Reset Request.Writing 1 to this bit asserts a signal to request a reset by the external system." "0: do not request a reset,1: request reset"
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bitfld.long 0x0 1. "CLRACTVT,Clear All Active Vector.Clears all active state information for fixed and configurable exceptions..The effect of writing a 1 to this bit if the processor is not halted in Debug  is UNPREDICTABLE." "0: do not clear state information,1: clear state information"
line.long 0x4 "SYSCTL_SCR,System Control Register"
bitfld.long 0x4 4. "SEVNONPN,Send Event On Pending Bit.When enabled  interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction..When an event or interrupt enters pending state  the event signal wakes up the processor.." "0: only enabled interrupts or events can wake-up..,1: enabled events and all interrupts including.."
bitfld.long 0x4 2. "SLPDEEP,Controls Whether The Processor Uses Sleep Or Deep Sleep As Its Low Power Mode.The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states." "0: sleep,1: deep sleep"
bitfld.long 0x4 1. "SLPONEXC,Sleep On Exception.When set to 1  the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset  the base level of execution. Setting this bit to 1 enables an interrupt driven.." "0,1"
group.long 0x1C++0x7
line.long 0x0 "SYSCTL_SHPR2,System Handler Priority Register 2"
bitfld.long 0x0 30.--31. "PRI11,Priority Of System Handler 11 - SVCall.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
line.long 0x4 "SYSCTL_SHPR3,System Handler Priority Register 3"
bitfld.long 0x4 30.--31. "PRI15,Priority Of System Handler 15 - SYST.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI14,Priority Of System Handler 14 - PendSV.'0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
tree.end
tree "SYSTICK (SysTick Timer)"
base ad:0xE000E010
group.long 0x0++0xB
line.long 0x0 "SYST_CSR,SYST Control and Status Register"
bitfld.long 0x0 16. "COUNTFLAG,Count Flag.Returns 1 if timer counted to 0 since last time this register was read.." "0: Cleared on read or by a write to the Current..,1: Set by a count transition from 1 to 0"
bitfld.long 0x0 2. "CLKSRC,Clock Source." "0: Clock selected from CLK_CLKSEL0.STCLKSEL is used..,1: Core clock used for SYST"
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bitfld.long 0x0 1. "TICKINT,Enables SYST Exception Request." "0: Counting down to 0 does not cause the SYST..,1: Counting down to 0 will cause SYST exception to.."
bitfld.long 0x0 0. "ENABLE,ENABLE." "0: The counter is disabled,1: The counter will operate in a multi-shot manner"
line.long 0x4 "SYST_RVR,SYST Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,SYST Reload.Value to load into the Current Value register when the counter reaches 0..To generate a multi-shot timer with a period of N processor clock cycles  use a RELOAD value of N-1. For example  if the SYST interrupt is required every 200.."
line.long 0x8 "SYST_CVR,SYST Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current Counter Value.This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear.."
tree.end
tree "TMR (Timer Controller)"
base ad:0x0
tree "TMR0"
base ad:0x40010000
group.long 0x0++0xF
line.long 0x0 "TIMERx_CTL,Timer Control and Status Register"
bitfld.long 0x0 30. "CNTEN,Counter Enable Bit.Note1: Setting CNTEN aaa 1 enables 24-bit counter. It continues count from last value..Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE aaa 00b) when the timer interrupt is generated (INTEN aaa 1b)." "0: Stops/Suspends counting,1: Starts counting"
bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit.If timer interrupt is enabled  the timer asserts its interrupt signal when the count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The timer is operating in the one-shot mode. The..,1: The timer is operating in the periodic mode. The..,2: RESERVED,3: The timer is operating in continuous counting.."
bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit.Set this bit will reset the timer counter  pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the counter status of timer.." "0: Timer is not active,1: Timer is active"
bitfld.long 0x0 16. "CNTDATEN,Data Latch Enable.When CNTDATEN is set  TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. ." "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Pre-Scale Counter.Clock input is divided by PSC+1 before it is fed to the counter. If PSC aaa 0  then there is no scaling."
line.long 0x4 "TIMERx_CMP,Timer Compare Register"
hexmask.long 0x4 0.--24. 1. "CMPDAT,Timer Comparison Value.CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value  a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN aaa 1. The CMPDAT.."
line.long 0x8 "TIMERx_INTSTS,Timer Interrupt Status Register"
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1." "0,1"
line.long 0xC "TIMERx_CNT,Timer Data Register"
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.When TIMERx_CTL.CNTDATEN is set to 1  the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value."
tree.end
tree "TMR1"
base ad:0x40010020
group.long 0x0++0xF
line.long 0x0 "TIMERx_CTL,Timer Control and Status Register"
bitfld.long 0x0 30. "CNTEN,Counter Enable Bit.Note1: Setting CNTEN aaa 1 enables 24-bit counter. It continues count from last value..Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE aaa 00b) when the timer interrupt is generated (INTEN aaa 1b)." "0: Stops/Suspends counting,1: Starts counting"
bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit.If timer interrupt is enabled  the timer asserts its interrupt signal when the count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The timer is operating in the one-shot mode. The..,1: The timer is operating in the periodic mode. The..,2: RESERVED,3: The timer is operating in continuous counting.."
bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit.Set this bit will reset the timer counter  pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 24-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only).This bit indicates the counter status of timer.." "0: Timer is not active,1: Timer is active"
bitfld.long 0x0 16. "CNTDATEN,Data Latch Enable.When CNTDATEN is set  TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting. ." "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Pre-Scale Counter.Clock input is divided by PSC+1 before it is fed to the counter. If PSC aaa 0  then there is no scaling."
line.long 0x4 "TIMERx_CMP,Timer Compare Register"
hexmask.long 0x4 0.--24. 1. "CMPDAT,Timer Comparison Value.CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value  a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN aaa 1. The CMPDAT.."
line.long 0x8 "TIMERx_INTSTS,Timer Interrupt Status Register"
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag.This bit indicates the interrupt status of Timer..TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1." "0,1"
line.long 0xC "TIMERx_CNT,Timer Data Register"
hexmask.long.tbyte 0xC 0.--23. 1. "CNT,Timer Data Register.When TIMERx_CTL.CNTDATEN is set to 1  the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value."
tree.end
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x40050000
group.long 0x0++0x33
line.long 0x0 "UART_DAT,UART0 Receive/Transfer FIFO Register."
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receive FIFO Register.Reading this register will return data from the receive data FIFO. By reading this register  the UART will return the 8-bit data received from Rx pin (LSB first)."
line.long 0x4 "UART_INTEN,UART0 Interrupt Enable Register."
bitfld.long 0x4 15. "DMARXEN,Receive DMA Enable.If enabled  the UART will request DMA service when data is available in receive FIFO." "0,1"
bitfld.long 0x4 14. "DMATXEN,Transmit DMA Enable .If enabled  the UART will request DMA service when space is available in transmit FIFO." "0,1"
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bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable .When CTS auto-flow is enabled  the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted)." "0: Disable CTS auto flow control,1: Enable"
bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable.When RTS auto-flow is enabled  if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV  the UART will de-assert the RTS signal." "0: Disable RTS auto flow control,1: Enable"
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bitfld.long 0x4 11. "TOCNTEN,Time-Out Counter Enable." "0: Disable Time-out counter,1: Enable"
bitfld.long 0x4 8. "LINIEN,LIN RX Break Field Detected Interrupt Enable." "0: Mask off Lin bus Rx break field interrupt,1: Enable Lin bus Rx break field interrupt"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable." "0: Mask off BUFERRINT,1: Enable IBUFERRINT"
bitfld.long 0x4 4. "RXTOIEN,Receive Time Out Interrupt Enable." "0: Mask off RXTOINT,1: Enable RXTOINT"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable." "0: Mask off MODEMINT,1: Enable MODEMINT"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable ." "0: Mask off RLSINT,1: Enable RLSINT"
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bitfld.long 0x4 1. "THREIEN,Transmit FIFO Register Empty Interrupt Enable." "0: Mask off THERINT,1: Enable THERINT"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable." "0: Mask off RDAINT,1: Enable RDAINT"
line.long 0x8 "UART_FIFO,UART0 FIFO Control Register."
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level For Auto-Flow Control.Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send)..Value : Trigger Level (Bytes).0 : 1.1.."
hexmask.long.byte 0x8 4.--7. 1. "RFITL,Receive FIFO Interrupt (RDAINT) Trigger Level .When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and  if enabled  an RDAINT interrupt will generated..Value : INTR_RDA Trigger Level.."
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bitfld.long 0x8 2. "TXRST,Transmit FIFO Reset.When TXRST is set  all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset..Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the transmit.."
bitfld.long 0x8 1. "RXRST,Receive FIFO Reset.When RXRST is set  all the bytes in the receive FIFO are cleared and receive internal state machine is reset..Note: This bit will auto-clear after 3 UART engine clock cycles." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the receiving.."
line.long 0xC "UART_LINE,UART0 Line Control Register."
bitfld.long 0xC 6. "BCB,Break Control Bit .When this bit is set to logic 1  the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic." "0,1"
bitfld.long 0xC 5. "SPE,Stick Parity Enable ." "0: Disable stick parity,1: When bits PBE and SPE are set 'Stick Parity' is.."
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bitfld.long 0xC 4. "EPE,Even Parity Enable.This bit has effect only when PBE (parity bit enable) is set." "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.."
bitfld.long 0xC 3. "PBE,Parity Bit Enable." "0: Parity bit is not generated (transmit data) or..,1: Parity bit is generated or checked between the.."
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bitfld.long 0xC 2. "NSB,Number Of STOP Bits." "0: One 'STOP bit' is generated after the..,1: Two 'STOP bits' are generated when 6- 7- and.."
bitfld.long 0xC 0.--1. "WLS,Word Length Select.0 (5bits)  1(6bits)  2(7bits)  3(8bits)" "0,1,2,3"
line.long 0x10 "UART_MODEM,UART0 Modem Control Register."
rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only).This bit is the pin status of RTS." "0,1"
bitfld.long 0x10 9. "RTSACTLV,Request-To-Send (RTS) Active Trigger Level.This bit can change the RTS trigger level.." "0: RTS is active low level,1: RTS is active high level"
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bitfld.long 0x10 4. "LBMEN,Loopback Mode Enable." "0: Disable,1: Enable"
bitfld.long 0x10 1. "RTS,RTS (Request-To-Send) Signal .If UART_INTEN.ATORTSEN aaa 0  this bit controls whether RTS pin is active or not.." "0: Drive RTS inactive ( aaa ~RTSACTLV),1: Drive RTS active ( aaa RTSACTLV)"
line.long 0x14 "UART_MODEMSTS,UART0 Modem Status Register."
bitfld.long 0x14 8. "CTSACTLV,Clear-To-Send (CTS) Active Trigger Level.This bit can change the CTS trigger level.." "0: CTS is active low level,1: CTS is active high level"
rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only).This bit is the pin status of CTS." "0,1"
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bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag.This bit is set whenever CTS input has state change. It will generate Modem interrupt to CPU when UART_INTEN.MODEMIEN aaa 1.NOTE: This bit is cleared by writing 1 to itself." "0,1"
line.long 0x18 "UART_FIFOSTS,UART0 FIFO Status Register."
rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty (Read Only).Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted..Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed..NOTE: This.." "0,1"
bitfld.long 0x18 24. "TXOVIF,Tx Overflow Error Interrupt Flag .If the Tx FIFO (UART_DAT) is full  an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled..NOTE: This bit is.." "0,1"
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rbitfld.long 0x18 23. "TXFULL,Transmit FIFO Full (Read Only).This bit indicates whether the Tx FIFO is full or not.." "0,1"
rbitfld.long 0x18 22. "TXEMPTY,Transmit FIFO Empty (Read Only).This bit indicates whether the Tx FIFO is empty or not..When the last byte of Tx FIFO has been transferred to Transmitter Shift Register  hardware sets this bit high. It will be cleared after writing data to FIFO.." "0,1"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,Tx FIFO Pointer (Read Only).This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO  TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register  TXPTR is decremented."
rbitfld.long 0x18 15. "RXFULL,Receive FIFO Full (Read Only).This bit indicates whether the Rx FIFO is full or not..This bit is set when Rx FIFO is full; otherwise it is cleared by hardware." "0,1"
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rbitfld.long 0x18 14. "RXEMPTY,Receive FIFO Empty (Read Only).This bit indicates whether the Rx FIFO is empty or not..When the last byte of Rx FIFO has been read by CPU  hardware sets this bit high. It will be cleared when UART receives any new data." "0,1"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,Rx FIFO Pointer (Read Only).This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device  RXPTR is incremented. When one byte of Rx FIFO is read by CPU .."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag.This bit is set to a logic 1 whenever the receive data input (Rx) is held in the 'space' state (logic 0) for longer than a full word transmission time (that is  the total time of start bit + data bits + parity + stop bits). It is.." "0,1"
bitfld.long 0x18 5. "FEF,Framing Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is  the stop bit following the last data bit or parity bit is detected as a logic 0)  and is reset whenever the CPU writes 1 to this.." "0,1"
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bitfld.long 0x18 4. "PEF,Parity Error Flag.This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'  and is reset whenever the CPU writes 1 to this bit." "0,1"
bitfld.long 0x18 0. "RXOVIF,Rx Overflow Error Interrupt Flag .If the Rx FIFO (UART_DAT) is full  and an additional byte is received by the UART  an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if.." "0,1"
line.long 0x1C "UART_INTSTS,UART0 Interrupt Status Register."
bitfld.long 0x1C 31. "DLININT,DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF." "0,1"
bitfld.long 0x1C 29. "DBERRINT,DMA MODE Buffer Error Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DBERRIF." "0,1"
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bitfld.long 0x1C 28. "DRXTOINT,DMA MODE Time Out Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRXTOIF." "0,1"
bitfld.long 0x1C 27. "DMODEMI,DMA MODE MODEM Status Interrupt Indicator To Interrupt.Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DMODENIF." "0,1"
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bitfld.long 0x1C 26. "DRLSINT,DMA MODE Receive Line Status Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF." "0,1"
bitfld.long 0x1C 23. "DLINIF,DMA MODE LIN Bus Rx Break Field Detected Flag.This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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rbitfld.long 0x1C 21. "DBERRIF,DMA MODE Buffer Error Interrupt Flag (Read Only).This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set  the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is.." "0,1"
rbitfld.long 0x1C 20. "DRXTOIF,DMA MODE Time Out Interrupt Flag (Read Only).This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be.." "0,1"
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rbitfld.long 0x1C 19. "DMODEMIF,DMA MODE MODEM Interrupt Flag (Read Only).NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
rbitfld.long 0x1C 18. "DRLSIF,DMA MODE Receive Line Status Interrupt Flag (Read Only).This bit is set when the Rx receive data has a parity  framing or break error (at least one of  UART_FIFOSTS.BIF  UART_FIFOSTS.FEF and UART_FIFOSTS.PEF  is set). If UART_INTEN.RLSIEN is.." "0,1"
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bitfld.long 0x1C 15. "LININT,LIN Bus Rx Break Field Detected Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.LINIEN and LINIF." "0,1"
bitfld.long 0x1C 13. "BUFERRINT,Buffer Error Interrupt Indicator To Interrupt Controller .Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF." "0,1"
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bitfld.long 0x1C 12. "RXTOINT,Time Out Interrupt Indicator To Interrupt Controller .Logical AND of UART_INTEN.RXTOIEN and RXTOIF." "0,1"
bitfld.long 0x1C 11. "MODEMINT,MODEM Status Interrupt Indicator To Interrupt .Logical AND of UART_INTEN.MODEMIEN and MODENIF." "0,1"
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bitfld.long 0x1C 10. "RLSINT,Receive Line Status Interrupt Indicator To Interrupt Controller .Logical AND of UART_INTEN.RLSIEN and RLSIF." "0,1"
bitfld.long 0x1C 9. "THERINT,Transmit Holding Register Empty Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.THREIEN and THREIF." "0,1"
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bitfld.long 0x1C 8. "RDAINT,Receive Data Available Interrupt Indicator To Interrupt Controller.Logical AND of UART_INTEN.RDAIEN and RDAIF." "0,1"
bitfld.long 0x1C 7. "LINIF,LIN Bus Rx Break Field Detected Flag.This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1." "0,1"
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rbitfld.long 0x1C 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only).This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set  the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a.." "0,1"
rbitfld.long 0x1C 4. "RXTOIF,Time Out Interrupt Flag (Read Only).This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated..NOTE: This.." "0,1"
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rbitfld.long 0x1C 3. "MODENIF,MODEM Interrupt Flag (Read Only).NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1." "0,1"
rbitfld.long 0x1C 2. "RLSIF,Receive Line Status Interrupt Flag (Read Only).This bit is set when the Rx receive data has a parity  framing or break error (at least one of  UART_FIFOSTS.BIF  UART_FIFOSTS.FEF and UART_FIFOSTS.PEF  is set). If UART_INTEN.RLSIEN is enabled  the.." "0,1"
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rbitfld.long 0x1C 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only).This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled  the THRE interrupt will be generated..NOTE: This bit is read.." "0,1"
rbitfld.long 0x1C 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only).When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled  the RDA interrupt will be generated. .NOTE: This bit is read only and it.." "0,1"
line.long 0x20 "UART_TOUT,UART0 Time Out Register"
hexmask.long.byte 0x20 0.--6. 1. "TOIC,Time Out Interrupt Comparator.The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC)  a receiver time out interrupt.."
line.long 0x24 "UART_BAUD,UART0 Baud Rate Divisor Register"
bitfld.long 0x24 29. "BAUDM1,Divider X Enable.The baud rate equation is: Baud Rate aaa UART_CLK / [ M * (BRD + 2) ] ; The default value of M is 16..Refer to Table 5111 for more information..NOTE: When in IrDA mode  this bit must disabled." "0: Disable divider X ( M aaa 16),1: Enable divider X (M aaa EDIVM1+1 with EDIVM1 >= 8)"
bitfld.long 0x24 28. "BAUDM0,Divider X Equal 1.0: M aaa EDIVM1+1  with restriction EDIVM1 >= 8..1: M aaa 1  with restriction BRD[15:0] >= 3..Refer to Table 5111 for more information." "0: M aaa EDIVM1+1,1: M aaa 1"
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hexmask.long.byte 0x24 24.--27. 1. "EDIVM1,Divider X.The baud rate divider M aaa EDIVM1+1."
hexmask.long.word 0x24 0.--15. 1. "BRD,Baud Rate Divider.Refer to Table 5111 for more information."
line.long 0x28 "UART_IRDA,UART0 IrDA Control Register."
bitfld.long 0x28 6. "RXINV,Receive Inversion Enable." "0: No inversion,1: Invert Rx input signal"
bitfld.long 0x28 5. "TXINV,Transmit Inversion Enable." "0: No inversion,1: Invert Tx output signal"
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bitfld.long 0x28 2. "LOOPBACK,IrDA Loopback Test Mode.Loopback Tx to Rx." "0,1"
bitfld.long 0x28 1. "TXEN,Transmit/Receive Selection." "0: Enable IrDA receiver,1: Enable IrDA transmitter"
line.long 0x2C "UART_ALTCTL,UART0 LIN Control Register."
bitfld.long 0x2C 7. "LINTXEN,LIN TX Break Mode Enable.NOTE: When Tx break field transfer operation finished  this bit will be cleared automatically." "0: Disable LIN Tx Break Mode,1: Enable LIN Tx Break Mode"
bitfld.long 0x2C 6. "LINRXEN,LIN RX Enable." "0: Disable LIN Rx mode,1: Enable LIN Rx mode"
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hexmask.long.byte 0x2C 0.--3. 1. "BRKFL,UART LIN Break Field Length Count.This field indicates a 4-bit LIN Tx break field count..NOTE: This break field length is BRKFL + 2"
line.long 0x30 "UART_FUNCSEL,UART0 Function Select Register."
bitfld.long 0x30 1. "IRDAEN,Enable IrDA Function." "0: UART Function,1: Enable IrDA Function"
bitfld.long 0x30 0. "LINEN,Enable LIN Function.Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time." "0: UART Function,1: Enable LIN Function"
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40004000
group.long 0x0++0x3
line.long 0x0 "WDT_CTL,Watchdog Timer Control Register"
bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Select.These three bits select the timeout interval for the Watchdog timer  a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:.Interrupt Timeout aaa 2^(2xTOUTSEL+4) x.." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable." "0: Disable the Watchdog timer (This action will..,1: Enable the Watchdog timer"
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bitfld.long 0x0 6. "INTEN,Watchdog Timer Interrupt Enable." "0: Disable the Watchdog timer interrupt,1: Enable the Watchdog timer interrupt"
bitfld.long 0x0 3. "IF,Watchdog Timer Interrupt Flag.If the Watchdog timer interrupt is enabled  then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled  then this bit indicates that a.." "0: Watchdog timer interrupt has not occurred,1: Watchdog timer interrupt has occurred"
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bitfld.long 0x0 2. "RSTF,Watchdog Timer Reset Flag.When the Watchdog timer initiates a reset  the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is.." "0: Watchdog timer reset has not occurred,1: Watchdog timer reset has occurred"
bitfld.long 0x0 1. "RSTEN,Watchdog Timer Reset Enable.Setting this bit will enable the Watchdog timer reset function.." "0: Disable Watchdog timer reset function,1: Enable Watchdog timer reset function"
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bitfld.long 0x0 0. "RSTCNT,Clear Watchdog Timer .Set this bit will clear the Watchdog timer. .NOTE: This bit will auto clear after few clock cycle" "0: Writing 0 to this bit has no effect,1: Reset the contents of the Watchdog timer"
tree.end
AUTOINDENT.OFF